diff options
| author | Daniel Mierswa <d.mierswa@phytec.de> | 2013-01-17 07:32:57 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-01-17 19:02:42 +0100 |
| commit | 0f7bff88f023aeeae6ded9c351600d7ced46103c (patch) | |
| tree | 02312814e1958f52c5d2ccab170ce217bb0c3d99 /arch/arm/mach-imx/clk-imx21.c | |
| parent | 1d37166cb2d4d11ea08a3566c6ceb6585c276f96 (diff) | |
| download | barebox-0f7bff88f023aeeae6ded9c351600d7ced46103c.tar.gz barebox-0f7bff88f023aeeae6ded9c351600d7ced46103c.tar.xz | |
i.MX21/27: don't enable lcd bus clocks too early
On the MX27 based board phycard-i.MX27 the display won't properly
come up.
Before removing imx-regs.h and the code that sets the register
in the i.MX video driver, the PCCR registers were set _after_
the screen start (LSSAR) was set.
This restores that old behaviour and makes the display come up
properly again.
I did not have a chance to test this on any other i.MX27 or i.MX21
hardware though I assume that the "old" order is required there
too.
Signed-off-by: Daniel Mierswa <d.mierswa@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx/clk-imx21.c')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx21.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c index 784951de1b..6e91424638 100644 --- a/arch/arm/mach-imx/clk-imx21.c +++ b/arch/arm/mach-imx/clk-imx21.c @@ -89,7 +89,8 @@ enum imx21_clks { ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1, - per2, per3, per4, usb_div, nfc_div, lcdc_per_gate, clk_max + per2, per3, per4, usb_div, nfc_div, lcdc_per_gate, lcdc_ahb_gate, + lcdc_ipg_gate, clk_max }; static struct clk *clks[clk_max]; @@ -116,7 +117,7 @@ static int imx21_ccm_probe(struct device_d *dev) PCCR0_CSPI1_EN | PCCR0_CSPI2_EN | PCCR0_SDHC1_EN | PCCR0_SDHC2_EN | PCCR0_GPIO_EN | PCCR0_I2C_EN | PCCR0_DMA_EN | PCCR0_USBOTG_EN | PCCR0_NFC_EN | PCCR0_PERCLK4_EN | - PCCR0_HCLK_USBOTG_EN | PCCR0_HCLK_LCDC_EN | PCCR0_HCLK_DMA_EN, + PCCR0_HCLK_USBOTG_EN | PCCR0_HCLK_DMA_EN, base + CCM_PCCR0); writel(PCCR1_CSPI3_EN | PCCR1_WDT_EN | PCCR1_GPT1_EN | PCCR1_GPT2_EN | @@ -143,6 +144,12 @@ static int imx21_ccm_probe(struct device_d *dev) clks[usb_div] = imx_clk_divider("usb_div", "spll", base + CCM_CSCR, 26, 3); clks[nfc_div] = imx_clk_divider("nfc_div", "ipg", base + CCM_PCDR0, 12, 4); clks[lcdc_per_gate] = imx_clk_gate("lcdc_per_gate", "per3", base + CCM_PCCR0, 18); + clks[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", base + CCM_PCCR0, 26); + /* + * i.MX21 doesn't have an IPG clock for the LCD. To avoid even more conditionals + * in the framebuffer code, provide a dummy clock. + */ + clks[lcdc_ipg_gate] = clk_fixed("dummy", 0); clkdev_add_physbase(clks[per1], MX21_GPT1_BASE_ADDR, NULL); clkdev_add_physbase(clks[per1], MX21_GPT2_BASE_ADDR, NULL); @@ -158,6 +165,8 @@ static int imx21_ccm_probe(struct device_d *dev) clkdev_add_physbase(clks[ipg], MX21_SDHC1_BASE_ADDR, NULL); clkdev_add_physbase(clks[ipg], MX21_SDHC2_BASE_ADDR, NULL); clkdev_add_physbase(clks[lcdc_per_gate], MX21_LCDC_BASE_ADDR, NULL); + clkdev_add_physbase(clks[lcdc_ahb_gate], MX21_LCDC_BASE_ADDR, "ahb"); + clkdev_add_physbase(clks[lcdc_ipg_gate], MX21_LCDC_BASE_ADDR, "ipg"); return 0; } |