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authorSascha Hauer <s.hauer@pengutronix.de>2014-05-06 11:10:45 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2014-05-09 17:41:45 +0200
commit1f0db00f81d9c1a52d573d1e1cfd9c7b30ce1580 (patch)
tree465dc55685b253be8b6d20ad021a2c22922b195e /arch/arm/mach-imx/clk-imx5.c
parent961a8298a6b777201e3c308d31269d83d30983af (diff)
downloadbarebox-1f0db00f81d9c1a52d573d1e1cfd9c7b30ce1580.tar.gz
barebox-1f0db00f81d9c1a52d573d1e1cfd9c7b30ce1580.tar.xz
ARM: i.MX53: Add pwm support
Aliases and clocks are needed to support the i.MX53 PWMs. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx/clk-imx5.c')
-rw-r--r--arch/arm/mach-imx/clk-imx5.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-imx5.c b/arch/arm/mach-imx/clk-imx5.c
index 9d536bc607..814635917f 100644
--- a/arch/arm/mach-imx/clk-imx5.c
+++ b/arch/arm/mach-imx/clk-imx5.c
@@ -209,6 +209,8 @@ int __init mx51_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigne
clkdev_add_physbase(clks[IMX5_CLK_ESDHC_C_SEL], MX51_MMC_SDHC3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_ESDHC_D_SEL], MX51_MMC_SDHC4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_IPG], MX51_ATA_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_PWM1_BASE_ADDR, "per");
+ clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_PWM2_BASE_ADDR, "per");
return 0;
}
@@ -272,6 +274,8 @@ int __init mx53_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigne
clkdev_add_physbase(clks[IMX5_CLK_ESDHC_B_PODF], MX53_ESDHC3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_ESDHC_D_SEL], MX53_ESDHC4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_AHB], MX53_SATA_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_PWM1_BASE_ADDR, "per");
+ clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_PWM2_BASE_ADDR, "per");
return 0;
}