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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2010-12-03 12:56:09 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2011-07-25 09:59:57 +0200 |
| commit | 3f57a5e5a5a58fa318953e5e538e3d1c67823315 (patch) | |
| tree | f3d8dda76a324f8407cd18282a88a38589450d70 /arch/arm/mach-imx/imx35.c | |
| parent | f4f952faa4047bfeb80ba6b960d331724807d52a (diff) | |
| download | barebox-3f57a5e5a5a58fa318953e5e538e3d1c67823315.tar.gz barebox-3f57a5e5a5a58fa318953e5e538e3d1c67823315.tar.xz | |
ARM i.MX35: Fix bogus L2 cache settings
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx/imx35.c')
| -rw-r--r-- | arch/arm/mach-imx/imx35.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c index 74d63eb1ba..5a0cff4f09 100644 --- a/arch/arm/mach-imx/imx35.c +++ b/arch/arm/mach-imx/imx35.c @@ -16,6 +16,7 @@ */ #include <common.h> +#include <init.h> #include <asm/io.h> #include <mach/imx-regs.h> #include <mach/iim.h> @@ -39,3 +40,21 @@ int imx_silicon_revision() return (reg & 0xFF); } + +/* + * There are some i.MX35 CPUs in the wild, comming with bogus L2 cache settings. + * These misconfigured CPUs will run amok immediately when the L2 cache gets + * enabled. Workaraound is to setup the correct register setting prior enabling + * the L2 cache. This should not hurt already working CPUs, as they are using the + * same value + */ + +#define L2_MEM_VAL 0x10 + +static int imx35_l2_fix(void) +{ + writel(0x515, IMX_CLKCTL_BASE + L2_MEM_VAL); + + return 0; +} +core_initcall(imx35_l2_fix); |