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authorAndrey Smirnov <andrew.smirnov@gmail.com>2016-03-15 20:33:48 -0700
committerSascha Hauer <s.hauer@pengutronix.de>2016-03-17 08:23:05 +0100
commit1414c55f825ca8f0721085425a4110fc89b7dbfc (patch)
tree52fdec5790cefe2a25dc17d209afa2534b8b2a1f /arch/arm/mach-imx/imx6.c
parentf65c093abc37aca0def4c99fd26fb7eec8006839 (diff)
downloadbarebox-1414c55f825ca8f0721085425a4110fc89b7dbfc.tar.gz
barebox-1414c55f825ca8f0721085425a4110fc89b7dbfc.tar.xz
L2x0: i.MX6: Replace magic numbers with constants
Use constants instead of magic numbers for PL301 registers bits in imx6_mmu_init() Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx/imx6.c')
-rw-r--r--arch/arm/mach-imx/imx6.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index f80334d71a..db1530c1d0 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -217,8 +217,10 @@ static int imx6_mmu_init(void)
/* configure the PREFETCH register */
val = readl(l2x0_base + L2X0_PREFETCH_CTRL);
- val |= 0x70800000;
-
+ val |= L2X0_DOUBLE_LINEFILL_EN |
+ L2X0_INSTRUCTION_PREFETCH_EN |
+ L2X0_DATA_PREFETCH_EN |
+ L2X0_INCR_DOUBLE_LINEFILL_EN;
/*
* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
@@ -229,7 +231,8 @@ static int imx6_mmu_init(void)
* double linefill feature. This is the default behavior.
*/
if (cpu_is_mx6q())
- val &= ~(1 << 30 | 1 << 23);
+ val &= ~(L2X0_DOUBLE_LINEFILL_EN |
+ L2X0_INCR_DOUBLE_LINEFILL_EN);
writel(val, l2x0_base + L2X0_PREFETCH_CTRL);