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author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-08-07 14:52:05 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-08-08 16:45:29 +0200 |
commit | 3a375c99af4aba38dfd55da13855545999dcb8ae (patch) | |
tree | f58253f67c4ca0d1a89c2c20eeeff40bfa54cef4 /arch/arm/mach-imx/imx6.c | |
parent | e6f08998224339437872a9fb4307b09f52f08e79 (diff) | |
download | barebox-3a375c99af4aba38dfd55da13855545999dcb8ae.tar.gz barebox-3a375c99af4aba38dfd55da13855545999dcb8ae.tar.xz |
ARM: i.MX6: Enable l2 cache
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx/imx6.c')
-rw-r--r-- | arch/arm/mach-imx/imx6.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index 7508964bf5..ceabe19dc2 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -22,6 +22,7 @@ #include <mach/imx6-anadig.h> #include <mach/imx6-regs.h> #include <mach/generic.h> +#include <asm/mmu.h> #define SI_REV 0x260 @@ -193,3 +194,37 @@ int imx6_devices_init(void) return 0; } + +#define L310_PREFETCH_CTRL 0xF60 + +static int imx6_mmu_init(void) +{ + void __iomem *l2x0_base = IOMEM(0x00a02000); + u32 val; + + if (!cpu_is_mx6()) + return 0; + + /* Configure the L2 PREFETCH and POWER registers */ + val = readl(l2x0_base + L310_PREFETCH_CTRL); + val |= 0x70800000; + + /* + * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 + * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 + * But according to ARM PL310 errata: 752271 + * ID: 752271: Double linefill feature can cause data corruption + * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 + * Workaround: The only workaround to this erratum is to disable the + * double linefill feature. This is the default behavior. + */ + if (cpu_is_mx6q()) + val &= ~(1 << 30 | 1 << 23); + + writel(val, l2x0_base + L310_PREFETCH_CTRL); + + l2x0_init(l2x0_base, 0x0, ~0UL); + + return 0; +} +postmmu_initcall(imx6_mmu_init); |