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authorLucas Stach <l.stach@pengutronix.de>2016-09-15 13:10:22 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2016-09-22 11:20:52 +0200
commit4e6e8f73e9aec6a9cbf4e37ab39a3154b01c2362 (patch)
treee150eece3234c5638d5fa0c2ff909f3670f18be7 /arch/arm/mach-imx/imx6.c
parent3386e25f2d60266bb25a3004f5cabf1277203551 (diff)
downloadbarebox-4e6e8f73e9aec6a9cbf4e37ab39a3154b01c2362.tar.gz
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ARM: imx6: don't execute IPU QoS setup on MX6 SX/SL
SX and SL variants only include the PXP and have no IPU, so skip any IPU related QoS setup. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx/imx6.c')
-rw-r--r--arch/arm/mach-imx/imx6.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 0138cc696b..a6cc5d39e5 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -99,6 +99,10 @@ void imx6_setup_ipu_qos(void)
void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR;
uint32_t val;
+ if (!cpu_mx6_is_mx6q() && !cpu_mx6_is_mx6d() &&
+ !cpu_mx6_is_mx6dl() && cpu_mx6_is_mx6s())
+ return;
+
val = readl(iomux + IOMUXC_GPR4);
val |= IMX6Q_GPR4_VPU_WR_CACHE_SEL | IMX6Q_GPR4_VPU_RD_CACHE_SEL |
IMX6Q_GPR4_VPU_P_WR_CACHE_VAL | IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |