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| author | Lucas Stach <l.stach@pengutronix.de> | 2016-09-15 13:10:23 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-09-22 11:20:52 +0200 |
| commit | b997cc26c22fa7a95f84f4ffed2c3a0ef596aea8 (patch) | |
| tree | 884ce3f0a7ce4d4ef7edb764c6c4261506ee5023 /arch/arm/mach-imx/imx6.c | |
| parent | 4e6e8f73e9aec6a9cbf4e37ab39a3154b01c2362 (diff) | |
| download | barebox-b997cc26c22fa7a95f84f4ffed2c3a0ef596aea8.tar.gz barebox-b997cc26c22fa7a95f84f4ffed2c3a0ef596aea8.tar.xz | |
ARM: imx6qp: set NoC regulator to bypass
The NoC regulator only passes the QoS signals through if it is
in bypass mode. This is a safe setting to give the IPU priority
over other requests. The kernel may change it to some other setting
once it knows the bandwidth requirements of the use-case.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx/imx6.c')
| -rw-r--r-- | arch/arm/mach-imx/imx6.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index a6cc5d39e5..1230215c2e 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -97,6 +97,7 @@ void imx6_init_lowlevel(void) void imx6_setup_ipu_qos(void) { void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR; + void __iomem *fast2 = (void *)MX6_FAST2_BASE_ADDR; uint32_t val; if (!cpu_mx6_is_mx6q() && !cpu_mx6_is_mx6d() && @@ -119,6 +120,16 @@ void imx6_setup_ipu_qos(void) val &= ~(IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK | IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK); val |= (0xf << 16) | (0x7 << 20); writel(val, iomux + IOMUXC_GPR7); + + /* + * On i.MX6 QP/DP the NoC regulator for the IPU ports needs to be in + * bypass mode for the above settings to take effect. + */ + if ((cpu_mx6_is_mx6q() || cpu_mx6_is_mx6d()) && + imx_silicon_revision() >= IMX_CHIP_REV_2_0) { + writel(0x2, fast2 + 0xb048c); + writel(0x2, fast2 + 0xb050c); + } } int imx6_init(void) |