ARM: i.MX8M: Add DDR controller support

This adds the DDR driver for the i.MX8MQ/i.MX8MM. It's taken from
U-Boot v2020.04-rc1 with slight modifications for barebox

The i.MX8MQ boards in the tree currently use the output of an earlier
version of the NXP i.MX8M DDR Tool which doesn't use a controller driver
but instead does most stuff in board code. It seems this can coexist
with the new driver, only a few helper functions that previously lived
in arch/arm/mach-imx/imx8-ddrc.c are now provided by the new driver.

Tested on an i.MX8MM EVK

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 0 insertions, 91 deletions

diff --git a/arch/arm/mach-imx/imx8-ddrc.c b/arch/arm/mach-imx/imx8-ddrc.c
deleted file mode 100644
index 8bb2672102..0000000000
--- a/arch/arm/mach-imx/imx8-ddrc.c
+++ /dev/null
@@ -1,91 +0,0 @@
-#include <common.h>
-#include <linux/iopoll.h>
-#include <mach/imx8-ddrc.h>
-#include <debug_ll.h>
-
-void ddrc_phy_load_firmware(void __iomem *phy,
-			    enum ddrc_phy_firmware_offset offset,
-			    const u16 *blob, size_t size)
-{
-	while (size) {
-		writew(*blob++, phy + DDRC_PHY_REG(offset));
-		offset++;
-		size -= sizeof(*blob);
-	}
-}
-
-enum pmc_constants {
-	PMC_MESSAGE_ID,
-	PMC_MESSAGE_STREAM,
-
-	PMC_TRAIN_SUCCESS	= 0x07,
-	PMC_TRAIN_STREAM_START	= 0x08,
-	PMC_TRAIN_FAIL		= 0xff,
-};
-
-static u32 ddrc_phy_get_message(void __iomem *phy, int type)
-{
-	u32 r, message;
-
-	/*
-	 * When BIT0 set to 0, the PMU has a message for the user
-	 * Wait for it indefinitely.
-	 */
-	readl_poll_timeout(phy + DDRC_PHY_REG(0xd0004),
-			   r, !(r & BIT(0)), 0);
-
-	switch (type) {
-	case PMC_MESSAGE_ID:
-		/*
-		 * Get the major message ID
-		 */
-		message = readl(phy + DDRC_PHY_REG(0xd0032));
-		break;
-	case PMC_MESSAGE_STREAM:
-		message = readl(phy + DDRC_PHY_REG(0xd0034));
-		message <<= 16;
-		message |= readl(phy + DDRC_PHY_REG(0xd0032));
-		break;
-	}
-
-	/*
-	 * By setting this register to 0, the user acknowledges the
-	 * receipt of the message.
-	 */
-	writel(0x00000000, phy + DDRC_PHY_REG(0xd0031));
-	/*
-	 * When BIT0 set to 0, the PMU has a message for the user
-	 */
-	readl_poll_timeout(phy + DDRC_PHY_REG(0xd0004),
-			   r, r & BIT(0), 0);
-
-	writel(0x00000001, phy + DDRC_PHY_REG(0xd0031));
-
-	return message;
-}
-
-static void ddrc_phy_fetch_streaming_message(void __iomem *phy)
-{
-	const u16 index = ddrc_phy_get_message(phy, PMC_MESSAGE_STREAM);
-	u16 i;
-
-	for (i = 0; i < index; i++)
-		ddrc_phy_get_message(phy, PMC_MESSAGE_STREAM);
-}
-
-void ddrc_phy_wait_training_complete(void __iomem *phy)
-{
-	for (;;) {
-		const u32 m = ddrc_phy_get_message(phy, PMC_MESSAGE_ID);
-
-		switch (m) {
-		case PMC_TRAIN_STREAM_START:
-			ddrc_phy_fetch_streaming_message(phy);
-			break;
-		case PMC_TRAIN_SUCCESS:
-			return;
-		case PMC_TRAIN_FAIL:
-			hang();
-		}
-	}
-}