ARM i.MX31: add SPI support

The i.MX31 SPI interface was refered by freescale as spi_ver_0_4 in one
of their older vendor extended linux releases. spi_ver_0_4 differs only
in minor aspects to spi_ver_0_7 (i.MX35) which is already supported by
barebox.
Regarding barebox, the differences boil down to the location and length
of the CHIP SELECT and BIT COUNT/BURST LENGTH elements of CONREG. The
spi_ver_0_4 variant is limited to single word bursts with a maximum of
32 bits_per_word.

Add support for the i.MX31 SPI interface to the barebox spi_ver_0_7
implementation.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 3 insertions, 3 deletions

diff --git a/arch/arm/mach-imx/include/mach/devices-imx31.h b/arch/arm/mach-imx/include/mach/devices-imx31.h
index 63319fea37..7c70e40f9d 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx31.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx31.h
@@ -4,17 +4,17 @@
 
 static inline struct device_d *imx31_add_spi0(struct spi_imx_master *pdata)
 {
-	return imx_add_spi_imx27((void *)MX31_CSPI1_BASE_ADDR, 0, pdata);
+	return imx_add_spi_imx35((void *)MX31_CSPI1_BASE_ADDR, 0, pdata);
 }
 
 static inline struct device_d *imx31_add_spi1(struct spi_imx_master *pdata)
 {
-	return imx_add_spi_imx27((void *)MX31_CSPI2_BASE_ADDR, 1, pdata);
+	return imx_add_spi_imx35((void *)MX31_CSPI2_BASE_ADDR, 1, pdata);
 }
 
 static inline struct device_d *imx31_add_spi2(struct spi_imx_master *pdata)
 {
-	return imx_add_spi_imx27((void *)MX31_CSPI3_BASE_ADDR, 2, pdata);
+	return imx_add_spi_imx35((void *)MX31_CSPI3_BASE_ADDR, 2, pdata);
 }
 
 static inline struct device_d *imx31_add_uart0(void)