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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-09-23 21:36:29 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-10-04 15:19:53 +0200 |
| commit | a36a8f5d1b2a4031e12a204d01185c07d42561f5 (patch) | |
| tree | a6116f90e9c731a5534490777da3c18ce7812291 /arch/arm/mach-imx/include/mach/imx1-regs.h | |
| parent | 8b88e6dadb60d3aa4beb8c591a5be8b54f9f1fe8 (diff) | |
| download | barebox-a36a8f5d1b2a4031e12a204d01185c07d42561f5.tar.gz barebox-a36a8f5d1b2a4031e12a204d01185c07d42561f5.tar.xz | |
ARM i.MX1: Add function to setup chipselect
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx/include/mach/imx1-regs.h')
| -rw-r--r-- | arch/arm/mach-imx/include/mach/imx1-regs.h | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/arch/arm/mach-imx/include/mach/imx1-regs.h b/arch/arm/mach-imx/include/mach/imx1-regs.h index 0e07dcd236..cb60c84d31 100644 --- a/arch/arm/mach-imx/include/mach/imx1-regs.h +++ b/arch/arm/mach-imx/include/mach/imx1-regs.h @@ -86,21 +86,6 @@ #define CSCR_MPLL_RESTART (1<<21) -/* Chip Select Registers */ -#define CS0U __REG(MX1_EIM_BASE_ADDR) /* Chip Select 0 Upper Register */ -#define CS0L __REG(MX1_EIM_BASE_ADDR + 0x4) /* Chip Select 0 Lower Register */ -#define CS1U __REG(MX1_EIM_BASE_ADDR + 0x8) /* Chip Select 1 Upper Register */ -#define CS1L __REG(MX1_EIM_BASE_ADDR + 0xc) /* Chip Select 1 Lower Register */ -#define CS2U __REG(MX1_EIM_BASE_ADDR + 0x10) /* Chip Select 2 Upper Register */ -#define CS2L __REG(MX1_EIM_BASE_ADDR + 0x14) /* Chip Select 2 Lower Register */ -#define CS3U __REG(MX1_EIM_BASE_ADDR + 0x18) /* Chip Select 3 Upper Register */ -#define CS3L __REG(MX1_EIM_BASE_ADDR + 0x1c) /* Chip Select 3 Lower Register */ -#define CS4U __REG(MX1_EIM_BASE_ADDR + 0x20) /* Chip Select 4 Upper Register */ -#define CS4L __REG(MX1_EIM_BASE_ADDR + 0x24) /* Chip Select 4 Lower Register */ -#define CS5U __REG(MX1_EIM_BASE_ADDR + 0x28) /* Chip Select 5 Upper Register */ -#define CS5L __REG(MX1_EIM_BASE_ADDR + 0x2c) /* Chip Select 5 Lower Register */ -#define EIM __REG(MX1_EIM_BASE_ADDR + 0x30) /* EIM Configuration Register */ - /* assignements for GPIO alternate/primary functions */ /* FIXME: This list is not completed. The correct directions are |