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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2010-11-02 17:02:04 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-11-02 18:11:03 +0100 |
| commit | aaf125fa8141249d5e52969ce3d31913fceb6194 (patch) | |
| tree | 145be3b6a11f49f170bdac777f7ced7e9da4634b /arch/arm/mach-imx/include/mach/imx51-regs.h | |
| parent | 3d4f24ef0bc1d00577b87ec216cec61bbf34a4ec (diff) | |
| download | barebox-aaf125fa8141249d5e52969ce3d31913fceb6194.tar.gz barebox-aaf125fa8141249d5e52969ce3d31913fceb6194.tar.xz | |
ARM i.MX51: Add SPBA0 base addresses
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx/include/mach/imx51-regs.h')
| -rw-r--r-- | arch/arm/mach-imx/include/mach/imx51-regs.h | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/include/mach/imx51-regs.h b/arch/arm/mach-imx/include/mach/imx51-regs.h index 1719a787c5..1d241c89b3 100644 --- a/arch/arm/mach-imx/include/mach/imx51-regs.h +++ b/arch/arm/mach-imx/include/mach/imx51-regs.h @@ -91,7 +91,18 @@ #define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000) #define MX51_SPBA0_BASE_ADDR 0x70000000 -#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000) +#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000) +#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000) +#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000) +#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000) +#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000) +#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000) +#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000) +#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00028000) +#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00030000) +#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00034000) +#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00038000) +#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000) /* * Memory regions and CS |