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| author | Christian Hemp <c.hemp@phytec.de> | 2014-04-25 13:54:25 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-04-28 08:09:31 +0200 |
| commit | 3858b933b504f44562d6c2cd2251aed7828637ff (patch) | |
| tree | defd8c52c847ca057127078bf7af2a85ac35b090 /arch/arm/mach-imx/include/mach/imx6-mmdc.h | |
| parent | fca64d3fda866ba1f9dd5650ef37e613767ed07f (diff) | |
| download | barebox-3858b933b504f44562d6c2cd2251aed7828637ff.tar.gz barebox-3858b933b504f44562d6c2cd2251aed7828637ff.tar.xz | |
imx6:mmdc: Move register defines to header file
Move mmdc register defines to mmdc header file.
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx/include/mach/imx6-mmdc.h')
| -rw-r--r-- | arch/arm/mach-imx/include/mach/imx6-mmdc.h | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/include/mach/imx6-mmdc.h b/arch/arm/mach-imx/include/mach/imx6-mmdc.h index 4ad939eaea..3152e1673c 100644 --- a/arch/arm/mach-imx/include/mach/imx6-mmdc.h +++ b/arch/arm/mach-imx/include/mach/imx6-mmdc.h @@ -1,6 +1,45 @@ #ifndef __MACH_MMDC_H #define __MACH_MMDC_H + +#define P0_IPS (void __iomem *)MX6_MMDC_P0_BASE_ADDR +#define P1_IPS (void __iomem *)MX6_MMDC_P1_BASE_ADDR + +#define MDCTL 0x000 +#define MDPDC 0x004 +#define MDSCR 0x01c +#define MDMISC 0x018 +#define MDREF 0x020 +#define MAPSR 0x404 +#define MPZQHWCTRL 0x800 +#define MPWLGCR 0x808 +#define MPWLDECTRL0 0x80c +#define MPWLDECTRL1 0x810 +#define MPPDCMPR1 0x88c +#define MPSWDAR 0x894 +#define MPRDDLCTL 0x848 +#define MPMUR 0x8b8 +#define MPDGCTRL0 0x83c +#define MPDGCTRL1 0x840 +#define MPRDDLCTL 0x848 +#define MPWRDLCTL 0x850 +#define MPRDDLHWCTL 0x860 +#define MPWRDLHWCTL 0x864 +#define MPDGHWST0 0x87c +#define MPDGHWST1 0x880 +#define MPDGHWST2 0x884 +#define MPDGHWST3 0x888 + +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x5a8) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x5b0) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x524) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x51c) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x518) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x50c) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x5b8) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x5c0) + + int mmdc_do_write_level_calibration(void); int mmdc_do_dqs_calibration(void); |