diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2020-02-14 11:53:38 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-02-19 08:30:32 +0100 |
| commit | 0266042714b2e0a17e397fe5d8a29a4487785df4 (patch) | |
| tree | 3ec6d49a15181e40d14ef2349afdbd84438acd2d /arch/arm/mach-imx/include | |
| parent | 5973ed7e2196aac7df53f81033cd46b51acba09c (diff) | |
| download | barebox-0266042714b2e0a17e397fe5d8a29a4487785df4.tar.gz barebox-0266042714b2e0a17e397fe5d8a29a4487785df4.tar.xz | |
ARM: i.MX8M: Add DDR controller support
This adds the DDR driver for the i.MX8MQ/i.MX8MM. It's taken from
U-Boot v2020.04-rc1 with slight modifications for barebox
The i.MX8MQ boards in the tree currently use the output of an earlier
version of the NXP i.MX8M DDR Tool which doesn't use a controller driver
but instead does most stuff in board code. It seems this can coexist
with the new driver, only a few helper functions that previously lived
in arch/arm/mach-imx/imx8-ddrc.c are now provided by the new driver.
Tested on an i.MX8MM EVK
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx/include')
| -rw-r--r-- | arch/arm/mach-imx/include/mach/imx8-ddrc.h | 66 |
1 files changed, 0 insertions, 66 deletions
diff --git a/arch/arm/mach-imx/include/mach/imx8-ddrc.h b/arch/arm/mach-imx/include/mach/imx8-ddrc.h deleted file mode 100644 index d49e29f263..0000000000 --- a/arch/arm/mach-imx/include/mach/imx8-ddrc.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef __IMX8_DDRC_H__ -#define __IMX8_DDRC_H__ - -#include <mach/imx8mq-regs.h> -#include <io.h> -#include <firmware.h> -#include <linux/compiler.h> - -enum ddrc_phy_firmware_offset { - DDRC_PHY_IMEM = 0x00050000U, - DDRC_PHY_DMEM = 0x00054000U, -}; - -void ddrc_phy_load_firmware(void __iomem *, - enum ddrc_phy_firmware_offset, - const u16 *, size_t); - -#define DDRC_PHY_REG(x) ((x) * 4) - -void ddrc_phy_wait_training_complete(void __iomem *phy); - - -/* - * i.MX8M DDR Tool compatibility layer - */ - -#define reg32_write(a, v) writel(v, a) -#define reg32_read(a) readl(a) - -static inline void wait_ddrphy_training_complete(void) -{ - ddrc_phy_wait_training_complete(IOMEM(MX8MQ_DDRC_PHY_BASE_ADDR)); -} - -#define __ddr_load_train_code(imem, dmem) \ - do { \ - const u16 *__mem; \ - size_t __size; \ - \ - get_builtin_firmware(imem, &__mem, &__size); \ - ddrc_phy_load_firmware(IOMEM(MX8MQ_DDRC_PHY_BASE_ADDR), \ - DDRC_PHY_IMEM, __mem, __size); \ - \ - get_builtin_firmware(dmem, &__mem, &__size); \ - ddrc_phy_load_firmware(IOMEM(MX8MQ_DDRC_PHY_BASE_ADDR), \ - DDRC_PHY_DMEM, __mem, __size); \ - } while (0) - -#define ddr_load_train_code(imem_dmem) __ddr_load_train_code(imem_dmem) - -#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + (X * 0x2000000)) - -#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) -#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18) -#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30) -#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60) -#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc) -#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0) -#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc) -#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320) -#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324) -#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490) - -#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) - -#endif
\ No newline at end of file |