ARM i.MX35: give register base addresses a proper MX35_ prefix

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

4 files changed, 162 insertions, 79 deletions

diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c
index 579e14814d..2e94f175e6 100644
--- a/arch/arm/mach-imx/imx35.c
+++ b/arch/arm/mach-imx/imx35.c
@@ -22,7 +22,7 @@
 int imx_silicon_revision()
 {
 	uint32_t reg;
-	reg = readl(IMX_IIM_BASE + IIM_SREV);
+	reg = readl(MX35_IIM_BASE_ADDR + IIM_SREV);
 	/* 0×00 = TO 1.0, First silicon */
 	reg += IMX_CHIP_REV_1_0;
 
@@ -41,7 +41,7 @@ int imx_silicon_revision()
 
 static int imx35_l2_fix(void)
 {
-	writel(0x515, IMX_CLKCTL_BASE + L2_MEM_VAL);
+	writel(0x515, MX35_CLKCTL_BASE_ADDR + L2_MEM_VAL);
 
 	return 0;
 }
@@ -49,13 +49,13 @@ core_initcall(imx35_l2_fix);
 
 static int imx35_init(void)
 {
-	add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K,
+	add_generic_device("imx_iim", 0, NULL, MX35_IIM_BASE_ADDR, SZ_4K,
 			IORESOURCE_MEM, NULL);
 
-	add_generic_device("imx31-gpt", 0, NULL, 0x53f90000, 0x100, IORESOURCE_MEM, NULL);
-	add_generic_device("imx31-gpio", 0, NULL, 0x53fcc000, 0x1000, IORESOURCE_MEM, NULL);
-	add_generic_device("imx31-gpio", 1, NULL, 0x53fd0000, 0x1000, IORESOURCE_MEM, NULL);
-	add_generic_device("imx31-gpio", 2, NULL, 0x53fa4000, 0x1000, IORESOURCE_MEM, NULL);
+	add_generic_device("imx31-gpt", 0, NULL, MX35_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+	add_generic_device("imx-gpio", 0, NULL, MX35_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+	add_generic_device("imx-gpio", 1, NULL, MX35_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+	add_generic_device("imx-gpio", 2, NULL, MX35_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
 
 	return 0;
 }
diff --git a/arch/arm/mach-imx/include/mach/devices-imx35.h b/arch/arm/mach-imx/include/mach/devices-imx35.h
index 9ecaa35ffe..27c49e7161 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx35.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx35.h
@@ -3,60 +3,70 @@
 
 static inline struct device_d *imx35_add_i2c0(struct i2c_platform_data *pdata)
 {
-	return imx_add_i2c((void *)IMX_I2C1_BASE, 0, pdata);
+	return imx_add_i2c((void *)MX35_I2C1_BASE_ADDR, 0, pdata);
 }
 
 static inline struct device_d *imx35_add_i2c1(struct i2c_platform_data *pdata)
 {
-	return imx_add_i2c((void *)IMX_I2C2_BASE, 1, pdata);
+	return imx_add_i2c((void *)MX35_I2C2_BASE_ADDR, 1, pdata);
 }
 
 static inline struct device_d *imx35_add_i2c2(struct i2c_platform_data *pdata)
 {
-	return imx_add_i2c((void *)IMX_I2C3_BASE, 2, pdata);
+	return imx_add_i2c((void *)MX35_I2C3_BASE_ADDR, 2, pdata);
 }
 
 static inline struct device_d *imx35_add_spi0(struct spi_imx_master *pdata)
 {
-	return imx_add_spi((void *)IMX_CSPI1_BASE, 0, pdata);
+	return imx_add_spi((void *)MX35_CSPI1_BASE_ADDR, 0, pdata);
+}
+
+static inline struct device_d *imx35_add_spi(struct spi_imx_master *pdata)
+{
+	return imx_add_spi((void *)MX35_CSPI2_BASE_ADDR, 1, pdata);
 }
 
 static inline struct device_d *imx35_add_uart0(void)
 {
-	return imx_add_uart((void *)IMX_UART1_BASE, 0);
+	return imx_add_uart((void *)MX35_UART1_BASE_ADDR, 0);
 }
 
 static inline struct device_d *imx35_add_uart1(void)
 {
-	return imx_add_uart((void *)IMX_UART2_BASE, 1);
+	return imx_add_uart((void *)MX35_UART2_BASE_ADDR, 1);
+}
+
+static inline struct device_d *imx35_add_uart2(void)
+{
+	return imx_add_uart((void *)MX35_UART3_BASE_ADDR, 2);
 }
 
 static inline struct device_d *imx35_add_nand(struct imx_nand_platform_data *pdata)
 {
-	return imx_add_nand((void *)IMX_NFC_BASE, pdata);
+	return imx_add_nand((void *)MX35_NFC_BASE_ADDR, pdata);
 }
 
 static inline struct device_d *imx35_add_fb(struct imx_ipu_fb_platform_data *pdata)
 {
-	return imx_add_ipufb((void *)IMX_IPU_BASE, pdata);
+	return imx_add_ipufb((void *)MX35_IPU_CTRL_BASE_ADDR, pdata);
 }
 
 static inline struct device_d *imx35_add_fec(struct fec_platform_data *pdata)
 {
-	return imx_add_fec((void *)IMX_FEC_BASE, pdata);
+	return imx_add_fec((void *)MX35_FEC_BASE_ADDR, pdata);
 }
 
 static inline struct device_d *imx35_add_mmc0(struct esdhc_platform_data *pdata)
 {
-	return imx_add_esdhc((void *)IMX_SDHC1_BASE, 0, pdata);
+	return imx_add_esdhc((void *)MX35_ESDHC1_BASE_ADDR, 0, pdata);
 }
 
 static inline struct device_d *imx35_add_mmc1(struct esdhc_platform_data *pdata)
 {
-	return imx_add_esdhc((void *)IMX_SDHC2_BASE, 1, pdata);
+	return imx_add_esdhc((void *)MX35_ESDHC2_BASE_ADDR, 1, pdata);
 }
 
 static inline struct device_d *imx35_add_mmc2(struct esdhc_platform_data *pdata)
 {
-	return imx_add_esdhc((void *)IMX_SDHC3_BASE, 2, pdata);
+	return imx_add_esdhc((void *)MX35_ESDHC3_BASE_ADDR, 2, pdata);
 }
diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h
index 5a4ab90082..8c6833875b 100644
--- a/arch/arm/mach-imx/include/mach/imx35-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx35-regs.h
@@ -19,6 +19,8 @@
 #ifndef __ASM_ARCH_MX35_REGS_H
 #define __ASM_ARCH_MX35_REGS_H
 
+#include <sizes.h>
+
 /*
  * sanity check
  */
@@ -26,32 +28,122 @@
 # error "Please do not include directly. Use imx-regs.h instead."
 #endif
 
-#define IMX_L2CC_BASE		0x30000000
-#define IMX_CLKCTL_BASE		0x43F0C000
-#define IMX_UART1_BASE		0x43F90000
-#define IMX_UART2_BASE		0x43F94000
-#define IMX_TIM1_BASE		0x53F90000
-#define IMX_IOMUXC_BASE		0x43FAC000
-#define IMX_WDT_BASE		0x53FDC000
-#define IMX_MAX_BASE		0x43F04000
-#define IMX_ESD_BASE		0xb8001000
-#define IMX_AIPS1_BASE		0x43F00000
-#define IMX_AIPS2_BASE		0x53F00000
-#define IMX_CCM_BASE		0x53F80000
-#define IMX_IIM_BASE		0x53FF0000
-#define IMX_M3IF_BASE		0xB8003000
-#define IMX_NFC_BASE		0xBB000000
-#define IMX_FEC_BASE		0x50038000
-#define IMX_I2C1_BASE		0x43F80000
-#define IMX_I2C2_BASE		0x43F98000
-#define IMX_I2C3_BASE		0x43F84000
-#define IMX_CSPI1_BASE		0x43FA4000
-#define IMX_SDHC1_BASE		0x53FB4000
-#define IMX_SDHC2_BASE		0x53FB8000
-#define IMX_SDHC3_BASE		0x53FBC000
-#define IMX_IPU_BASE		0x53FC0000
-#define IMX_OTG_BASE		0x53FF4000
-#define IMX_WDOG_BASE		0x53fdc000
+#define MX35_IRAM_BASE_ADDR		0x10000000	/* internal ram */
+#define MX35_IRAM_SIZE			SZ_128K
+
+#define MX35_L2CC_BASE_ADDR		0x30000000
+#define MX35_L2CC_SIZE			SZ_1M
+
+#define MX35_AIPS1_BASE_ADDR		0x43f00000
+#define MX35_AIPS1_SIZE			SZ_1M
+#define MX35_MAX_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x04000)
+#define MX35_EVTMON_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x08000)
+#define MX35_CLKCTL_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x0c000)
+#define MX35_ETB_SLOT4_BASE_ADDR		(MX35_AIPS1_BASE_ADDR + 0x10000)
+#define MX35_ETB_SLOT5_BASE_ADDR		(MX35_AIPS1_BASE_ADDR + 0x14000)
+#define MX35_ECT_CTIO_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x18000)
+#define MX35_I2C1_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x80000)
+#define MX35_I2C3_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x84000)
+#define MX35_UART1_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x90000)
+#define MX35_UART2_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x94000)
+#define MX35_I2C2_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x98000)
+#define MX35_OWIRE_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x9c000)
+#define MX35_SSI1_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0xa0000)
+#define MX35_CSPI1_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0xa4000)
+#define MX35_KPP_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0xa8000)
+#define MX35_IOMUXC_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0xac000)
+#define MX35_ECT_IP1_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0xb8000)
+#define MX35_ECT_IP2_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0xbc000)
+
+#define MX35_SPBA0_BASE_ADDR		0x50000000
+#define MX35_SPBA0_SIZE			SZ_1M
+#define MX35_UART3_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x0c000)
+#define MX35_CSPI2_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x10000)
+#define MX35_SSI2_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x14000)
+#define MX35_ATA_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x20000)
+#define MX35_MSHC1_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x24000)
+#define MX35_FEC_BASE_ADDR		0x50038000
+#define MX35_SPBA_CTRL_BASE_ADDR		(MX35_SPBA0_BASE_ADDR + 0x3c000)
+
+#define MX35_AIPS2_BASE_ADDR		0x53f00000
+#define MX35_AIPS2_SIZE			SZ_1M
+#define MX35_CCM_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0x80000)
+#define MX35_GPT1_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0x90000)
+#define MX35_EPIT1_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0x94000)
+#define MX35_EPIT2_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0x98000)
+#define MX35_GPIO3_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xa4000)
+#define MX35_SCC_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xac000)
+#define MX35_RNGA_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xb0000)
+#define MX35_ESDHC1_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xb4000)
+#define MX35_ESDHC2_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xb8000)
+#define MX35_ESDHC3_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xbc000)
+#define MX35_IPU_CTRL_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xc0000)
+#define MX35_AUDMUX_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xc4000)
+#define MX35_GPIO1_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xcc000)
+#define MX35_GPIO2_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xd0000)
+#define MX35_SDMA_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xd4000)
+#define MX35_RTC_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xd8000)
+#define MX35_WDOG_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xdc000)
+#define MX35_PWM_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xe0000)
+#define MX35_CAN1_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xe4000)
+#define MX35_CAN2_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xe8000)
+#define MX35_RTIC_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xec000)
+#define MX35_IIM_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xf0000)
+#define MX35_USB_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xf4000)
+#define MX35_USB_OTG_BASE_ADDR			(MX35_USB_BASE_ADDR + 0x0000)
+
+/*
+ * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for
+ * HS.  When host support was implemented only a preliminary document was
+ * available, which told 0x400.  This works fine.
+ */
+#define MX35_USB_HS_BASE_ADDR			(MX35_USB_BASE_ADDR + 0x0400)
+
+#define MX35_ROMP_BASE_ADDR		0x60000000
+#define MX35_ROMP_SIZE			SZ_1M
+
+#define MX35_AVIC_BASE_ADDR		0x68000000
+#define MX35_AVIC_SIZE			SZ_1M
+
+/*
+ * Memory regions and CS
+ */
+#define MX35_IPU_MEM_BASE_ADDR		0x70000000
+#define MX35_CSD0_BASE_ADDR		0x80000000
+#define MX35_CSD1_BASE_ADDR		0x90000000
+
+#define MX35_CS0_BASE_ADDR		0xa0000000
+#define MX35_CS1_BASE_ADDR		0xa8000000
+#define MX35_CS2_BASE_ADDR		0xb0000000
+#define MX35_CS3_BASE_ADDR		0xb2000000
+
+#define MX35_CS4_BASE_ADDR		0xb4000000
+#define MX35_CS4_SIZE			SZ_32M
+
+#define MX35_CS5_BASE_ADDR		0xb6000000
+#define MX35_CS5_SIZE			SZ_32M
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define MX35_X_MEMC_BASE_ADDR		0xb8000000
+#define MX35_X_MEMC_SIZE		SZ_64K
+#define MX35_ESDCTL_BASE_ADDR			(MX35_X_MEMC_BASE_ADDR + 0x1000)
+#define MX35_WEIM_BASE_ADDR			(MX35_X_MEMC_BASE_ADDR + 0x2000)
+#define MX35_M3IF_BASE_ADDR			(MX35_X_MEMC_BASE_ADDR + 0x3000)
+#define MX35_EMI_CTL_BASE_ADDR			(MX35_X_MEMC_BASE_ADDR + 0x4000)
+#define MX35_PCMCIA_CTL_BASE_ADDR		MX35_EMI_CTL_BASE_ADDR
+
+#define MX35_NFC_BASE_ADDR		0xbb000000
+#define MX35_PCMCIA_MEM_BASE_ADDR	0xbc000000
+
+/* FIXME: Get rid of these */
+#define IMX_WDT_BASE	MX35_WDOG_BASE_ADDR
+#define IMX_TIM1_BASE	MX35_GPT1_BASE_ADDR
+#define IMX_ESD_BASE	MX35_ESDCTL_BASE_ADDR
+#define IMX_IOMUXC_BASE	MX35_IOMUXC_BASE_ADDR
+#define IMX_CCM_BASE	MX35_CCM_BASE_ADDR
+#define IMX_NFC_BASE	MX35_NFC_BASE_ADDR
 
 /*
  * Clock Controller Module (CCM)
@@ -88,25 +180,6 @@
 #define PDR0_AUTO_CON		(1 << 0)
 #define PDR0_PER_SEL		(1 << 26)
 
-/*
- * Adresses and ranges of the external chip select lines
- */
-#define IMX_CS0_BASE	0xA0000000
-#define IMX_CS0_RANGE	(128 * 1024 * 1024)
-#define IMX_CS1_BASE	0xA8000000
-#define IMX_CS1_RANGE	(128 * 1024 * 1024)
-#define IMX_CS2_BASE	0xB0000000
-#define IMX_CS2_RANGE	(32 * 1024 * 1024)
-#define IMX_CS3_BASE	0xB2000000
-#define IMX_CS3_RANGE	(32 * 1024 * 1024)
-#define IMX_CS4_BASE	0xB4000000
-#define IMX_CS4_RANGE	(32 * 1024 * 1024)
-#define IMX_CS5_BASE	0xB6000000
-#define IMX_CS5_RANGE	(32 * 1024 * 1024)
-
-#define IMX_SDRAM_CS0  0x80000000
-#define IMX_SDRAM_CS1  0x90000000
-
 #define WEIM_BASE 0xb8002000
 #define CSCR_U(x)     (WEIM_BASE + (x) * 0x10)
 #define CSCR_L(x)     (WEIM_BASE + 4 + (x) * 0x10)
diff --git a/arch/arm/mach-imx/speed-imx35.c b/arch/arm/mach-imx/speed-imx35.c
index a4e0120da5..a8063f20b3 100644
--- a/arch/arm/mach-imx/speed-imx35.c
+++ b/arch/arm/mach-imx/speed-imx35.c
@@ -21,13 +21,13 @@
 
 unsigned long imx_get_mpllclk(void)
 {
-	ulong mpctl = readl(IMX_CCM_BASE + CCM_MPCTL);
+	ulong mpctl = readl(MX35_CCM_BASE_ADDR + CCM_MPCTL);
 	return imx_decode_pll(mpctl, CONFIG_MX35_HCLK_FREQ);
 }
 
 static unsigned long imx_get_ppllclk(void)
 {
-	ulong ppctl = readl(IMX_CCM_BASE + CCM_PPCTL);
+	ulong ppctl = readl(MX35_CCM_BASE_ADDR + CCM_PPCTL);
 	return imx_decode_pll(ppctl, CONFIG_MX35_HCLK_FREQ);
 }
 
@@ -56,7 +56,7 @@ static struct arm_ahb_div clk_consumer[] = {
 
 static unsigned long imx_get_armclk(void)
 {
-	unsigned long pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
+	unsigned long pdr0 = readl(MX35_CCM_BASE_ADDR + CCM_PDR0);
 	struct arm_ahb_div *aad;
 	unsigned long fref = imx_get_mpllclk();
 
@@ -70,7 +70,7 @@ static unsigned long imx_get_armclk(void)
 
 unsigned long imx_get_ahbclk(void)
 {
-	unsigned long pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
+	unsigned long pdr0 = readl(MX35_CCM_BASE_ADDR + CCM_PDR0);
 	struct arm_ahb_div *aad;
 	unsigned long fref = imx_get_mpllclk();
 
@@ -100,8 +100,8 @@ static unsigned long get_6_div(unsigned long in)
 
 static unsigned long imx_get_ipg_perclk(void)
 {
-	ulong pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
-	ulong pdr4 = readl(IMX_CCM_BASE + CCM_PDR4);
+	ulong pdr0 = readl(MX35_CCM_BASE_ADDR + CCM_PDR0);
+	ulong pdr4 = readl(MX35_CCM_BASE_ADDR + CCM_PDR4);
 	ulong div;
 	ulong fref;
 
@@ -129,7 +129,7 @@ unsigned long imx_get_gptclk(void)
  */
 unsigned long imx_get_lcdclk(void)
 {
-	unsigned long hsp_podf = (readl(IMX_CCM_BASE + CCM_PDR0) >> 20) & 0x03;
+	unsigned long hsp_podf = (readl(MX35_CCM_BASE_ADDR + CCM_PDR0) >> 20) & 0x03;
 	unsigned long base_clk = imx_get_armclk();
 
 	if (base_clk > 400 * 1000 * 1000) {
@@ -156,8 +156,8 @@ unsigned long imx_get_lcdclk(void)
 
 unsigned long imx_get_uartclk(void)
 {
-	unsigned long pdr3 = readl(IMX_CCM_BASE + CCM_PDR3);
-	unsigned long pdr4 = readl(IMX_CCM_BASE + CCM_PDR4);
+	unsigned long pdr3 = readl(MX35_CCM_BASE_ADDR + CCM_PDR3);
+	unsigned long pdr4 = readl(MX35_CCM_BASE_ADDR + CCM_PDR4);
 	unsigned long div = get_3_3_div(pdr4 >> 10);
 
 	if (pdr3 & (1 << 14))
@@ -169,7 +169,7 @@ unsigned long imx_get_uartclk(void)
 /* mmc0 clk only */
 unsigned long imx_get_mmcclk(void)
 {
-	unsigned long pdr3 = readl(IMX_CCM_BASE + CCM_PDR3);
+	unsigned long pdr3 = readl(MX35_CCM_BASE_ADDR + CCM_PDR3);
 	unsigned long div = get_6_div(pdr3);
 
 	if (pdr3 & (1 << 6))
@@ -213,7 +213,7 @@ void imx_dump_clocks(void)
  */
 int imx_clko_set_div(int num, int div)
 {
-	unsigned long cosr = readl(IMX_CCM_BASE + CCM_COSR);
+	unsigned long cosr = readl(MX35_CCM_BASE_ADDR + CCM_COSR);
 
 	if (num != 1)
 		return -ENODEV;
@@ -224,7 +224,7 @@ int imx_clko_set_div(int num, int div)
 	cosr &= ~(0x3f << 10);
 	cosr |= div << 10;
 
-	writel(cosr, IMX_CCM_BASE + CCM_COSR);
+	writel(cosr, MX35_CCM_BASE_ADDR + CCM_COSR);
 
 	return div + 1;
 }
@@ -234,14 +234,14 @@ int imx_clko_set_div(int num, int div)
  */
 void imx_clko_set_src(int num, int src)
 {
-	unsigned long cosr = readl(IMX_CCM_BASE + CCM_COSR);
+	unsigned long cosr = readl(MX35_CCM_BASE_ADDR + CCM_COSR);
 
 	if (num != 1)
 		return;
 
 	if (src < 0) {
 		cosr &= ~(1 << 5);
-		writel(cosr, IMX_CCM_BASE + CCM_COSR);
+		writel(cosr, MX35_CCM_BASE_ADDR + CCM_COSR);
 		return;
 	}
 
@@ -250,6 +250,6 @@ void imx_clko_set_src(int num, int src)
 	cosr &= ~(1 << 6);
 	cosr |= src & 0x1f;
 
-	writel(cosr, IMX_CCM_BASE + CCM_COSR);
+	writel(cosr, MX35_CCM_BASE_ADDR + CCM_COSR);
 }