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| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2022-03-03 15:42:45 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-03-04 15:28:40 +0100 |
| commit | 4b07580be56e540728af3658c57a1c8a4dbd1b7f (patch) | |
| tree | b61e6b41625c1a327f8d20d3ab9c7c2f647c0905 /arch/arm/mach-imx | |
| parent | ebac7952ef9a25b877edcdbed50b2715aed836b9 (diff) | |
| download | barebox-4b07580be56e540728af3658c57a1c8a4dbd1b7f.tar.gz barebox-4b07580be56e540728af3658c57a1c8a4dbd1b7f.tar.xz | |
ARM: i.MX: factor out AIPS configuration into helper function
We have the exact same sequence twice for each AIPS and i.MX6ULL/SX add
another AIPS, so it's time to factor this out into a dedicated helper
function and comment it a bit more.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20220303144246.3603311-1-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx')
| -rw-r--r-- | arch/arm/mach-imx/imx6.c | 44 |
1 files changed, 23 insertions, 21 deletions
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index 3ee42fd966..256288b25a 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -31,10 +31,29 @@ #define MX6_OCOTP_CFG0 0x410 #define MX6_OCOTP_CFG1 0x420 +static void imx6_configure_aips(void __iomem *aips) +{ + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, aips); + writel(0x77777777, aips + 0x4); + + /* + * Set all OPACRx to be non-bufferable, not require + * supervisor privilege level for access,allow for + * write access and untrusted master access. + */ + writel(0, aips + 0x40); + writel(0, aips + 0x44); + writel(0, aips + 0x48); + writel(0, aips + 0x4c); + writel(0, aips + 0x50); +} + static void imx6_init_lowlevel(void) { - void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR; - void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR; bool is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q; bool is_imx6d = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6D; uint32_t val_480; @@ -51,25 +70,8 @@ static void imx6_init_lowlevel(void) if ((readl(MXC_CCM_CCGR6) & 0x3)) imx_reset_otg_controller(IOMEM(MX6_OTG_BASE_ADDR)); - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - writel(0x77777777, aips1); - writel(0x77777777, aips1 + 0x4); - writel(0, aips1 + 0x40); - writel(0, aips1 + 0x44); - writel(0, aips1 + 0x48); - writel(0, aips1 + 0x4c); - writel(0, aips1 + 0x50); - - writel(0x77777777, aips2); - writel(0x77777777, aips2 + 0x4); - writel(0, aips2 + 0x40); - writel(0, aips2 + 0x44); - writel(0, aips2 + 0x48); - writel(0, aips2 + 0x4c); - writel(0, aips2 + 0x50); + imx6_configure_aips(IOMEM(MX6_AIPS1_ON_BASE_ADDR)); + imx6_configure_aips(IOMEM(MX6_AIPS2_ON_BASE_ADDR)); /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs * to make sure PFD is working right, otherwise, PFDs may |