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| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2021-10-01 12:09:44 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-10-05 09:05:37 +0200 |
| commit | a65b9f3e3844b7f2711cfd0ed48845f4de7c3bda (patch) | |
| tree | 67bd6755c0e2f3941ecb9839fedffccace8492b0 /arch/arm/mach-imx | |
| parent | 190616dc0bfefb4c20f57c951b444ceeeb2f73b1 (diff) | |
| download | barebox-a65b9f3e3844b7f2711cfd0ed48845f4de7c3bda.tar.gz barebox-a65b9f3e3844b7f2711cfd0ed48845f4de7c3bda.tar.xz | |
ARM: i.MX8MN: adapt early clock support
PBL runs fine when doing the same early clock setup as for the i.MX8MM:
i2c communication works, copying to DRAM works, but boot hangs in
barebox proper. Vendor patches for U-Boot configure SYS_PLL3 as 600MHz
for i.MX8MP and i.MX8MN. barebox i.MX8MP port evidently can do without,
but for i.MX8MN, reducing PLL frequency to 600MHz was required to boot.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20211001100949.6891-4-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx')
| -rw-r--r-- | arch/arm/mach-imx/imx8m.c | 16 | ||||
| -rw-r--r-- | arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h | 1 |
2 files changed, 14 insertions, 3 deletions
diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c index ac48e7aa0a..6b7cdac541 100644 --- a/arch/arm/mach-imx/imx8m.c +++ b/arch/arm/mach-imx/imx8m.c @@ -181,7 +181,7 @@ int imx8mq_init(void) #define IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL 0x104 #define IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL 0x114 -void imx8mm_early_clock_init(void) +static void __imx8mm_early_clock_init(unsigned long pll3_freq) /* and later */ { void __iomem *ana = IOMEM(MX8M_ANATOP_BASE_ADDR); void __iomem *ccm = IOMEM(MX8M_CCM_BASE_ADDR); @@ -224,9 +224,9 @@ void imx8mm_early_clock_init(void) IMX8M_CCM_TARGET_ROOTn_MUX(3)); imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC); - /* Configure SYS_PLL3 to 750MHz */ + /* Configure SYS_PLL3 */ clk_pll1416x_early_set_rate(ana + IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL, - 750000000UL, 25000000UL); + pll3_freq, 25000000UL); clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT), IMX8M_CCM_TARGET_ROOTn_MUX(7), @@ -249,6 +249,16 @@ void imx8mm_early_clock_init(void) FIELD_PREP(CCM_TARGET_ROOT0_DIV, 0)); } +void imx8mm_early_clock_init(void) +{ + __imx8mm_early_clock_init(750000000UL); +} + +void imx8mn_early_clock_init(void) +{ + __imx8mm_early_clock_init(600000000UL); +} + #define KEEP_ALIVE 0x18 #define VER_L 0x1c #define VER_H 0x20 diff --git a/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h index 743ed6cda0..985391f31a 100644 --- a/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h +++ b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h @@ -50,6 +50,7 @@ void imx8m_early_setup_uart_clock(void); void imx8mm_early_clock_init(void); +void imx8mn_early_clock_init(void); void imx8m_clock_set_target_val(int clock_id, u32 val); void imx8m_ccgr_clock_enable(int index); void imx8m_ccgr_clock_disable(int index); |