ARM: Layerscape: Add QSPI boot support

Booting Layerscape from QSPI is a bit tricky and the approach we take is
different from the one U-Boot has taken, so it's worth writing and
reading the following explanation.

The QSPI controller can map the Flash contents into the memory space (On
LS1046a at 0x40000000). The PBL unit uses this to read the RCW from this
memory window. The Layerscape SoCs have a PowerPC history, so it seemed
appropriate for the designers to let the QSPI controller operate in
big endian mode by default. To let the SoC see the correct RCW we have
to write the RCW and PBI data with be64 endianess. Our PBL image tool
pokes the initial binary into the SoC internal SRAM using PBI data as
done with SD/MMC boot aswell. barebox then changes the QSPI controller
endianess to le64 to properly read the barebox binary (placed at an
flash offset of 128KiB, so found in memory at 0x40020000) into SDRAM and
jumps to it.

U-Boot has another approach. Here the initial binary is executed in
place directly at 0x40100000. This means the QSPI controller endianess
must be swapped inside the PBI data. This has the effect that the whole
RCW/PBI data must be 64bit endianess swapped *except* the very last word
of the PBI data which contains the CRC command and is read already with
changed endianess. As a conclusion when porting QSPI PBI files from U-Boot
to barebox skip commands changing the endianess in the QSPI controller
and make sure the image is executed in internal SRAM and not in the
Flash memory window.

Lines like this should be removed:

09550000 000f400c

This sets the binary execution address:

09570604 40100000

For barebox it should be changed to 0x10000000.

As a result the PBI files can probably be unified between SD and QSPI
boot.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

3 files changed, 40 insertions, 0 deletions

diff --git a/arch/arm/mach-layerscape/Makefile b/arch/arm/mach-layerscape/Makefile
index ad4e2f7af3..4705154fb1 100644
--- a/arch/arm/mach-layerscape/Makefile
+++ b/arch/arm/mach-layerscape/Makefile
@@ -3,3 +3,4 @@ lwl-y += lowlevel.o errata.o
 lwl-$(CONFIG_ARCH_LS1046) += lowlevel-ls1046a.o
 obj-y += icid.o
 obj-pbl-y += boot.o
+pbl-y += xload-qspi.o
diff --git a/arch/arm/mach-layerscape/include/mach/xload.h b/arch/arm/mach-layerscape/include/mach/xload.h
index fedd36e020..94756ed13d 100644
--- a/arch/arm/mach-layerscape/include/mach/xload.h
+++ b/arch/arm/mach-layerscape/include/mach/xload.h
@@ -2,5 +2,7 @@
 #define __MACH_XLOAD_H
 
 int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long r2);
+int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1,
+					     unsigned long r2);
 
 #endif /* __MACH_XLOAD_H */
diff --git a/arch/arm/mach-layerscape/xload-qspi.c b/arch/arm/mach-layerscape/xload-qspi.c
new file mode 100644
index 0000000000..c76780a0e8
--- /dev/null
+++ b/arch/arm/mach-layerscape/xload-qspi.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <soc/fsl/immap_lsch2.h>
+#include <asm-generic/sections.h>
+#include <asm/cache.h>
+#include <mach/xload.h>
+#include <mach/layerscape.h>
+
+/*
+ * The offset of the 2nd stage image in the output file. This must match with the
+ * offset the pblimage tool puts barebox to.
+ */
+#define BAREBOX_START	(128 * 1024)
+
+int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1,
+					     unsigned long r2)
+{
+	void *qspi_reg_base = IOMEM(LSCH2_QSPI0_BASE_ADDR);
+	void *membase = (void *)LS1046A_DDR_SDRAM_BASE;
+	void *qspi_mem_base = IOMEM(0x40000000);
+	void (*barebox)(unsigned long, unsigned long, unsigned long) = membase;
+
+	/* Switch controller into little endian mode */
+	out_be32(qspi_reg_base, 0x000f400c);
+
+	memcpy(membase, qspi_mem_base + BAREBOX_START, barebox_image_size);
+	icache_invalidate();
+
+	printf("Starting barebox\n");
+
+	barebox(r0, r1, r2);
+
+	printf("failed\n");
+
+	return -EIO;
+}