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authorEzequiel Garcia <ezequiel.garcia@free-electrons.com>2014-11-10 15:19:43 -0300
committerSascha Hauer <s.hauer@pengutronix.de>2014-11-11 14:59:43 +0100
commit6638760c225c37f90e822ebf4dd8f0d2cd0b0ef3 (patch)
tree5d3f2bb2f10da35ea984f00e51fb2b79e9f05cea /arch/arm/mach-mvebu
parentabf9c94b538722487509701126bd1bc2314253b8 (diff)
downloadbarebox-6638760c225c37f90e822ebf4dd8f0d2cd0b0ef3.tar.gz
barebox-6638760c225c37f90e822ebf4dd8f0d2cd0b0ef3.tar.xz
ARM: mvebu: Enable PUP register
As reported by Sebastian, we need to enable this explicitly for the Tx clock on RGMII. While here, let's enable all the other peripherals. Although this is documented to be required only for Armada XP SoC, it has been found to be harmless on Armada 370, so we do it unconditionally to simplify the code. Reported-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mvebu')
-rw-r--r--arch/arm/mach-mvebu/armada-370-xp.c5
-rw-r--r--arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h7
2 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 57f6a5fe0d..244f8cdd81 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -74,6 +74,11 @@ static int armada_370_xp_init_soc(struct device_node *root, void *context)
mvebu_set_memory(phys_base, phys_size);
+ /* Enable peripherals PUP */
+ reg = readl(ARMADA_XP_PUP_ENABLE_BASE);
+ reg |= GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN | NAND_PUP_EN | SPI_PUP_EN;
+ writel(reg, ARMADA_XP_PUP_ENABLE_BASE);
+
return 0;
}
diff --git a/arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h b/arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h
index ccc687c03b..bac27e5a26 100644
--- a/arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h
+++ b/arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h
@@ -30,6 +30,13 @@
#define SAR_TCLK_FREQ BIT(20)
#define SAR_HIGH 0x04
+#define ARMADA_XP_PUP_ENABLE_BASE (ARMADA_370_XP_INT_REGS_BASE + 0x1864c)
+#define GE0_PUP_EN BIT(0)
+#define GE1_PUP_EN BIT(1)
+#define LCD_PUP_EN BIT(2)
+#define NAND_PUP_EN BIT(4)
+#define SPI_PUP_EN BIT(5)
+
#define ARMADA_370_XP_SDRAM_BASE (ARMADA_370_XP_INT_REGS_BASE + 0x20000)
#define DDR_BASE_CS 0x180
#define DDR_BASE_CSn(n) (DDR_BASE_CS + ((n) * 0x8))