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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2017-06-13 00:37:49 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2017-06-13 09:22:48 +0200
commit7351b6b5c59c7a280787998006f39a5cd3a2f18b (patch)
tree6e2d5e91a27061abe4139fc9694bc2965a80912d /arch/arm/mach-mvebu
parent52daa4a94e7515aef7e29d92ebd483357129fbf2 (diff)
downloadbarebox-7351b6b5c59c7a280787998006f39a5cd3a2f18b.tar.gz
barebox-7351b6b5c59c7a280787998006f39a5cd3a2f18b.tar.xz
ARM: mvebu: fix size mask for RAM window
The size field in the window control register occupies bits 31:16. So adapt ARMADA_370_XP_DDR_SIZE_MASK accordingly. This fixes detection of RAM chips smaller than 32 MiB and so probably doesn't affect any supported machine. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mvebu')
-rw-r--r--arch/arm/mach-mvebu/common.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c
index 06bfb72615..fa971da11e 100644
--- a/arch/arm/mach-mvebu/common.c
+++ b/arch/arm/mach-mvebu/common.c
@@ -47,7 +47,7 @@
#define ARMADA_370_XP_SDRAM_BASE (IOMEM(MVEBU_REMAP_INT_REG_BASE) + 0x20000)
#define ARMADA_370_XP_DDR_SIZE_CSn(n) (0x184 + ((n) * 0x8))
#define ARMADA_370_XP_DDR_SIZE_ENABLED BIT(0)
-#define ARMADA_370_XP_DDR_SIZE_MASK 0xff000000
+#define ARMADA_370_XP_DDR_SIZE_MASK 0xffff0000
/*
* Marvell MVEBU SoC id and revision can be read from any PCIe