diff options
| author | Wolfram Sang <w.sang@pengutronix.de> | 2011-12-18 23:26:39 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-06-30 12:53:36 +0200 |
| commit | eb76c8e827b94bc445635baf8d1bdcd41ca8f48d (patch) | |
| tree | e5ff82682647236ded8938671915c84ffbf7cbf9 /arch/arm/mach-mxs/speed-imx23.c | |
| parent | 4a39f83320b90517c9b6db7d696420393890b94d (diff) | |
| download | barebox-eb76c8e827b94bc445635baf8d1bdcd41ca8f48d.tar.gz barebox-eb76c8e827b94bc445635baf8d1bdcd41ca8f48d.tar.xz | |
mtd nand: add mxs-nand driver
Based on the U-Boot version. Changed to kernel style register layout, added
MX23 support (WIP!), made MMU aware and adapted to barebox.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mxs/speed-imx23.c')
| -rw-r--r-- | arch/arm/mach-mxs/speed-imx23.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/mach-mxs/speed-imx23.c b/arch/arm/mach-mxs/speed-imx23.c index b10c78643c..3a2a1b62c0 100644 --- a/arch/arm/mach-mxs/speed-imx23.c +++ b/arch/arm/mach-mxs/speed-imx23.c @@ -47,6 +47,8 @@ # define GET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK) # define SET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK) #define HW_CLKCTRL_GPMI 0x080 +# define CLKCTRL_GPMI_CLKGATE (1 << 31) +# define CLKCTRL_GPMI_DIV_MASK 0x3ff /* note: no set/clear register! */ #define HW_CLKCTRL_SPDIF 0x090 /* note: no set/clear register! */ @@ -266,6 +268,23 @@ unsigned imx_set_sspclk(unsigned index, unsigned nc, int high) return imx_get_sspclk(index); } +void imx_enable_nandclk(void) +{ + uint32_t reg; + + /* Clear bypass bit; refman says clear, but fsl-code does set. Hooray! */ + writel(CLKCTRL_CLKSEQ_BYPASS_GPMI, + IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + BIT_SET); + + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_GPMI) & ~CLKCTRL_GPMI_CLKGATE; + writel(reg, IMX_CCM_BASE + HW_CLKCTRL_GPMI); + udelay(1000); + /* Initialize DIV to 1 */ + reg &= ~CLKCTRL_GPMI_DIV_MASK; + reg |= 1; + writel(reg, IMX_CCM_BASE + HW_CLKCTRL_GPMI); +} + void imx_dump_clocks(void) { printf("mpll: %10u kHz\n", imx_get_mpllclk() / 1000); |