diff options
| author | Roland Hieber <r.hieber@pengutronix.de> | 2018-08-13 15:02:49 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-08-14 08:54:40 +0200 |
| commit | b9d14c715e75a12ac6689742982170d2f218081a (patch) | |
| tree | 40eca75fb5f52c844f8ea233a581344d7985c220 /arch/arm/mach-mxs | |
| parent | 3c8ec2338b7a8e4e6e23a9f7067f3ed6dcdeba12 (diff) | |
| download | barebox-b9d14c715e75a12ac6689742982170d2f218081a.tar.gz barebox-b9d14c715e75a12ac6689742982170d2f218081a.tar.xz | |
ARM: MXS: i.MX28: allow setup of low-voltage SDRAM
The PINCTRL_*_DDR_MODE_* defines are now needed in global scope, so move
them to the respective include header.
Signed-off-by: Roland Hieber <r.hieber@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mxs')
| -rw-r--r-- | arch/arm/mach-mxs/include/mach/init.h | 7 | ||||
| -rw-r--r-- | arch/arm/mach-mxs/mem-init.c | 9 |
2 files changed, 9 insertions, 7 deletions
diff --git a/arch/arm/mach-mxs/include/mach/init.h b/arch/arm/mach-mxs/include/mach/init.h index 6526d303a1..7021981d41 100644 --- a/arch/arm/mach-mxs/include/mach/init.h +++ b/arch/arm/mach-mxs/include/mach/init.h @@ -21,8 +21,13 @@ void mxs_power_wait_pswitch(void); extern const uint32_t mx28_dram_vals_default[190]; extern uint32_t mx23_dram_vals[]; +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_LPDDR1 (0b00 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_LVDDR2 (0b10 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2 (0b11 << 16) + void mx23_mem_init(void); -void mx28_mem_init(const uint32_t dram_vals[190]); +void mx28_mem_init(const int emi_ds_ctrl_ddr_mode, + const uint32_t dram_vals[190]); void mxs_mem_setup_cpu_and_hbus(void); void mxs_mem_setup_vdda(void); void mxs_mem_init_clock(unsigned char divider); diff --git a/arch/arm/mach-mxs/mem-init.c b/arch/arm/mach-mxs/mem-init.c index ac8bfee18e..7bc6be00b4 100644 --- a/arch/arm/mach-mxs/mem-init.c +++ b/arch/arm/mach-mxs/mem-init.c @@ -318,18 +318,15 @@ void mx23_mem_init(void) mxs_mem_setup_cpu_and_hbus(); } -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2 (0x3 << 16) - -void mx28_mem_init(const uint32_t dram_vals[190]) +void mx28_mem_init(const int emi_ds_ctrl_ddr_mode, const uint32_t dram_vals[190]) { mxs_early_delay(11000); /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */ mxs_mem_init_clock(21); - /* Set DDR2 mode */ - writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, - IMX_IOMUXC_BASE + 0x1b80); + /* Set DDR mode */ + writel(emi_ds_ctrl_ddr_mode, IMX_IOMUXC_BASE + 0x1b80); /* * Configure the DRAM registers |