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| author | Vicente Bergas <vicencb@gmail.com> | 2013-04-09 23:48:19 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-04-11 10:47:43 +0200 |
| commit | bb18fee0d8d3f9ddb377ece250486a1a473f6763 (patch) | |
| tree | 498f23e63fcdebe45ed9e018e4ee736665ccaffc /arch/arm/mach-omap/include/mach/omap4-silicon.h | |
| parent | be78f86efc1f03c6b77e1685c93afbd615ee8ece (diff) | |
| download | barebox-bb18fee0d8d3f9ddb377ece250486a1a473f6763.tar.gz barebox-bb18fee0d8d3f9ddb377ece250486a1a473f6763.tar.xz | |
OMAP4: add command to select next boot device priority
On OMAP4 SoC there is a SAR memory region (Save & Rescue)
where the ROM code reads the device to boot from.
This patch adds a way to set this.
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-omap/include/mach/omap4-silicon.h')
| -rw-r--r-- | arch/arm/mach-omap/include/mach/omap4-silicon.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h index 9e82435e9c..666e721551 100644 --- a/arch/arm/mach-omap/include/mach/omap4-silicon.h +++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h @@ -161,6 +161,25 @@ #define OMAP44XX_PRM_RSTCTRL_RESET 0x01 /* + * SAR (Save & Rescue) memory region + */ +#define OMAP44XX_SAR_RAM_BASE 0x4a326000 +#define OMAP44XX_SAR_CH_ADDRESS (OMAP44XX_SAR_RAM_BASE + 0xA00) +#define OMAP44XX_SAR_CH_START (OMAP44XX_SAR_RAM_BASE + 0xA0C) +#define OMAP44XX_SAR_BOOT_VOID 0x00 +#define OMAP44XX_SAR_BOOT_XIP 0x01 +#define OMAP44XX_SAR_BOOT_XIPWAIT 0x02 +#define OMAP44XX_SAR_BOOT_NAND 0x03 +#define OMAP44XX_SAR_BOOT_ONENAND 0x04 +#define OMAP44XX_SAR_BOOT_MMC1 0x05 +#define OMAP44XX_SAR_BOOT_MMC2_1 0x06 +#define OMAP44XX_SAR_BOOT_MMC2_2 0x07 +#define OMAP44XX_SAR_BOOT_UART 0x43 +#define OMAP44XX_SAR_BOOT_USB_1 0x45 +#define OMAP44XX_SAR_BOOT_USB_ULPI 0x46 +#define OMAP44XX_SAR_BOOT_USB_2 0x47 + +/* * Non-secure SRAM Addresses * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE * at 0x40304000(EMU base) so that our code works for both EMU and GP @@ -212,6 +231,7 @@ void omap4_ddr_init(const struct ddr_regs *, const struct dpll_param *); void omap4_power_i2c_send(u32); unsigned int omap4_revision(void); noinline int omap4_scale_vcores(unsigned vsel0_pin); +void omap4_set_warmboot_order(u32 *device_list); #endif |