diff options
| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-10-22 14:21:25 +0200 |
|---|---|---|
| committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-10-22 14:21:25 +0200 |
| commit | f6a579da9c6c3e2d776f9251bcc727f6e17c0a11 (patch) | |
| tree | ee85d7902996c70bffe668b5d7172dee24c46574 /arch/arm/mach-omap | |
| parent | 9956bdf77d7dbc61fe0f923917d2cdce3e2b40e5 (diff) | |
| download | barebox-f6a579da9c6c3e2d776f9251bcc727f6e17c0a11.tar.gz barebox-f6a579da9c6c3e2d776f9251bcc727f6e17c0a11.tar.xz | |
[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'arch/arm/mach-omap')
22 files changed, 1644 insertions, 30 deletions
diff --git a/arch/arm/mach-omap/gpmc.c b/arch/arm/mach-omap/gpmc.c index 4e7383ccc0..2b9964950d 100644 --- a/arch/arm/mach-omap/gpmc.c +++ b/arch/arm/mach-omap/gpmc.c @@ -30,10 +30,10 @@ #include <common.h> #include <init.h> #include <asm/io.h> -#include <asm/arch/silicon.h> -#include <asm/arch/gpmc.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/syslib.h> +#include <mach/silicon.h> +#include <mach/gpmc.h> +#include <mach/sys_info.h> +#include <mach/syslib.h> /** * @brief Do a Generic initialization of GPMC. if you choose otherwise, diff --git a/arch/arm/mach-omap/include/mach/clocks.h b/arch/arm/mach-omap/include/mach/clocks.h new file mode 100644 index 0000000000..1221238de8 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/clocks.h @@ -0,0 +1,48 @@ +/** + * @file + * @brief Generic Clock wrapper header. + * + * FileName: include/asm-arm/arch-omap/clocks.h + * + * This includes each of the architecture Clock definitions under it. + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __OMAP_CLOCKS_H_ +#define __OMAP_CLOCKS_H_ + +#define LDELAY 12000000 + +/* Standard defines for Various clocks */ +#define S12M 12000000 +#define S13M 13000000 +#define S19_2M 19200000 +#define S24M 24000000 +#define S26M 26000000 +#define S38_4M 38400000 + +#ifdef CONFIG_ARCH_OMAP3 +#include <mach/omap3-clock.h> +#endif + +#endif /* __OMAP_CLOCKS_H_ */ diff --git a/arch/arm/mach-omap/include/mach/control.h b/arch/arm/mach-omap/include/mach/control.h new file mode 100644 index 0000000000..7c1614cc24 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/control.h @@ -0,0 +1,98 @@ +/** + * @file + * @brief This file contains the Control register defines + * + * FileName: include/asm-arm/arch-omap/control.h + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz + * include/asm-arm/arch-omap/omap34xx.h + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * Copyright (C) 2007 Texas Instruments, <www.ti.com> + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP_CONTROL_H +#define __ASM_ARCH_OMAP_CONTROL_H + +/** + * Control register defintion which unwraps to the real register + * offset + base address + */ +#define CONTROL_REG(REGNAME) (OMAP_CTRL_BASE + CONTROL_##REGNAME) + +#define CONTROL_SCALABLE_OMAP_STATUS (0x44C) +#define CONTROL_SCALABLE_OMAP_OCP (0x534) +#define CONTROL_SCRATCHPAD_BASE (0x910) +#define CONTROL_SCRATCHPAD_ROM_BASE (0x860) +#define CONTROL_STATUS (0x2f0) +#define CONTROL_SYSCONFIG (0x010) +#define CONTROL_DEVCONF0 (0x274) +#define CONTROL_DEVCONF1 (0x2D8) +#define CONTROL_IVA2_BOOTMOD (0x404) +#define CONTROL_IVA2_BOOTADDR (0x400) +#define CONTROL_PBIAS_1 (0x520) +#define CONTROL_GENERAL_PURPOSE_STATUS (0x2F4) +#define CONTROL_MEM_DFTRW0 (0x278) +#define CONTROL_MEM_DFTRW1 (0x27C) +#define CONTROL_MSUSPENDMUX_0 (0x290) +#define CONTROL_MSUSPENDMUX_1 (0x294) +#define CONTROL_MSUSPENDMUX_2 (0x298) +#define CONTROL_MSUSPENDMUX_3 (0x29C) +#define CONTROL_MSUSPENDMUX_4 (0x2A0) +#define CONTROL_MSUSPENDMUX_5 (0x2A4) +#define CONTROL_SEC_CTRL (0x2B0) +#define CONTROL_CSIRXFE (0x2DC) +#define CONTROL_DEBOBS_0 (0x420) +#define CONTROL_DEBOBS_1 (0x424) +#define CONTROL_DEBOBS_2 (0x428) +#define CONTROL_DEBOBS_3 (0x42C) +#define CONTROL_DEBOBS_4 (0x430) +#define CONTROL_DEBOBS_5 (0x434) +#define CONTROL_DEBOBS_6 (0x438) +#define CONTROL_DEBOBS_7 (0x43C) +#define CONTROL_DEBOBS_8 (0x440) +#define CONTROL_PROG_IO0 (0x444) +#define CONTROL_PROG_IO1 (0x448) +#define CONTROL_DSS_DPLL_SPREADING (0x450) +#define CONTROL_CORE_DPLL_SPREADING (0x454) +#define CONTROL_PER_DPLL_SPREADING (0x458) +#define CONTROL_USBHOST_DPLL_SPREADING (0x45C) +#define CONTROL_TEMP_SENSOR (0x524) +#define CONTROL_SRAMLDO4 (0x528) +#define CONTROL_SRAMLDO5 (0x52C) +#define CONTROL_CSI (0x530) +#define CONTROL_SCALABLE_OMAP_OCP (0x534) +#define CONTROL_SCALABLE_OMAP_STATUS (0x44C) + +/** Provide the Regoffset, Value */ +#define MUX_VAL(OFFSET,VALUE)\ + writew((VALUE), OMAP_CTRL_BASE + (OFFSET)) + +/** + * macro for Padconfig Registers @see + * include/mach-arm/arch-omap/omap3-mux.h + */ +#define CP(X) (CONTROL_PADCONF_##X) + +#endif /* __ASM_ARCH_OMAP_CONTROL_H */ diff --git a/arch/arm/mach-omap/include/mach/gpmc.h b/arch/arm/mach-omap/include/mach/gpmc.h new file mode 100644 index 0000000000..a658cf00e7 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/gpmc.h @@ -0,0 +1,161 @@ +/** + * @file + * @brief This file contains the GPMC's generic definitions + * + * FileName: include/asm-arm/arch-omap/gpmc.h + * + * OMAP's General Purpose Memory Controller(GPMC) provides features + * allowing us to communicate with memory devices such as NOR, NAND, + * OneNAND, SRAM etc.. This file defines certain generic parameters + * allowing us to configure the same painlessly. + * + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz + * include/asm-arm/arch-omap/omap34xx.h + * + * Copyright (C) 2007 Texas Instruments, <www.ti.com> + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP_GPMC_H +#define __ASM_ARCH_OMAP_GPMC_H + +/** GPMC Reg Wrapper */ +#define GPMC_REG(REGNAME) (OMAP_GPMC_BASE + GPMC_##REGNAME) + +#define GPMC_SYS_CONFIG (0x10) +#define GPMC_SYS_STATUS (0x14) +#define GPMC_IRQSTATUS (0x18) +#define GPMC_IRQ_ENABLE (0x1C) +#define GPMC_TIMEOUT_CONTROL (0x40) +#define GPMC_CFG (0x50) +#define GPMC_STATUS (0x54) +#define GPMC_PREFETCH_CONFIG_1 (0x1E0) +#define GPMC_PREFETCH_CONFIG_2 (0x1E4) +#define GPMC_PREFETCH_CTRL (0x1EC) +#define GPMC_ECC_CONFIG (0x1F4) +#define GPMC_ECC_CONTROL (0x1F8) +#define GPMC_ECC_SIZE_CONFIG (0x1FC) +#define GPMC_ECC1_RESULT (0x200) +#define GPMC_ECC2_RESULT (0x204) +#define GPMC_ECC3_RESULT (0x208) +#define GPMC_ECC4_RESULT (0x20C) +#define GPMC_ECC5_RESULT (0x210) +#define GPMC_ECC6_RESULT (0x214) +#define GPMC_ECC7_RESULT (0x218) +#define GPMC_ECC8_RESULT (0x21C) +#define GPMC_ECC9_RESULT (0x220) + +#define GPMC_CONFIG1_0 (0x60) +#define GPMC_CONFIG1_1 (0x90) +#define GPMC_CONFIG1_2 (0xC0) +#define GPMC_CONFIG1_3 (0xF0) +#define GPMC_CONFIG1_4 (0x120) +#define GPMC_CONFIG1_5 (0x150) +#define GPMC_CONFIG1_6 (0x180) +#define GPMC_CONFIG1_7 (0x1B0) +#define GPMC_CONFIG2_0 (0x64) +#define GPMC_CONFIG2_1 (0x94) +#define GPMC_CONFIG2_2 (0xC4) +#define GPMC_CONFIG2_3 (0xF4) +#define GPMC_CONFIG2_4 (0x124) +#define GPMC_CONFIG2_5 (0x154) +#define GPMC_CONFIG2_6 (0x184) +#define GPMC_CONFIG2_7 (0x1B4) +#define GPMC_CONFIG3_0 (0x68) +#define GPMC_CONFIG3_1 (0x98) +#define GPMC_CONFIG3_2 (0xC8) +#define GPMC_CONFIG3_3 (0xF8) +#define GPMC_CONFIG3_4 (0x128) +#define GPMC_CONFIG3_5 (0x158) +#define GPMC_CONFIG3_6 (0x188) +#define GPMC_CONFIG3_7 (0x1B8) +#define GPMC_CONFIG4_0 (0x6C) +#define GPMC_CONFIG4_1 (0x9C) +#define GPMC_CONFIG4_2 (0xCC) +#define GPMC_CONFIG4_3 (0xFC) +#define GPMC_CONFIG4_4 (0x12C) +#define GPMC_CONFIG4_5 (0x15C) +#define GPMC_CONFIG4_6 (0x18C) +#define GPMC_CONFIG4_7 (0x1BC) +#define GPMC_CONFIG5_0 (0x70) +#define GPMC_CONFIG5_1 (0xA0) +#define GPMC_CONFIG5_2 (0xD0) +#define GPMC_CONFIG5_3 (0x100) +#define GPMC_CONFIG5_4 (0x130) +#define GPMC_CONFIG5_5 (0x160) +#define GPMC_CONFIG5_6 (0x190) +#define GPMC_CONFIG5_7 (0x1C0) +#define GPMC_CONFIG6_0 (0x74) +#define GPMC_CONFIG6_1 (0xA4) +#define GPMC_CONFIG6_2 (0xD4) +#define GPMC_CONFIG6_3 (0x104) +#define GPMC_CONFIG6_4 (0x134) +#define GPMC_CONFIG6_5 (0x164) +#define GPMC_CONFIG6_6 (0x194) +#define GPMC_CONFIG6_7 (0x1C4) +#define GPMC_CONFIG7_0 (0x78) +#define GPMC_CONFIG7_1 (0xA8) +#define GPMC_CONFIG7_2 (0xD8) +#define GPMC_CONFIG7_3 (0x108) +#define GPMC_CONFIG7_4 (0x138) +#define GPMC_CONFIG7_5 (0x168) +#define GPMC_CONFIG7_6 (0x198) +#define GPMC_CONFIG7_7 (0x1C8) + +#define GPMC_NUM_CS 8 +#define GPMC_CONFIG_CS_SIZE (GPMC_CONFIG1_1 - GPMC_CONFIG1_0) +#define GPMC_CONFIG_REG_OFF (GPMC_CONFIG2_0 - GPMC_CONFIG1_0) + +#define GPMC_CS_NAND_COMMAND (0x1C) +#define GPMC_CS_NAND_ADDRESS (0x20) +#define GPMC_CS_NAND_DATA (0x24) + +#define GPMC_SIZE_128M 0x08 +#define GPMC_SIZE_64M 0x0C +#define GPMC_SIZE_32M 0x0E +#define GPMC_SIZE_16M 0x0F + +#define NAND_WP_BIT 0x00000010 + +#ifndef __ASSEMBLY__ + +/** Generic GPMC configuration structure to be used to configure a + * chip select + */ +struct gpmc_config { + unsigned int cfg[6]; + unsigned int base; + unsigned char size; +}; + +/** Generic configuration - will reset all the cs configs. */ +void gpmc_generic_init(unsigned int cfg); + +/** Configuration for a specific chip select */ +void gpmc_cs_config(char cs, struct gpmc_config *config); + +#endif + +#endif /* __ASM_ARCH_OMAP_GPMC_H */ diff --git a/arch/arm/mach-omap/include/mach/gpmc_nand.h b/arch/arm/mach-omap/include/mach/gpmc_nand.h new file mode 100644 index 0000000000..c6c51d5d52 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/gpmc_nand.h @@ -0,0 +1,121 @@ +/** + * @file + * @brief This file contains exported structure for NAND + * + * FileName: include/asm-arm/arch-omap/gpmc_nand.h + * + * OMAP's General Purpose Memory Controller (GPMC) has a NAND controller + * embedded. this file provides the platform data structure required to + * hook on to it. + * + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.3.tar.gz + * include/asm-arm/arch-omap/nand.h + * + * Copyright (C) 2006 Micron Technology Inc. + * Author: Shahrom Sharif-Kashani + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_OMAP_NAND_GPMC_H +#define __ASM_OMAP_NAND_GPMC_H + +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/nand_ecc.h> + +/** omap nand platform data structure */ +struct gpmc_nand_platform_data { + /** Chip select you want to use */ + int cs; + struct mtd_partition *parts; + int nr_parts; + /** If there are any special setups you'd want to do */ + int (*nand_setup) (struct gpmc_nand_platform_data *); + + /** set up if we want H/w ECC here and other + * platform specific configs here + */ + unsigned short plat_options; + /** setup any special options */ + unsigned int options; + /** set up device access as 8,16 as per GPMC config */ + char device_width; + /** Set this to WAITx+1, so GPMC WAIT0 will be 1 and so on. */ + char wait_mon_pin; + /** Set this to the max timeout for the device */ + uint64_t max_timeout; + + /* if you like a custom oob use this. */ + struct nand_ecclayout *oob; + /** platform specific private data */ + void *priv; +}; + +/** Platform specific options definitions */ +/** plat_options: Wait montioring pin low */ +#define NAND_WAITPOL_LOW (0 << 0) +/** plat_options: Wait montioring pin high */ +#define NAND_WAITPOL_HIGH (1 << 0) +#define NAND_WAITPOL_MASK (1 << 0) + +#ifdef CONFIG_NAND_OMAP_GPMC_HWECC +/** plat_options: hw ecc enabled */ +#define NAND_HWECC_ENABLE (1 << 1) +#endif +/** plat_options: hw ecc disabled */ +#define NAND_HWECC_DISABLE (0 << 1) +#define NAND_HWECC_MASK (1 << 1) + +/* Typical BOOTROM oob layouts-requires hwecc **/ +#ifdef CONFIG_NAND_OMAP_GPMC_HWECC +/** Large Page x8 NAND device Layout */ +#define GPMC_NAND_ECC_LP_x8_LAYOUT {\ + .eccbytes = 12,\ + .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\ + 9, 10, 11, 12},\ + .oobfree = {\ + {.offset = 60,\ + .length = 2 } } \ +} + +/** Large Page x16 NAND device Layout */ +#define GPMC_NAND_ECC_LP_x16_LAYOUT {\ + .eccbytes = 12,\ + .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13},\ + .oobfree = {\ + {.offset = 60,\ + .length = 2 } } \ +} + +/** Small Page x8 NAND device Layout */ +#define GPMC_NAND_ECC_SP_x8_LAYOUT {\ + .eccbytes = 3,\ + .eccpos = {1, 2, 3},\ + .oobfree = {\ + {.offset = 14,\ + .length = 2 } } \ +} + +/** Small Page x16 NAND device Layout */ +#define GPMC_NAND_ECC_SP_x16_LAYOUT {\ + .eccbytes = 3,\ + .eccpos = {2, 3, 4},\ + .oobfree = {\ + {.offset = 14,\ + .length = 2 } } \ +} + +#endif /* CONFIG_NAND_OMAP_GPMC_HWECC */ + +#endif /* __ASM_OMAP_NAND_GPMC_H */ diff --git a/arch/arm/mach-omap/include/mach/intc.h b/arch/arm/mach-omap/include/mach/intc.h new file mode 100644 index 0000000000..48fcf3d1d6 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/intc.h @@ -0,0 +1,58 @@ +/** + * @file + * @brief This file contains the Interrupt controller register defines + * + * FileName: include/asm-arm/arch-omap/intc.h + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz + * include/asm-arm/arch-omap/omap34xx.h + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * Copyright (C) 2007 Texas Instruments, <www.ti.com> + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP_INTC_H +#define __ASM_ARCH_OMAP_INTC_H + +/** Interrupt Controller Register wrapper */ +#define INTC_REG(REGNAME) (OMAP_INTC_BASE + INTC_##REGNAME) + +#define INTC_MIR_0 (0x084) +#define INTC_MIR_1 (0x0A4) +#define INTC_MIR_2 (0x0C4) +#define INTC_MIR_SET_0 (0x08C) +#define INTC_MIR_SET_1 (0x0AC) +#define INTC_MIR_SET_2 (0x0CC) +#define INTC_MIR_CLEAR_0 (0x094) +#define INTC_MIR_CLEAR_1 (0x0B4) +#define INTC_MIR_CLEAR_2 (0x0D4) +#define INTC_PS_SYSCONFIG (0x010) +#define INTC_PS_PROTECTION (0x04C) +#define INTC_PS_IDLE (0x050) +#define INTC_PS_THRESHOLD (0x068) +#define INTC_PS_PENDING_IRQ0 (0x098) +#define INTC_PS_PENDING_IRQ1 (0x0B8) +#define INTC_PS_PENDING_IRQ2 (0x0D8) + +#endif /* __ASM_ARCH_OMAP_INTC_H */ diff --git a/arch/arm/mach-omap/include/mach/omap3-clock.h b/arch/arm/mach-omap/include/mach/omap3-clock.h new file mode 100644 index 0000000000..22694f2367 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/omap3-clock.h @@ -0,0 +1,124 @@ +/** + * @file + * @brief Contains the PRM and CM definitions + * + * FileName: include/asm-arm/arch-omap/omap3-clock.h + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + * + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP343X_CLOCKS_H_ +#define _OMAP343X_CLOCKS_H_ + +/** CM Clock Regs Wrapper */ +#define CM_REG(REGNAME) (OMAP_CM_BASE + CM_##REGNAME) + +#define CM_FCLKEN_IVA2 0X0000 +#define CM_CLKEN_PLL_IVA2 0X0004 +#define CM_IDLEST_PLL_IVA2 0X0024 +#define CM_CLKSEL1_PLL_IVA2 0X0040 +#define CM_CLKSEL2_PLL_IVA2 0X0044 +#define CM_CLKEN_PLL_MPU 0X0904 +#define CM_IDLEST_PLL_MPU 0X0924 +#define CM_CLKSEL1_PLL_MPU 0X0940 +#define CM_CLKSEL2_PLL_MPU 0X0944 +#define CM_FCLKEN1_CORE 0X0A00 +#define CM_ICLKEN1_CORE 0X0A10 +#define CM_ICLKEN2_CORE 0X0A14 +#define CM_CLKSEL_CORE 0X0A40 +#define CM_FCLKEN_GFX 0X0B00 +#define CM_ICLKEN_GFX 0X0B10 +#define CM_CLKSEL_GFX 0X0B40 +#define CM_FCLKEN_WKUP 0X0C00 +#define CM_ICLKEN_WKUP 0X0C10 +#define CM_CLKSEL_WKUP 0X0C40 +#define CM_IDLEST_WKUP 0X0C20 +#define CM_CLKEN_PLL 0X0D00 +#define CM_IDLEST_CKGEN 0X0D20 +#define CM_CLKSEL1_PLL 0X0D40 +#define CM_CLKSEL2_PLL 0X0D44 +#define CM_CLKSEL3_PLL 0X0D48 +#define CM_FCLKEN_DSS 0X0E00 +#define CM_ICLKEN_DSS 0X0E10 +#define CM_CLKSEL_DSS 0X0E40 +#define CM_FCLKEN_CAM 0X0F00 +#define CM_ICLKEN_CAM 0X0F10 +#define CM_CLKSEL_CAM 0X0f40 +#define CM_FCLKEN_PER 0X1000 +#define CM_ICLKEN_PER 0X1010 +#define CM_CLKSEL_PER 0X1040 +#define CM_CLKSEL1_EMU 0X1140 + +/** PRM Clock Regs */ +#define PRM_REG(REGNAME) (OMAP_PRM_BASE + PRM_##REGNAME) +#define PRM_CLKSEL 0x0D40 +#define PRM_RSTCTRL 0x1250 +#define PRM_CLKSRC_CTRL 0x1270 + +/*************** Clock Values */ +#define PLL_STOP 1 /* PER & IVA */ +#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ +#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ +#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ + +/* The following configurations are OPP and SysClk value independant + * and hence are defined here. + */ + +/* CORE DPLL */ +#define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ +#define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ +#define CORE_FUSB_DIV 2 /* 41.5MHz: */ +#define CORE_L4_DIV 2 /* 83MHz : L4 */ +#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ +#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ +#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ + +/* PER DPLL */ +#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ +#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ +#define PER_M4X2 9 /* 96MHz : CM_CLKSEL_DSS-dss1 */ +#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ + +#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50)) + +#define MAX_SIL_INDEX 1 + +#ifndef __ASSEMBLY__ +void prcm_init(void); +/* Used to index into DPLL parameter tables -See TRM for further details */ +struct dpll_param { + unsigned int m; + unsigned int n; + unsigned int fsel; + unsigned int m2; +}; +/* External functions see omap3_clock_core.S */ +extern struct dpll_param *get_mpu_dpll_param(void); +extern struct dpll_param *get_iva_dpll_param(void); +extern struct dpll_param *get_core_dpll_param(void); +extern struct dpll_param *get_per_dpll_param(void); + +#endif /* __ASSEMBLY__ */ + +#endif /* endif _OMAP343X_CLOCKS_H_ */ diff --git a/arch/arm/mach-omap/include/mach/omap3-mux.h b/arch/arm/mach-omap/include/mach/omap3-mux.h new file mode 100644 index 0000000000..2badc3f851 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/omap3-mux.h @@ -0,0 +1,423 @@ +/** + * @file + * @brief Mux Configuration Register defines for OMAP3 + * + * FileName: include/asm-arm/arch-omap/omap3-mux.h + * + * This file defines the various Pin Mux registers + * @see include/asm-arm/arch-omap/control.h + * The @ref MUX_VAL macro uses the defines from this file + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Syed Mohammed Khasim <x0khasim@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _ASM_ARCH_OMAP3_MUX_H_ +#define _ASM_ARCH_OMAP3_MUX_H_ + +/** + * Pin Mux Enable Defines + * + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0-7 - Mode 0-7 + * + * @see MUX_VAL + */ +#define IEN (1 << 8) + +#define IDIS (0 << 8) +#define PTU (1 << 4) +#define PTD (0 << 4) +#define EN (1 << 3) +#define DIS (0 << 3) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 + +/* + * To get the actual address the offset has to added + * with OMAP_CTRL_BASE to get the actual address + */ + +/* SDRC */ +#define CONTROL_PADCONF_SDRC_D0 0x0030 +#define CONTROL_PADCONF_SDRC_D1 0x0032 +#define CONTROL_PADCONF_SDRC_D2 0x0034 +#define CONTROL_PADCONF_SDRC_D3 0x0036 +#define CONTROL_PADCONF_SDRC_D4 0x0038 +#define CONTROL_PADCONF_SDRC_D5 0x003A +#define CONTROL_PADCONF_SDRC_D6 0x003C +#define CONTROL_PADCONF_SDRC_D7 0x003E +#define CONTROL_PADCONF_SDRC_D8 0x0040 +#define CONTROL_PADCONF_SDRC_D9 0x0042 +#define CONTROL_PADCONF_SDRC_D10 0x0044 +#define CONTROL_PADCONF_SDRC_D11 0x0046 +#define CONTROL_PADCONF_SDRC_D12 0x0048 +#define CONTROL_PADCONF_SDRC_D13 0x004A +#define CONTROL_PADCONF_SDRC_D14 0x004C +#define CONTROL_PADCONF_SDRC_D15 0x004E +#define CONTROL_PADCONF_SDRC_D16 0x0050 +#define CONTROL_PADCONF_SDRC_D17 0x0052 +#define CONTROL_PADCONF_SDRC_D18 0x0054 +#define CONTROL_PADCONF_SDRC_D19 0x0056 +#define CONTROL_PADCONF_SDRC_D20 0x0058 +#define CONTROL_PADCONF_SDRC_D21 0x005A +#define CONTROL_PADCONF_SDRC_D22 0x005C +#define CONTROL_PADCONF_SDRC_D23 0x005E +#define CONTROL_PADCONF_SDRC_D24 0x0060 +#define CONTROL_PADCONF_SDRC_D25 0x0062 +#define CONTROL_PADCONF_SDRC_D26 0x0064 +#define CONTROL_PADCONF_SDRC_D27 0x0066 +#define CONTROL_PADCONF_SDRC_D28 0x0068 +#define CONTROL_PADCONF_SDRC_D29 0x006A +#define CONTROL_PADCONF_SDRC_D30 0x006C +#define CONTROL_PADCONF_SDRC_D31 0x006E +#define CONTROL_PADCONF_SDRC_CLK 0x0070 +#define CONTROL_PADCONF_SDRC_DQS0 0x0072 +#define CONTROL_PADCONF_SDRC_DQS1 0x0074 +#define CONTROL_PADCONF_SDRC_DQS2 0x0076 +#define CONTROL_PADCONF_SDRC_DQS3 0x0078 +/* GPMC */ +#define CONTROL_PADCONF_GPMC_A1 0x007A +#define CONTROL_PADCONF_GPMC_A2 0x007C +#define CONTROL_PADCONF_GPMC_A3 0x007E +#define CONTROL_PADCONF_GPMC_A4 0x0080 +#define CONTROL_PADCONF_GPMC_A5 0x0082 +#define CONTROL_PADCONF_GPMC_A6 0x0084 +#define CONTROL_PADCONF_GPMC_A7 0x0086 +#define CONTROL_PADCONF_GPMC_A8 0x0088 +#define CONTROL_PADCONF_GPMC_A9 0x008A +#define CONTROL_PADCONF_GPMC_A10 0x008C +#define CONTROL_PADCONF_GPMC_D0 0x008E +#define CONTROL_PADCONF_GPMC_D1 0x0090 +#define CONTROL_PADCONF_GPMC_D2 0x0092 +#define CONTROL_PADCONF_GPMC_D3 0x0094 +#define CONTROL_PADCONF_GPMC_D4 0x0096 +#define CONTROL_PADCONF_GPMC_D5 0x0098 +#define CONTROL_PADCONF_GPMC_D6 0x009A +#define CONTROL_PADCONF_GPMC_D7 0x009C +#define CONTROL_PADCONF_GPMC_D8 0x009E +#define CONTROL_PADCONF_GPMC_D9 0x00A0 +#define CONTROL_PADCONF_GPMC_D10 0x00A2 +#define CONTROL_PADCONF_GPMC_D11 0x00A4 +#define CONTROL_PADCONF_GPMC_D12 0x00A6 +#define CONTROL_PADCONF_GPMC_D13 0x00A8 +#define CONTROL_PADCONF_GPMC_D14 0x00AA +#define CONTROL_PADCONF_GPMC_D15 0x00AC +#define CONTROL_PADCONF_GPMC_NCS0 0x00AE +#define CONTROL_PADCONF_GPMC_NCS1 0x00B0 +#define CONTROL_PADCONF_GPMC_NCS2 0x00B2 +#define CONTROL_PADCONF_GPMC_NCS3 0x00B4 +#define CONTROL_PADCONF_GPMC_NCS4 0x00B6 +#define CONTROL_PADCONF_GPMC_NCS5 0x00B8 +#define CONTROL_PADCONF_GPMC_NCS6 0x00BA +#define CONTROL_PADCONF_GPMC_NCS7 0x00BC +#define CONTROL_PADCONF_GPMC_CLK 0x00BE +#define CONTROL_PADCONF_GPMC_NADV_ALE 0x00C0 +#define CONTROL_PADCONF_GPMC_NOE 0x00C2 +#define CONTROL_PADCONF_GPMC_NWE 0x00C4 +#define CONTROL_PADCONF_GPMC_NBE0_CLE 0x00C6 +#define CONTROL_PADCONF_GPMC_NBE1 0x00C8 +#define CONTROL_PADCONF_GPMC_NWP 0x00CA +#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC +#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE +#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0 +#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2 +/* DSS */ +#define CONTROL_PADCONF_DSS_PCLK 0x00D4 +#define CONTROL_PADCONF_DSS_HSYNC 0x00D6 +#define CONTROL_PADCONF_DSS_VSYNC 0x00D8 +#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA +#define CONTROL_PADCONF_DSS_DATA0 0x00DC +#define CONTROL_PADCONF_DSS_DATA1 0x00DE +#define CONTROL_PADCONF_DSS_DATA2 0x00E0 +#define CONTROL_PADCONF_DSS_DATA3 0x00E2 +#define CONTROL_PADCONF_DSS_DATA4 0x00E4 +#define CONTROL_PADCONF_DSS_DATA5 0x00E6 +#define CONTROL_PADCONF_DSS_DATA6 0x00E8 +#define CONTROL_PADCONF_DSS_DATA7 0x00EA +#define CONTROL_PADCONF_DSS_DATA8 0x00EC +#define CONTROL_PADCONF_DSS_DATA9 0x00EE +#define CONTROL_PADCONF_DSS_DATA10 0x00F0 +#define CONTROL_PADCONF_DSS_DATA11 0x00F2 +#define CONTROL_PADCONF_DSS_DATA12 0x00F4 +#define CONTROL_PADCONF_DSS_DATA13 0x00F6 +#define CONTROL_PADCONF_DSS_DATA14 0x00F8 +#define CONTROL_PADCONF_DSS_DATA15 0x00FA +#define CONTROL_PADCONF_DSS_DATA16 0x00FC +#define CONTROL_PADCONF_DSS_DATA17 0x00FE +#define CONTROL_PADCONF_DSS_DATA18 0x0100 +#define CONTROL_PADCONF_DSS_DATA19 0x0102 +#define CONTROL_PADCONF_DSS_DATA20 0x0104 +#define CONTROL_PADCONF_DSS_DATA21 0x0106 +#define CONTROL_PADCONF_DSS_DATA22 0x0108 +#define CONTROL_PADCONF_DSS_DATA23 0x010A +/* CAMERA */ +#define CONTROL_PADCONF_CAM_HS 0x010C +#define CONTROL_PADCONF_CAM_VS 0x010E +#define CONTROL_PADCONF_CAM_XCLKA 0x0110 +#define CONTROL_PADCONF_CAM_PCLK 0x0112 +#define CONTROL_PADCONF_CAM_FLD 0x0114 +#define CONTROL_PADCONF_CAM_D0 0x0116 +#define CONTROL_PADCONF_CAM_D1 0x0118 +#define CONTROL_PADCONF_CAM_D2 0x011A +#define CONTROL_PADCONF_CAM_D3 0x011C +#define CONTROL_PADCONF_CAM_D4 0x011E +#define CONTROL_PADCONF_CAM_D5 0x0120 +#define CONTROL_PADCONF_CAM_D6 0x0122 +#define CONTROL_PADCONF_CAM_D7 0x0124 +#define CONTROL_PADCONF_CAM_D8 0x0126 +#define CONTROL_PADCONF_CAM_D9 0x0128 +#define CONTROL_PADCONF_CAM_D10 0x012A +#define CONTROL_PADCONF_CAM_D11 0x012C +#define CONTROL_PADCONF_CAM_XCLKB 0x012E +#define CONTROL_PADCONF_CAM_WEN 0x0130 +#define CONTROL_PADCONF_CAM_STROBE 0x0132 +#define CONTROL_PADCONF_CSI2_DX0 0x0134 +#define CONTROL_PADCONF_CSI2_DY0 0x0136 +#define CONTROL_PADCONF_CSI2_DX1 0x0138 +#define CONTROL_PADCONF_CSI2_DY1 0x013A +/* Audio Interface */ +#define CONTROL_PADCONF_MCBSP2_FSX 0x013C +#define CONTROL_PADCONF_MCBSP2_CLKX 0x013E +#define CONTROL_PADCONF_MCBSP2_DR 0x0140 +#define CONTROL_PADCONF_MCBSP2_DX 0x0142 +#define CONTROL_PADCONF_ +#define CONTROL_PADCONF_MMC1_CLK 0x0144 +#define CONTROL_PADCONF_MMC1_CMD 0x0146 +#define CONTROL_PADCONF_MMC1_DAT0 0x0148 +#define CONTROL_PADCONF_MMC1_DAT1 0x014A +#define CONTROL_PADCONF_MMC1_DAT2 0x014C +#define CONTROL_PADCONF_MMC1_DAT3 0x014E +#define CONTROL_PADCONF_MMC1_DAT4 0x0150 +#define CONTROL_PADCONF_MMC1_DAT5 0x0152 +#define CONTROL_PADCONF_MMC1_DAT6 0x0154 +#define CONTROL_PADCONF_MMC1_DAT7 0x0156 +/* WirelesS LAN */ +#define CONTROL_PADCONF_MMC2_CLK 0x0158 +#define CONTROL_PADCONF_MMC2_CMD 0x015A +#define CONTROL_PADCONF_MMC2_DAT0 0x015C +#define CONTROL_PADCONF_MMC2_DAT1 0x015E +#define CONTROL_PADCONF_MMC2_DAT2 0x0160 +#define CONTROL_PADCONF_MMC2_DAT3 0x0162 +#define CONTROL_PADCONF_MMC2_DAT4 0x0164 +#define CONTROL_PADCONF_MMC2_DAT5 0x0166 +#define CONTROL_PADCONF_MMC2_DAT6 0x0168 +#define CONTROL_PADCONF_MMC2_DAT7 0x016A +/* Bluetooth */ +#define CONTROL_PADCONF_MCBSP3_DX 0x016C +#define CONTROL_PADCONF_MCBSP3_DR 0x016E +#define CONTROL_PADCONF_MCBSP3_CLKX 0x0170 +#define CONTROL_PADCONF_MCBSP3_FSX 0x0172 +#define CONTROL_PADCONF_UART2_CTS 0x0174 +#define CONTROL_PADCONF_UART2_RTS 0x0176 +#define CONTROL_PADCONF_UART2_TX 0x0178 +#define CONTROL_PADCONF_UART2_RX 0x017A +/* Modem Interface */ +#define CONTROL_PADCONF_UART1_TX 0x017C +#define CONTROL_PADCONF_UART1_RTS 0x017E +#define CONTROL_PADCONF_UART1_CTS 0x0180 +#define CONTROL_PADCONF_UART1_RX 0x0182 +#define CONTROL_PADCONF_MCBSP4_CLKX 0x0184 +#define CONTROL_PADCONF_MCBSP4_DR 0x0186 +#define CONTROL_PADCONF_MCBSP4_DX 0x0188 +#define CONTROL_PADCONF_MCBSP4_FSX 0x018A +#define CONTROL_PADCONF_MCBSP1_CLKR 0x018C +#define CONTROL_PADCONF_MCBSP1_FSR 0x018E +#define CONTROL_PADCONF_MCBSP1_DX 0x0190 +#define CONTROL_PADCONF_MCBSP1_DR 0x0192 +#define CONTROL_PADCONF_MCBSP_CLKS 0x0194 +#define CONTROL_PADCONF_MCBSP1_FSX 0x0196 +#define CONTROL_PADCONF_MCBSP1_CLKX 0x0198 +/* Serial Interface */ +#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A +#define CONTROL_PADCONF_UART3_RTS_SD 0x019C +#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E +#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0 +#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2 +#define CONTROL_PADCONF_HSUSB0_STP 0x01A4 +#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6 +#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8 +#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA +#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC +#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE +#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0 +#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2 +#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4 +#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6 +#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8 +#define CONTROL_PADCONF_I2C1_SCL 0x01BA +#define CONTROL_PADCONF_I2C1_SDA 0x01BC +#define CONTROL_PADCONF_I2C2_SCL 0x01BE +#define CONTROL_PADCONF_I2C2_SDA 0x01C0 +#define CONTROL_PADCONF_I2C3_SCL 0x01C2 +#define CONTROL_PADCONF_I2C3_SDA 0x01C4 +#define CONTROL_PADCONF_I2C4_SCL 0x0A00 +#define CONTROL_PADCONF_I2C4_SDA 0x0A02 +#define CONTROL_PADCONF_HDQ_SIO 0x01C6 +#define CONTROL_PADCONF_MCSPI1_CLK 0x01C8 +#define CONTROL_PADCONF_MCSPI1_SIMO 0x01CA +#define CONTROL_PADCONF_MCSPI1_SOMI 0x01CC +#define CONTROL_PADCONF_MCSPI1_CS0 0x01CE +#define CONTROL_PADCONF_MCSPI1_CS1 0x01D0 +#define CONTROL_PADCONF_MCSPI1_CS2 0x01D2 +#define CONTROL_PADCONF_MCSPI1_CS3 0x01D4 +#define CONTROL_PADCONF_MCSPI2_CLK 0x01D6 +#define CONTROL_PADCONF_MCSPI2_SIMO 0x01D8 +#define CONTROL_PADCONF_MCSPI2_SOMI 0x01DA +#define CONTROL_PADCONF_MCSPI2_CS0 0x01DC +#define CONTROL_PADCONF_MCSPI2_CS1 0x01DE +/* Control and debug */ +#define CONTROL_PADCONF_SYS_32K 0x0A04 +#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 +#define CONTROL_PADCONF_SYS_NIRQ 0x01E0 +#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A +#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C +#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E +#define CONTROL_PADCONF_SYS_BOOT3 0x0A10 +#define CONTROL_PADCONF_SYS_BOOT4 0x0A12 +#define CONTROL_PADCONF_SYS_BOOT5 0x0A14 +#define CONTROL_PADCONF_SYS_BOOT6 0x0A16 +#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 +#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A +#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 +#define CONTROL_PADCONF_JTAG_NTRST 0x0A1C +#define CONTROL_PADCONF_JTAG_TCK 0x0A1E +#define CONTROL_PADCONF_JTAG_TMS 0x0A20 +#define CONTROL_PADCONF_JTAG_TDI 0x0A22 +#define CONTROL_PADCONF_JTAG_EMU0 0x0A24 +#define CONTROL_PADCONF_JTAG_EMU1 0x0A26 +#define CONTROL_PADCONF_ETK_CLK 0x0A28 +#define CONTROL_PADCONF_ETK_CTL 0x0A2A +#define CONTROL_PADCONF_ETK_D0 0x0A2C +#define CONTROL_PADCONF_ETK_D1 0x0A2E +#define CONTROL_PADCONF_ETK_D2 0x0A30 +#define CONTROL_PADCONF_ETK_D3 0x0A32 +#define CONTROL_PADCONF_ETK_D4 0x0A34 +#define CONTROL_PADCONF_ETK_D5 0x0A36 +#define CONTROL_PADCONF_ETK_D6 0x0A38 +#define CONTROL_PADCONF_ETK_D7 0x0A3A +#define CONTROL_PADCONF_ETK_D8 0x0A3C +#define CONTROL_PADCONF_ETK_D9 0x0A3E +#define CONTROL_PADCONF_ETK_D10 0x0A40 +#define CONTROL_PADCONF_ETK_D11 0x0A42 +#define CONTROL_PADCONF_ETK_D12 0x0A44 +#define CONTROL_PADCONF_ETK_D13 0x0A46 +#define CONTROL_PADCONF_ETK_D14 0x0A48 +#define CONTROL_PADCONF_ETK_D15 0x0A4A +#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8 +#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA +#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC +#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE +#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0 +#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2 +#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4 +#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6 +#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8 +#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA +#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC +#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE +#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0 +#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2 +#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4 +#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6 +#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 +#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA +/* Die to die */ +#define CONTROL_PADCONF_D2D_MCAD0 0x01E4 +#define CONTROL_PADCONF_D2D_MCAD1 0x01E6 +#define CONTROL_PADCONF_D2D_MCAD2 0x01E8 +#define CONTROL_PADCONF_D2D_MCAD3 0x01EA +#define CONTROL_PADCONF_D2D_MCAD4 0x01EC +#define CONTROL_PADCONF_D2D_MCAD5 0x01EE +#define CONTROL_PADCONF_D2D_MCAD6 0x01F0 +#define CONTROL_PADCONF_D2D_MCAD7 0x01F2 +#define CONTROL_PADCONF_D2D_MCAD8 0x01F4 +#define CONTROL_PADCONF_D2D_MCAD9 0x01F6 +#define CONTROL_PADCONF_D2D_MCAD10 0x01F8 +#define CONTROL_PADCONF_D2D_MCAD11 0x01FA +#define CONTROL_PADCONF_D2D_MCAD12 0x01FC +#define CONTROL_PADCONF_D2D_MCAD13 0x01FE +#define CONTROL_PADCONF_D2D_MCAD14 0x0200 +#define CONTROL_PADCONF_D2D_MCAD15 0x0202 +#define CONTROL_PADCONF_D2D_MCAD16 0x0204 +#define CONTROL_PADCONF_D2D_MCAD17 0x0206 +#define CONTROL_PADCONF_D2D_MCAD18 0x0208 +#define CONTROL_PADCONF_D2D_MCAD19 0x020A +#define CONTROL_PADCONF_D2D_MCAD20 0x020C +#define CONTROL_PADCONF_D2D_MCAD21 0x020E +#define CONTROL_PADCONF_D2D_MCAD22 0x0210 +#define CONTROL_PADCONF_D2D_MCAD23 0x0212 +#define CONTROL_PADCONF_D2D_MCAD24 0x0214 +#define CONTROL_PADCONF_D2D_MCAD25 0x0216 +#define CONTROL_PADCONF_D2D_MCAD26 0x0218 +#define CONTROL_PADCONF_D2D_MCAD27 0x021A +#define CONTROL_PADCONF_D2D_MCAD28 0x021C +#define CONTROL_PADCONF_D2D_MCAD29 0x021E +#define CONTROL_PADCONF_D2D_MCAD30 0x0220 +#define CONTROL_PADCONF_D2D_MCAD31 0x0222 +#define CONTROL_PADCONF_D2D_MCAD32 0x0224 +#define CONTROL_PADCONF_D2D_MCAD33 0x0226 +#define CONTROL_PADCONF_D2D_MCAD34 0x0228 +#define CONTROL_PADCONF_D2D_MCAD35 0x022A +#define CONTROL_PADCONF_D2D_MCAD36 0x022C +#define CONTROL_PADCONF_D2D_CLK26MI 0x022E +#define CONTROL_PADCONF_D2D_NRESPWRON 0x0230 +#define CONTROL_PADCONF_D2D_NRESWARM 0x0232 +#define CONTROL_PADCONF_D2D_ARM9NIRQ 0x0234 +#define CONTROL_PADCONF_D2D_UMA2P6FIQ 0x0236 +#define CONTROL_PADCONF_D2D_SPINT 0x0238 +#define CONTROL_PADCONF_D2D_FRINT 0x023A +#define CONTROL_PADCONF_D2D_DMAREQ0 0x023C +#define CONTROL_PADCONF_D2D_DMAREQ1 0x023E +#define CONTROL_PADCONF_D2D_DMAREQ2 0x0240 +#define CONTROL_PADCONF_D2D_DMAREQ3 0x0242 +#define CONTROL_PADCONF_D2D_N3GTRST 0x0244 +#define CONTROL_PADCONF_D2D_N3GTDI 0x0246 +#define CONTROL_PADCONF_D2D_N3GTDO 0x0248 +#define CONTROL_PADCONF_D2D_N3GTMS 0x024A +#define CONTROL_PADCONF_D2D_N3GTCK 0x024C +#define CONTROL_PADCONF_D2D_N3GRTCK 0x024E +#define CONTROL_PADCONF_D2D_MSTDBY 0x0250 +#define CONTROL_PADCONF_D2D_SWAKEUP 0x0A4C +#define CONTROL_PADCONF_D2D_IDLEREQ 0x0252 +#define CONTROL_PADCONF_D2D_IDLEACK 0x0254 +#define CONTROL_PADCONF_D2D_MWRITE 0x0256 +#define CONTROL_PADCONF_D2D_SWRITE 0x0258 +#define CONTROL_PADCONF_D2D_MREAD 0x025A +#define CONTROL_PADCONF_D2D_SREAD 0x025C +#define CONTROL_PADCONF_D2D_MBUSFLAG 0x025E +#define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260 +#define CONTROL_PADCONF_SDRC_CKE0 0x0262 +#define CONTROL_PADCONF_SDRC_CKE1 0x0264 + +#endif /* _ASM_ARCH_OMAP3_MUX_H_ */ diff --git a/arch/arm/mach-omap/include/mach/omap3-silicon.h b/arch/arm/mach-omap/include/mach/omap3-silicon.h new file mode 100644 index 0000000000..dde241272f --- /dev/null +++ b/arch/arm/mach-omap/include/mach/omap3-silicon.h @@ -0,0 +1,130 @@ +/** + * @file + * @brief This file contains the processor specific definitions of + * the TI OMAP34XX. For more info on OMAP34XX, + * See http://focus.ti.com/pdfs/wtbu/swpu114g.pdf + * + * FileName: include/asm-arm/arch-omap/omap3-silicon.h + * + * OMAP34XX base address defines go here. + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz + * include/asm-arm/arch-omap/omap3-silicon.h + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * Copyright (C) 2007 Texas Instruments, <www.ti.com> + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP3_H +#define __ASM_ARCH_OMAP3_H + +/* PLEASE PLACE ONLY BASE DEFINES HERE */ + +/** OMAP Internal Bus Base addresses */ +#define OMAP_L4_CORE_BASE 0x48000000 +#define OMAP_INTC_BASE 0x48200000 +#define OMAP_L4_WKUP_BASE 0x48300000 +#define OMAP_L4_PER_BASE 0x49000000 +#define OMAP_L4_EMU_BASE 0x54000000 +#define OMAP_SGX_BASE 0x50000000 +#define OMAP_IVA_BASE 0x5C000000 +#define OMAP_SMX_APE_BASE 0x68000000 +#define OMAP_SMS_BASE 0x6C000000 +#define OMAP_SDRC_BASE 0x6D000000 +#define OMAP_GPMC_BASE 0x6E000000 + +/** Peripheral Base Addresses */ +#define OMAP_CTRL_BASE (OMAP_L4_CORE_BASE + 0x02000) +#define OMAP_CM_BASE (OMAP_L4_CORE_BASE + 0x04000) +#define OMAP_PRM_BASE (OMAP_L4_WKUP_BASE + 0x06000) + +#define OMAP_UART1_BASE (OMAP_L4_CORE_BASE + 0x6A000) +#define OMAP_UART2_BASE (OMAP_L4_CORE_BASE + 0x6C000) +#define OMAP_UART3_BASE (OMAP_L4_PER_BASE + 0x20000) + +#define OMAP_I2C1_BASE (OMAP_L4_CORE_BASE + 0x70000) +#define OMAP_I2C2_BASE (OMAP_L4_CORE_BASE + 0x72000) +#define OMAP_I2C3_BASE (OMAP_L4_CORE_BASE + 0x60000) + +#define OMAP_GPTIMER1_BASE (OMAP_L4_WKUP_BASE + 0x18000) +#define OMAP_GPTIMER2_BASE (OMAP_L4_PER_BASE + 0x32000) +#define OMAP_GPTIMER3_BASE (OMAP_L4_PER_BASE + 0x34000) +#define OMAP_GPTIMER4_BASE (OMAP_L4_PER_BASE + 0x36000) +#define OMAP_GPTIMER5_BASE (OMAP_L4_PER_BASE + 0x38000) +#define OMAP_GPTIMER6_BASE (OMAP_L4_PER_BASE + 0x3A000) +#define OMAP_GPTIMER7_BASE (OMAP_L4_PER_BASE + 0x3C000) +#define OMAP_GPTIMER8_BASE (OMAP_L4_PER_BASE + 0x3E000) +#define OMAP_GPTIMER9_BASE (OMAP_L4_PER_BASE + 0x40000) +#define OMAP_GPTIMER10_BASE (OMAP_L4_CORE_BASE + 0x86000) +#define OMAP_GPTIMER11_BASE (OMAP_L4_CORE_BASE + 0x88000) + +#define OMAP_WDTIMER2_BASE (OMAP_L4_WKUP_BASE + 0x14000) +#define OMAP_WDTIMER3_BASE (OMAP_L4_PER_BASE + 0x30000) + +#define OMAP_32KTIMER_BASE (OMAP_L4_WKUP_BASE + 0x20000) + +#define OMAP_MMC1_BASE (OMAP_L4_CORE_BASE + 0x9C000) +#define OMAP_MMC2_BASE (OMAP_L4_CORE_BASE + 0xB4000) +#define OMAP_MMC3_BASE (OMAP_L4_CORE_BASE + 0xAD000) + +#define OMAP_MUSB0_BASE (OMAP_L4_CORE_BASE + 0xAB000) + +#define OMAP_GPIO1_BASE (OMAP_L4_WKUP_BASE + 0x10000) +#define OMAP_GPIO2_BASE (OMAP_L4_PER_BASE + 0x50000) +#define OMAP_GPIO3_BASE (OMAP_L4_PER_BASE + 0x52000) +#define OMAP_GPIO4_BASE (OMAP_L4_PER_BASE + 0x54000) +#define OMAP_GPIO5_BASE (OMAP_L4_PER_BASE + 0x56000) +#define OMAP_GPIO6_BASE (OMAP_L4_PER_BASE + 0x58000) + +/** MPU WDT Definition */ +#define OMAP_MPU_WDTIMER_BASE OMAP_WDTIMER2_BASE + +/** Interrupt Vector base address */ +#define OMAP_SRAM_INTVECT 0x4020F800 +#define OMAP_SRAM_INTVECT_COPYSIZE 0x64 +/** Temporary stack for us to use C calls in low_level_init */ +#define OMAP_SRAM_STACK 0x4020FFFC + +/** Gives the silicon revision */ +#define OMAP_TAP_BASE (OMAP_L4_WKUP_BASE + 0xA000) +#define IDCODE_REG (OMAP_TAP_BASE + 0x204) + +/************ Generic Chip specific Definitions **********/ +/** + * CHIP F number HAWKEYE (hex) + * OMAP3430 ES1.0 F771609 B6D6 + * OMAP3430 ES2.0 F771609A B7AE + */ +#define HAWKEYE_ES1 0x0B6D6000 +#define HAWKEYE_ES2 0x0B7AE000 +#define HAWKEYE_ES2_1 0x1B7AE000 +#define HAWKEYE_MASK 0x0FFFF000 +#define VERSION_MASK 0xF0000000 +#define DEVICE_MASK ((0x1 << 8)|(0x1 << 9)|(0x1 << 10)) + +#define OMAP_SDRC_CS0 0x80000000 +#define OMAP_SDRC_CS1 0xA0000000 + +#endif /* __ASM_ARCH_OMAP3_H */ + diff --git a/arch/arm/mach-omap/include/mach/omap3-smx.h b/arch/arm/mach-omap/include/mach/omap3-smx.h new file mode 100644 index 0000000000..78cff95f5b --- /dev/null +++ b/arch/arm/mach-omap/include/mach/omap3-smx.h @@ -0,0 +1,69 @@ +/** + * @file + * @brief This file contains the SMX specific register definitions + * + * FileName: include/asm-arm/arch-omap/omap3-smx.h + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz + * include/asm-arm/arch-omap/omap34xx.h + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * Copyright (C) 2007 Texas Instruments, <www.ti.com> + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP_SMX_H +#define __ASM_ARCH_OMAP_SMX_H + +/* SMX-APE */ +#define PM_RT_APE_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x10000) +#define PM_GPMC_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12400) +#define PM_OCM_RAM_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12800) +#define PM_OCM_ROM_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12C00) +#define PM_IVA2_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x14000) + +#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68) +#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50) +#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58) +#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60) + +#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48) +#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50) +#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58) + +#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48) +#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50) +#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58) +#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80) + +/* IVA2 */ +#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48) +#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50) +#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58) + +/* SMS */ +#define SMS_SYSCONFIG (OMAP_SMS_BASE + 0x10) +#define SMS_RG_ATT0 (OMAP_SMS_BASE + 0x48) +#define SMS_CLASS_ARB0 (OMAP_SMS_BASE + 0xD0) +#define BURSTCOMPLETE_GROUP7 (0x1 << 31) + +#endif /* __ASM_ARCH_OMAP_SMX_H */ diff --git a/arch/arm/mach-omap/include/mach/sdrc.h b/arch/arm/mach-omap/include/mach/sdrc.h new file mode 100644 index 0000000000..9d2d2d1107 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/sdrc.h @@ -0,0 +1,97 @@ +/** + * @file + * @brief This file contains the SDRC specific register definitions + * + * FileName: include/asm-arm/arch-omap/sdrc.h + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_ARCH_SDRC_H +#define _ASM_ARCH_SDRC_H + +#define SDRC_REG(REGNAME) (OMAP_SDRC_BASE + OMAP_SDRC_##REGNAME) +#define OMAP_SDRC_SYSCONFIG (0x10) +#define OMAP_SDRC_STATUS (0x14) +#define OMAP_SDRC_CS_CFG (0x40) +#define OMAP_SDRC_SHARING (0x44) +#define OMAP_SDRC_DLLA_CTRL (0x60) +#define OMAP_SDRC_DLLA_STATUS (0x64) +#define OMAP_SDRC_DLLB_CTRL (0x68) +#define OMAP_SDRC_DLLB_STATUS (0x6C) +#define DLLPHASE (0x1 << 1) +#define LOADDLL (0x1 << 2) +#define DLL_DELAY_MASK 0xFF00 +#define DLL_NO_FILTER_MASK ((0x1 << 8)|(0x1 << 9)) + +#define OMAP_SDRC_POWER (0x70) +#define WAKEUPPROC (0x1 << 26) + +#define OMAP_SDRC_MCFG_0 (0x80) +#define OMAP_SDRC_MCFG_1 (0xB0) +#define OMAP_SDRC_MR_0 (0x84) +#define OMAP_SDRC_MR_1 (0xB4) +#define OMAP_SDRC_ACTIM_CTRLA_0 (0x9C) +#define OMAP_SDRC_ACTIM_CTRLB_0 (0xA0) +#define OMAP_SDRC_ACTIM_CTRLA_1 (0xC4) +#define OMAP_SDRC_ACTIM_CTRLB_1 (0xC8) +#define OMAP_SDRC_RFR_CTRL_0 (0xA4) +#define OMAP_SDRC_RFR_CTRL_1 (0xD4) +#define OMAP_SDRC_MANUAL_0 (0xA8) +#define CMD_NOP 0x0 +#define CMD_PRECHARGE 0x1 +#define CMD_AUTOREFRESH 0x2 +#define CMD_ENTR_PWRDOWN 0x3 +#define CMD_EXIT_PWRDOWN 0x4 +#define CMD_ENTR_SRFRSH 0x5 +#define CMD_CKE_HIGH 0x6 +#define CMD_CKE_LOW 0x7 +#define SOFTRESET (0x1 << 1) +#define SMART_IDLE (0x2 << 3) +#define REF_ON_IDLE (0x1 << 6) + +#define SDRC_CS0_OSET 0x0 +/* Mirror CS1 regs appear offset 0x30 from CS0 */ +#define SDRC_CS1_OSET 0x30 + +#define SDRC_STACKED 0 +#define SDRC_IP_DDR 1 +#define SDRC_COMBO_DDR 2 +#define SDRC_IP_SDR 3 + + +#define SDRC_B_R_C (0 << 6) /* bank-row-column */ +#define SDRC_B1_R_B0_C (1 << 6) /* bank1-row-bank0-column */ +#define SDRC_R_B_C (2 << 6) /* row-bank-column */ + +#define DLL_OFFSET 0 +#define DLL_WRITEDDRCLKX2DIS 1 +#define DLL_ENADLL 1 +#define DLL_LOCKDLL 0 +#define DLL_DLLPHASE_72 0 +#define DLL_DLLPHASE_90 1 + +#endif /* _ASM_ARCH_SDRC_H */ diff --git a/arch/arm/mach-omap/include/mach/silicon.h b/arch/arm/mach-omap/include/mach/silicon.h new file mode 100644 index 0000000000..22daa5c964 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/silicon.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_OMAP_SILICON_H +#define __ASM_ARCH_OMAP_SILICON_H + +/* Each platform silicon header comes here */ +#ifdef CONFIG_ARCH_OMAP3 +#include <mach/omap3-silicon.h> +#endif + +/* If Architecture specific init functions are present */ +#ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT +#ifndef __ASSEMBLY__ +void a_init(void); +#endif /* __ASSEMBLY__ */ +#endif + +#endif /* __ASM_ARCH_OMAP_SILICON_H */ diff --git a/arch/arm/mach-omap/include/mach/sys_info.h b/arch/arm/mach-omap/include/mach/sys_info.h new file mode 100644 index 0000000000..43967209f1 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/sys_info.h @@ -0,0 +1,97 @@ +/** + * @file + * @brief This file defines the macros apis which are useful for most OMAP + * platforms. + * + * FileName: include/asm-arm/arch-omap/sys_info.h + * + * These are implemented by the System specific code in omapX-generic.c + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_SYS_INFO_H_ +#define __ASM_ARCH_SYS_INFO_H_ + +#define XDR_POP 5 /* package on package part */ +#define SDR_DISCRETE 4 /* 128M memory SDR module*/ +#define DDR_STACKED 3 /* stacked part on 2422 */ +#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ +#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ + +#define DDR_100 100 /* type found on most mem d-boards */ +#define DDR_111 111 /* some combo parts */ +#define DDR_133 133 /* most combo, some mem d-boards */ +#define DDR_165 165 /* future parts */ + +#define CPU_3430 0x3430 +#define CPU_2430 0x2430 +#define CPU_2420 0x2420 +#define CPU_1710 0x1710 +#define CPU_1610 0x1610 + +/** + * CPU revision + */ +#define CPU_ES1 1 +#define CPU_ES1P1 2 +#define CPU_ES1P2 3 +#define CPU_ES2 4 +#define CPU_ES2P1 5 +#define CPU_ES2P2 6 +#define CPU_ES3 7 +#define CPU_ES3P1 8 +#define CPU_ES3P2 9 +#define CPU_ES4 10 +#define CPU_ES4P1 11 +#define CPU_ES4P2 12 + +#define GPMC_MUXED 1 +#define GPMC_NONMUXED 0 + +#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ +#define TYPE_NOR 0x000 +#define TYPE_ONENAND 0x800 + +#define WIDTH_8BIT 0x0000 +#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ + +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + +/** These are implemented by the System specific code in omapX-generic.c */ +u32 get_cpu_type(void); +u32 get_cpu_rev(void); +u32 get_sdr_cs_size(u32 offset); +inline u32 get_sysboot_value(void); +u32 get_gpmc0_base(void); +u32 get_base(void); +u32 running_in_flash(void); +u32 running_in_sram(void); +u32 running_in_sdram(void); +u32 get_boot_type(void); +u32 get_device_type(void); + +#endif /*__ASM_ARCH_SYS_INFO_H_ */ diff --git a/arch/arm/mach-omap/include/mach/syslib.h b/arch/arm/mach-omap/include/mach/syslib.h new file mode 100644 index 0000000000..c89f50b816 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/syslib.h @@ -0,0 +1,43 @@ +/** + * @file + * @brief These Apis are OMAP independent support functions + * + * FileName: include/asm-arm/arch-omap/syslib.h + * + * Implemented by arch/arm/mach-omap/syslib.c + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + */ +/* + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_OMAP_SYSLIB_H_ +#define __ASM_ARCH_OMAP_SYSLIB_H_ + +/** System Independent functions */ +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value); +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); +void sdelay(unsigned long loops); + +/** All architectures need to implement these */ +void omap_uart_write(unsigned int val, unsigned long base, + unsigned char reg_idx); +unsigned int omap_uart_read(unsigned long base, unsigned char reg_idx); +#endif /* __ASM_ARCH_OMAP_SYSLIB_H_ */ diff --git a/arch/arm/mach-omap/include/mach/timers.h b/arch/arm/mach-omap/include/mach/timers.h new file mode 100644 index 0000000000..a93824378c --- /dev/null +++ b/arch/arm/mach-omap/include/mach/timers.h @@ -0,0 +1,60 @@ +/** + * @file + * @brief This defines the Register defines for OMAP GPTimers and Sync32 timers. + * + * FileName: include/asm-arm/arch-omap/timers.h + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz + * + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * Copyright (C) 2007 Texas Instruments, <www.ti.com> + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_GPT_H +#define __ASM_ARCH_GPT_H + +/** General Purpose timer regs offsets (32 bit regs) */ +#define TIDR 0x0 /* r */ +#define TIOCP_CFG 0x10 /* rw */ +#define TISTAT 0x14 /* r */ +#define TISR 0x18 /* rw */ +#define TIER 0x1C /* rw */ +#define TWER 0x20 /* rw */ +#define TCLR 0x24 /* rw */ +#define TCRR 0x28 /* rw */ +#define TLDR 0x2C /* rw */ +#define TTGR 0x30 /* rw */ +#define TWPS 0x34 /* r */ +#define TMAR 0x38 /* rw */ +#define TCAR1 0x3c /* r */ +#define TSICR 0x40 /* rw */ +#define TCAR2 0x44 /* r */ +/* Enable sys_clk NO-prescale /1 */ +#define GPT_EN ((0 << 2) | (0x1 << 1) | (0x1 << 0)) + +/** Sync 32Khz Timer registers */ +#define S32K_CR (OMAP_32KTIMER_BASE + 0x10) +#define S32K_FREQUENCY 32768 + +#endif /*__ASM_ARCH_GPT_H */ diff --git a/arch/arm/mach-omap/include/mach/wdt.h b/arch/arm/mach-omap/include/mach/wdt.h new file mode 100644 index 0000000000..532252d080 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/wdt.h @@ -0,0 +1,49 @@ +/** + * @file + * @brief This file contains the Watchdog timer specific register definitions + * + * FileName: include/asm-arm/arch-omap/wdt.h + * + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_OMAP_WDT_H +#define __ASM_ARCH_OMAP_WDT_H + +/** Watchdog Register defines */ +#define WDT_REG(REGNAME) (OMAP_MPU_WDTIMER_BASE + OMAP_WDT_##REGNAME) +#define OMAP_WDT_WIDR (0x000) +#define OMAP_WDT_SYSCONFIG (0x010) +#define OMAP_WDT_WD_SYSSTATUS (0x014) +#define OMAP_WDT_WISR (0x018) +#define OMAP_WDT_WIER (0x01C) +#define OMAP_WDT_WCLR (0x024) +#define OMAP_WDT_WCRR (0x028) +#define OMAP_WDT_WLDR (0x02C) +#define OMAP_WDT_WTGR (0x030) +#define OMAP_WDT_WWPS (0x034) +#define OMAP_WDT_WSPR (0x048) + +/* Unlock Code for Watchdog timer to disable the same */ +#define WDT_DISABLE_CODE1 0xAAAA +#define WDT_DISABLE_CODE2 0x5555 + +#endif /* __ASM_ARCH_OMAP_WDT_H */ diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c index ce26cb5fac..4e81ae80d4 100644 --- a/arch/arm/mach-omap/omap3_clock.c +++ b/arch/arm/mach-omap/omap3_clock.c @@ -40,11 +40,11 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/silicon.h> -#include <asm/arch/clocks.h> -#include <asm/arch/timers.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/syslib.h> +#include <mach/silicon.h> +#include <mach/clocks.h> +#include <mach/timers.h> +#include <mach/sys_info.h> +#include <mach/syslib.h> /* Following functions are exported from omap3_clock_core.S */ #ifdef CONFIG_OMAP3_COPY_CLOCK_SRAM diff --git a/arch/arm/mach-omap/omap3_clock_core.S b/arch/arm/mach-omap/omap3_clock_core.S index 6e10563fb4..872ae5abcd 100644 --- a/arch/arm/mach-omap/omap3_clock_core.S +++ b/arch/arm/mach-omap/omap3_clock_core.S @@ -37,9 +37,9 @@ */ #include <config.h> -#include <asm/arch/silicon.h> -#include <asm/arch/clocks.h> -#include <asm/arch/gpmc.h> +#include <mach/silicon.h> +#include <mach/clocks.h> +#include <mach/gpmc.h> #ifdef CONFIG_OMAP3_COPY_CLOCK_SRAM /** diff --git a/arch/arm/mach-omap/omap3_core.S b/arch/arm/mach-omap/omap3_core.S index dece199fae..76f80e68ca 100644 --- a/arch/arm/mach-omap/omap3_core.S +++ b/arch/arm/mach-omap/omap3_core.S @@ -37,9 +37,9 @@ */ #include <config.h> -#include <asm/arch/silicon.h> -#include <asm/arch/wdt.h> -#include <asm/arch/clocks.h> +#include <mach/silicon.h> +#include <mach/wdt.h> +#include <mach/clocks.h> #ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT .globl arch_init_lowlevel diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c index 3acf911251..794d2fa8f2 100644 --- a/arch/arm/mach-omap/omap3_generic.c +++ b/arch/arm/mach-omap/omap3_generic.c @@ -37,15 +37,15 @@ #include <common.h> #include <init.h> #include <asm/io.h> -#include <asm/arch/silicon.h> -#include <asm/arch/gpmc.h> -#include <asm/arch/sdrc.h> -#include <asm/arch/control.h> -#include <asm/arch/omap3-smx.h> -#include <asm/arch/clocks.h> -#include <asm/arch/wdt.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/syslib.h> +#include <mach/silicon.h> +#include <mach/gpmc.h> +#include <mach/sdrc.h> +#include <mach/control.h> +#include <mach/omap3-smx.h> +#include <mach/clocks.h> +#include <mach/wdt.h> +#include <mach/sys_info.h> +#include <mach/syslib.h> /** * @brief Reset the CPU diff --git a/arch/arm/mach-omap/s32k_clksource.c b/arch/arm/mach-omap/s32k_clksource.c index 4166d83d75..353670c583 100644 --- a/arch/arm/mach-omap/s32k_clksource.c +++ b/arch/arm/mach-omap/s32k_clksource.c @@ -34,11 +34,11 @@ #include <clock.h> #include <init.h> #include <asm/io.h> -#include <asm/arch/silicon.h> -#include <asm/arch/clocks.h> -#include <asm/arch/timers.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/syslib.h> +#include <mach/silicon.h> +#include <mach/clocks.h> +#include <mach/timers.h> +#include <mach/sys_info.h> +#include <mach/syslib.h> /** * @brief Provide a simple clock read diff --git a/arch/arm/mach-omap/syslib.c b/arch/arm/mach-omap/syslib.c index 0ca4ef21d3..51824dadb0 100644 --- a/arch/arm/mach-omap/syslib.c +++ b/arch/arm/mach-omap/syslib.c @@ -32,7 +32,7 @@ #include <config.h> #include <asm/io.h> -#include <asm/arch/syslib.h> +#include <mach/syslib.h> /** * @brief simple spin loop |