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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-08-28 12:01:38 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-08-28 12:05:50 +0200 |
| commit | 17828c5be2c0a7c07ce7d37828276adb374abcf0 (patch) | |
| tree | 9542d17d4340ee780a015153dfeb982d3e33d086 /arch/arm/mach-omap | |
| parent | 058556a5163c68e13ce165f861b895b9f6e9ac32 (diff) | |
| download | barebox-17828c5be2c0a7c07ce7d37828276adb374abcf0.tar.gz barebox-17828c5be2c0a7c07ce7d37828276adb374abcf0.tar.xz | |
ARM: omap: am35xx_emif4: Fix bit polling
((x & (1 << 10)) == 0x1) can never be true as the compiler mourns about.
Fix this to actually do what the comment says: Wait till bit 10 is
cleared. Looking at the corresponding U-Boot code also suggests that
this is the right thing to do.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-omap')
| -rw-r--r-- | arch/arm/mach-omap/am35xx_emif4.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-omap/am35xx_emif4.c b/arch/arm/mach-omap/am35xx_emif4.c index 38fc0f02d2..678a338fd6 100644 --- a/arch/arm/mach-omap/am35xx_emif4.c +++ b/arch/arm/mach-omap/am35xx_emif4.c @@ -37,7 +37,7 @@ void am35xx_emif4_init(void) writel(regval, &emif4_base->sdram_iodft_tlgc); /* Wait till that bit clears*/ - while ((readl(&emif4_base->sdram_iodft_tlgc) & (1 << 10)) == 0x1); + while (readl(&emif4_base->sdram_iodft_tlgc) & (1 << 10)); /* Re-verify the DDR PHY status*/ while ((readl(&emif4_base->sdram_sts) & (1 << 2)) == 0x0); |