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authorJuergen Beisert <jbe@pengutronix.de>2012-07-28 17:10:43 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2012-07-30 10:17:32 +0200
commit63f57091f2e60e9b1db9a143efaa03ac26710682 (patch)
treeda1ac14eb1bcc084d465d2ca4e01a4e273304a20 /arch/arm/mach-samsung
parent1fdb1cf1c4f70f70f5f4bee1f2eeda31ed544f0c (diff)
downloadbarebox-63f57091f2e60e9b1db9a143efaa03ac26710682.tar.gz
barebox-63f57091f2e60e9b1db9a143efaa03ac26710682.tar.xz
ARM/Samsung: add S3C6410 SoC iomap
Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-samsung')
-rw-r--r--arch/arm/mach-samsung/include/mach/s3c-iomap.h3
-rw-r--r--arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h51
2 files changed, 54 insertions, 0 deletions
diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
index d34ace47cd..09a6891429 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
@@ -22,6 +22,9 @@
#ifdef CONFIG_ARCH_S3C24xx
# include <mach/s3c24xx-iomap.h>
#endif
+#ifdef CONFIG_ARCH_S3C64xx
+# include <mach/s3c64xx-iomap.h>
+#endif
#ifdef CONFIG_ARCH_S5PCxx
# include <mach/s5pcxx-iomap.h>
#endif
diff --git a/arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h b/arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h
new file mode 100644
index 0000000000..9cc3a1bcba
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* S3C64xx device base addresses */
+#define S3C_SROM_SFR 0x70000000
+#define S3C_NAND_BASE 0x70200000
+#define S3C_SDI0_BASE 0x7c200000
+#define S3C_SDI0_SIZE 0x100
+#define S3C_SDI1_BASE 0x7c300000
+#define S3C_SDI1_SIZE 0x100
+#define S3C_SDI2_BASE 0x7c400000
+#define S3C_SDI2_SIZE 0x100
+#define S3C_DRAMC 0x7e001000
+#define S3C_WATCHDOG_BASE 0x7e004000
+#define S3C_CLOCK_POWER_BASE 0x7e00f000
+#define S3C_UART_BASE 0x7f005000
+#define S3C_TIMER_BASE 0x7f006000
+#define S3C_GPIO_BASE 0x7f008000
+
+#define S3C_UART1_BASE (S3C_UART_BASE)
+#define S3C_UART1_SIZE 0x400
+#define S3C_UART2_BASE (S3C_UART_BASE + 0x400)
+#define S3C_UART2_SIZE 0x400
+#define S3C_UART3_BASE (S3C_UART_BASE + 0x800)
+#define S3C_UART3_SIZE 0x400
+#define S3C_UART4_BASE (S3C_UART_BASE + 0xc00)
+#define S3C_UART4_SIZE 0x400
+
+#define S3C_SDRAM_BASE 0x50000000
+#define S3C_SDRAM_END (S3C_SDRAM_BASE + 0x10000000)
+
+#define S3C_SROM_BW (S3C_SROM_SFR)
+#define S3C_SROM_BC0 (S3C_SROM_SFR + 4)
+
+#define S3C_CS0_BASE 0x10000000
+#define S3C_CS1_BASE 0x18000000
+#define S3C_CS2_BASE 0x20000000
+#define S3C_CS3_BASE 0x28000000
+#define S3C_CS4_BASE 0x30000000
+#define S3C_CS5_BASE 0x38000000