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authorSteffen Trumtrar <s.trumtrar@pengutronix.de>2017-04-28 16:41:41 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2017-05-03 13:51:22 +0200
commitd5c8bc3ff1a795cb9ef44abd518f5dae6f9000fa (patch)
treea3dbd48b1feef91687bd75e9227870debbbbf9cb /arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h
parentdb3feb61d19060a0589f3906a8a081bebd934ace (diff)
downloadbarebox-d5c8bc3ff1a795cb9ef44abd518f5dae6f9000fa.tar.gz
ARM: socfpga: add arria10 support
Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that is already supported in barebox. Both a the same in some parts, but totaly different in others. Most of the hardware blocks are the same in the SoC parts. The OCRAM is larger on the Arria10 and the SDRAM controller is different. The serial core only supports 32bit accesses (different to the 8bit accesses on the Cyclone5). As Arria10 has 256KB of OCRAM, it is possible to fit a larger barebox (and/or use PBL) instead of the two stage bootprocess used on the Cyclone5 and its 64KB OCRAM. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h')
-rw-r--r--arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h114
1 files changed, 114 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h b/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h
new file mode 100644
index 0000000..ebd2043
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ARRIA10_RESET_MANAGER_H_
+#define _ARRIA10_RESET_MANAGER_H_
+
+#define ARRIA10_RSTMGR_STATUS 0x0
+#define ARRIA10_RSTMGR_RAMSTAT 0x4
+#define ARRIA10_RSTMGR_MISCSTAT 0x8
+#define ARRIA10_RSTMGR_CTRL 0xc
+#define ARRIA10_RSTMGR_HDSKEN 0x10
+#define ARRIA10_RSTMGR_HDSKREQ 0x14
+#define ARRIA10_RSTMGR_HDSKACK 0x18
+#define ARRIA10_RSTMGR_COUNTS 0x1c
+#define ARRIA10_RSTMGR_MPUMODRST 0x20
+#define ARRIA10_RSTMGR_PER0MODRST 0x24
+#define ARRIA10_RSTMGR_PER1MODRST 0x28
+#define ARRIA10_RSTMGR_BRGMODRST 0x2c
+#define ARRIA10_RSTMGR_SYSMODRST 0x30
+#define ARRIA10_RSTMGR_COLDMODRST 0x34
+#define ARRIA10_RSTMGR_NRSTMODRST 0x38
+#define ARRIA10_RSTMGR_DBGMODRST 0x3c
+#define ARRIA10_RSTMGR_MPUWARMMASK 0x40
+#define ARRIA10_RSTMGR_PER0WARMMASK 0x44
+#define ARRIA10_RSTMGR_PER1WARMMASK 0x48
+#define ARRIA10_RSTMGR_BRGWARMMASK 0x4c
+#define ARRIA10_RSTMGR_SYSWARMMASK 0x50
+#define ARRIA10_RSTMGR_NRSTWARMMASK 0x54
+#define ARRIA10_RSTMGR_L3WARMMASK 0x58
+#define ARRIA10_RSTMGR_TSTSTA 0x5c
+#define ARRIA10_RSTMGR_TSTSCRATCH 0x60
+#define ARRIA10_RSTMGR_HDSKTIMEOUT 0x64
+#define ARRIA10_RSTMGR_HMCINTR 0x68
+#define ARRIA10_RSTMGR_HMCINTREN 0x6c
+#define ARRIA10_RSTMGR_HMCINTRENS 0x70
+#define ARRIA10_RSTMGR_HMCINTRENR 0x74
+#define ARRIA10_RSTMGR_HMCGPOUT 0x78
+#define ARRIA10_RSTMGR_HMCGPIN 0x7c
+
+#define ARRIA10_RSTMGR_CTL_SWWARMRSTREQ BIT(1)
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC0 BIT(0)
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC1 BIT(1)
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC2 BIT(2)
+#define ARRIA10_RSTMGR_PER0MODRST_USB0 BIT(3)
+#define ARRIA10_RSTMGR_PER0MODRST_USB1 BIT(4)
+#define ARRIA10_RSTMGR_PER0MODRST_NAND BIT(5)
+#define ARRIA10_RSTMGR_PER0MODRST_QSPI BIT(6)
+#define ARRIA10_RSTMGR_PER0MODRST_SDMMC BIT(7)
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP BIT(8)
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP BIT(9)
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP BIT(10)
+#define ARRIA10_RSTMGR_PER0MODRST_USB0OCP BIT(11)
+#define ARRIA10_RSTMGR_PER0MODRST_USB1OCP BIT(12)
+#define ARRIA10_RSTMGR_PER0MODRST_NANDOCP BIT(13)
+#define ARRIA10_RSTMGR_PER0MODRST_QSPIOCP BIT(14)
+#define ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP BIT(15)
+#define ARRIA10_RSTMGR_PER0MODRST_DMA BIT(16)
+#define ARRIA10_RSTMGR_PER0MODRST_SPIM0 BIT(17)
+#define ARRIA10_RSTMGR_PER0MODRST_SPIM1 BIT(18)
+#define ARRIA10_RSTMGR_PER0MODRST_SPIS0 BIT(19)
+#define ARRIA10_RSTMGR_PER0MODRST_SPIS1 BIT(20)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAOCP BIT(21)
+#define ARRIA10_RSTMGR_PER0MODRST_EMACPTP BIT(22)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF0 BIT(24)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF1 BIT(25)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF2 BIT(26)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF3 BIT(27)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF4 BIT(28)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF5 BIT(29)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF6 BIT(30)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF7 BIT(31)
+
+#define ARRIA10_RSTMGR_PER1MODRST_WATCHDOG0 BIT(0)
+#define ARRIA10_RSTMGR_PER1MODRST_WATCHDOG1 BIT(1)
+#define ARRIA10_RSTMGR_PER1MODRST_L4SYSTIMER0 BIT(2)
+#define ARRIA10_RSTMGR_PER1MODRST_L4SYSTIMER1 BIT(3)
+#define ARRIA10_RSTMGR_PER1MODRST_SPTIMER0 BIT(4)
+#define ARRIA10_RSTMGR_PER1MODRST_SPTIMER1 BIT(5)
+#define ARRIA10_RSTMGR_PER1MODRST_I2C0 BIT(8)
+#define ARRIA10_RSTMGR_PER1MODRST_I2C1 BIT(9)
+#define ARRIA10_RSTMGR_PER1MODRST_I2C2 BIT(10)
+#define ARRIA10_RSTMGR_PER1MODRST_I2C3 BIT(11)
+#define ARRIA10_RSTMGR_PER1MODRST_I2C4 BIT(12)
+#define ARRIA10_RSTMGR_PER1MODRST_UART0 BIT(16)
+#define ARRIA10_RSTMGR_PER1MODRST_UART1 BIT(17)
+#define ARRIA10_RSTMGR_PER1MODRST_GPIO0 BIT(24)
+#define ARRIA10_RSTMGR_PER1MODRST_GPIO1 BIT(25)
+#define ARRIA10_RSTMGR_PER1MODRST_GPIO2 BIT(26)
+
+#define ARRIA10_RSTMGR_BRGMODRST_HPS2FPGA BIT(0)
+#define ARRIA10_RSTMGR_BRGMODRST_LWHPS2FPGA BIT(1)
+#define ARRIA10_RSTMGR_BRGMODRST_FPGA2HPS BIT(2)
+#define ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM0 BIT(3)
+#define ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM1 BIT(4)
+#define ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM2 BIT(5)
+#define ARRIA10_RSTMGR_BRGMODRST_DDRSCH BIT(6)
+
+#define ARRIA10_RSTMGR_OCP_MASK (ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP | \
+ ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP | \
+ ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP | \
+ ARRIA10_RSTMGR_PER0MODRST_NANDOCP | \
+ ARRIA10_RSTMGR_PER0MODRST_QSPIOCP | \
+ ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP)
+
+void arria10_reset_peripherals(void);
+void arria10_reset_deassert_dedicated_peripherals(void);
+void arria10_reset_deassert_shared_peripherals(void);
+void arria10_reset_deassert_fpga_peripherals(void);
+
+#endif
+