ARM: socfpga: add arria10 support

Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that
is already supported in barebox.
Both a the same in some parts, but totaly different in
others. Most of the hardware blocks are the same in the
SoC parts. The OCRAM is larger on the Arria10 and the
SDRAM controller is different.
The serial core only supports 32bit accesses (different to
the 8bit accesses on the Cyclone5).

As Arria10 has 256KB of OCRAM, it is possible to fit a larger
barebox (and/or use PBL) instead of the two stage bootprocess
used on the Cyclone5 and its 64KB OCRAM.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 42 insertions, 0 deletions

diff --git a/arch/arm/mach-socfpga/include/mach/barebox-arm-head.h b/arch/arm/mach-socfpga/include/mach/barebox-arm-head.h
new file mode 100644
index 0000000000..28fb1c92fc
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/barebox-arm-head.h
@@ -0,0 +1,42 @@
+static inline void __barebox_arm_head(void)
+{
+	__asm__ __volatile__ (
+#ifdef CONFIG_THUMB2_BAREBOX
+		".arm\n"
+		"adr r9, 1f + 1\n"
+		"bx r9\n"
+		".thumb\n"
+		"1:\n"
+		"bl 2f\n"
+		".rept 10\n"
+		"1: b 1b\n"
+		".endr\n"
+#else
+		"b 2f\n"
+		"1: b 1b\n"
+		"1: b 1b\n"
+		"1: b 1b\n"
+		"1: b 1b\n"
+		"1: b 1b\n"
+		"1: b 1b\n"
+		"1: b 1b\n"
+#endif
+		".asciz \"barebox\"\n"
+		".word _text\n"				/* text base. If copied there,
+							 * barebox can skip relocation
+							 */
+		".word _barebox_image_size\n"		/* image size to copy */
+
+		".rept 10\n"
+		".word 0x55555555\n"
+		".endr\n"
+		"2:\n"
+	);
+}
+static inline void barebox_arm_head(void)
+{
+	__barebox_arm_head();
+	__asm__ __volatile__ (
+		"b barebox_arm_reset_vector\n"
+	);
+}