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| author | Steffen Trumtrar <s.trumtrar@pengutronix.de> | 2018-07-31 12:44:39 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-08-08 09:22:48 +0200 |
| commit | 8a680e3c9b5dd8470b7437654877d5439e9a6407 (patch) | |
| tree | d2ca86ad8029b3b70c5754cbdc43618740b5f5d9 /arch/arm/mach-socfpga/include/mach/debug_ll.h | |
| parent | 1466d7d0e485fe43258aea423d2e4deba7d83c1e (diff) | |
| download | barebox-8a680e3c9b5dd8470b7437654877d5439e9a6407.tar.gz barebox-8a680e3c9b5dd8470b7437654877d5439e9a6407.tar.xz | |
ARM: socfpga: Arria10: support programming FPGA in PBL
Some Arria10 boards don't have the FPGA programmed externally.
Instead barebox needs to do that. As the Arria10 has the SDRAM
controller in the FPGA, the first thing we need to do is,
configure the FPGA before the SDRAM can even be used.
It works like this:
1. boot ROM fetches the PBL from MMC
2. read the MBR from MMC (this depends on the setup done by the boot ROM)
3. read the Bitstream from the MMC and program the FPGA
4. re-read the barebox image from MMC, this time with the full barebox
that is appended to the PBL
5. jump into the full barebox
Only supported boot device is eMMC.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-socfpga/include/mach/debug_ll.h')
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/debug_ll.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/debug_ll.h b/arch/arm/mach-socfpga/include/mach/debug_ll.h index f41258c504..3264934e6d 100644 --- a/arch/arm/mach-socfpga/include/mach/debug_ll.h +++ b/arch/arm/mach-socfpga/include/mach/debug_ll.h @@ -40,8 +40,6 @@ static inline void INIT_LL(void) unsigned int div = ns16550_calc_divisor(CONFIG_DEBUG_SOCFPGA_UART_CLOCK, 115200); - while ((readl(UART_BASE + LSR) & LSR_TEMT) == 0); - writel(0x00, UART_BASE + IER); writel(LCR_BKSE, UART_BASE + LCR); |