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authorSteffen Trumtrar <s.trumtrar@pengutronix.de>2015-01-12 10:48:39 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2015-01-13 08:42:16 +0100
commit243ef1835b7e0305f73cbf20c7988f0040704885 (patch)
treed0cd82fb75b5da89ba6deca58fc64a940d7b5c67 /arch/arm/mach-socfpga/include/mach
parent27f362a57d7fedf428a9502ef83ff3a8d80da38b (diff)
downloadbarebox-243ef1835b7e0305f73cbf20c7988f0040704885.tar.gz
ARM: socfpga: clkmgr: set alteragrp clocks
Altera's U-Boot tree has following commit FogBugz #159721: Enhance Arria V MPU clock to 1050MHz It writes to the two undocumented registers CLKMGR_ALTERAGRP_MPUCLK and CLKMGR_ALTERAGRP_MAINCLK to setup the SoC for higher clocks. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-socfpga/include/mach')
-rw-r--r--arch/arm/mach-socfpga/include/mach/clock-manager.h6
-rw-r--r--arch/arm/mach-socfpga/include/mach/pll_config.h3
2 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/clock-manager.h b/arch/arm/mach-socfpga/include/mach/clock-manager.h
index b67f256..649cf96 100644
--- a/arch/arm/mach-socfpga/include/mach/clock-manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock-manager.h
@@ -50,6 +50,10 @@ struct socfpga_cm_config {
uint32_t ddr2xdqsclk;
uint32_t ddrdqclk;
uint32_t s2fuser2clk;
+
+ /* altera group */
+ uint32_t alteragrp_mpu;
+ uint32_t alteregrp_main;
};
void socfpga_cm_basic_init(const struct socfpga_cm_config *cfg);
@@ -95,6 +99,8 @@ void socfpga_cm_basic_init(const struct socfpga_cm_config *cfg);
#define CLKMGR_SDRPLLGRP_DDRDQCLK_ADDRESS 0xd0
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_ADDRESS 0xd4
#define CLKMGR_SDRPLLGRP_EN_ADDRESS 0xd8
+#define CLKMGR_ALTERAGRP_MPUCLK 0xe0
+#define CLKMGR_ALTERAGRP_MAINCLK 0xe4
#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
diff --git a/arch/arm/mach-socfpga/include/mach/pll_config.h b/arch/arm/mach-socfpga/include/mach/pll_config.h
index d25f5cf..bb491d8 100644
--- a/arch/arm/mach-socfpga/include/mach/pll_config.h
+++ b/arch/arm/mach-socfpga/include/mach/pll_config.h
@@ -50,4 +50,7 @@ static struct socfpga_cm_config cm_default_cfg = {
CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
.s2fuser2clk = CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
+ /* undocumented alteragrp */
+ .alteragrp_mpu = CONFIG_HPS_ALTERAGRP_MPUCLK,
+ .alteregrp_main = CONFIG_HPS_ALTERAGRP_MAINCLK,
};