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authorSascha Hauer <s.hauer@pengutronix.de>2017-05-05 11:31:44 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2017-05-05 11:31:44 +0200
commit5485383d60cd62f1306c5ba6b781e684ba5c2ec3 (patch)
treea10523f97dbbfccb1b4a45e55a915831157394d9 /arch/arm/mach-socfpga/include/mach
parent8e91536a000c1738e354827d6f72965fa1444985 (diff)
parent243530107ad99daa9456e8843efef25326d2a613 (diff)
downloadbarebox-5485383d60cd62f1306c5ba6b781e684ba5c2ec3.tar.gz
Merge branch 'for-next/socfpga'
Diffstat (limited to 'arch/arm/mach-socfpga/include/mach')
-rw-r--r--arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h249
-rw-r--r--arch/arm/mach-socfpga/include/mach/arria10-pinmux.h250
-rw-r--r--arch/arm/mach-socfpga/include/mach/arria10-regs.h114
-rw-r--r--arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h114
-rw-r--r--arch/arm/mach-socfpga/include/mach/arria10-sdram.h353
-rw-r--r--arch/arm/mach-socfpga/include/mach/arria10-system-manager.h97
-rw-r--r--arch/arm/mach-socfpga/include/mach/barebox-arm-head.h42
-rw-r--r--arch/arm/mach-socfpga/include/mach/cyclone5-clock-manager.h (renamed from arch/arm/mach-socfpga/include/mach/clock-manager.h)6
-rw-r--r--arch/arm/mach-socfpga/include/mach/cyclone5-freeze-controller.h (renamed from arch/arm/mach-socfpga/include/mach/freeze-controller.h)6
-rw-r--r--arch/arm/mach-socfpga/include/mach/cyclone5-regs.h (renamed from arch/arm/mach-socfpga/include/mach/socfpga-regs.h)0
-rw-r--r--arch/arm/mach-socfpga/include/mach/cyclone5-reset-manager.h (renamed from arch/arm/mach-socfpga/include/mach/reset-manager.h)0
-rw-r--r--arch/arm/mach-socfpga/include/mach/cyclone5-scan-manager.h (renamed from arch/arm/mach-socfpga/include/mach/scan-manager.h)2
-rw-r--r--arch/arm/mach-socfpga/include/mach/cyclone5-sdram-config.h (renamed from arch/arm/mach-socfpga/include/mach/sdram_config.h)6
-rw-r--r--arch/arm/mach-socfpga/include/mach/cyclone5-sdram.h (renamed from arch/arm/mach-socfpga/include/mach/sdram.h)0
-rw-r--r--arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c (renamed from arch/arm/mach-socfpga/include/mach/sequencer.c)6
-rw-r--r--arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.h (renamed from arch/arm/mach-socfpga/include/mach/sequencer.h)0
-rw-r--r--arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h (renamed from arch/arm/mach-socfpga/include/mach/system-manager.h)0
-rw-r--r--arch/arm/mach-socfpga/include/mach/debug_ll.h81
-rw-r--r--arch/arm/mach-socfpga/include/mach/generic.h36
-rw-r--r--arch/arm/mach-socfpga/include/mach/pll_config.h2
-rw-r--r--[-rwxr-xr-x]arch/arm/mach-socfpga/include/mach/sdram_io.h2
-rw-r--r--arch/arm/mach-socfpga/include/mach/sequencer_defines.h6
-rw-r--r--[-rwxr-xr-x]arch/arm/mach-socfpga/include/mach/system.h0
-rw-r--r--[-rwxr-xr-x]arch/arm/mach-socfpga/include/mach/tclrpt.h2
24 files changed, 1326 insertions, 48 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h b/arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h
new file mode 100644
index 0000000..ee2b9b3
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h
@@ -0,0 +1,249 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ARRIA10_CLOCK_MANAGER_H_
+#define _ARRIA10_CLOCK_MANAGER_H_
+
+struct arria10_clock_manager {
+ /* clkmgr */
+ volatile uint32_t ctrl;
+ volatile uint32_t intr;
+ volatile uint32_t intrs;
+ volatile uint32_t intrr;
+ volatile uint32_t intren;
+ volatile uint32_t intrens;
+ volatile uint32_t intrenr;
+ volatile uint32_t stat;
+ volatile uint32_t testioctrl;
+ volatile uint32_t _pad_0x24_0x40[7];
+
+ /* mainpllgrp*/
+ volatile uint32_t main_pll_vco0;
+ volatile uint32_t main_pll_vco1;
+ volatile uint32_t main_pll_en;
+ volatile uint32_t main_pll_ens;
+ volatile uint32_t main_pll_enr;
+ volatile uint32_t main_pll_bypass;
+ volatile uint32_t main_pll_bypasss;
+ volatile uint32_t main_pll_bypassr;
+ volatile uint32_t main_pll_mpuclk;
+ volatile uint32_t main_pll_nocclk;
+ volatile uint32_t main_pll_cntr2clk;
+ volatile uint32_t main_pll_cntr3clk;
+ volatile uint32_t main_pll_cntr4clk;
+ volatile uint32_t main_pll_cntr5clk;
+ volatile uint32_t main_pll_cntr6clk;
+ volatile uint32_t main_pll_cntr7clk;
+ volatile uint32_t main_pll_cntr8clk;
+ volatile uint32_t main_pll_cntr9clk;
+ volatile uint32_t main_pll__pad_0x48_0x5b[5];
+ volatile uint32_t main_pll_cntr15clk;
+ volatile uint32_t main_pll_outrst;
+ volatile uint32_t main_pll_outrststat;
+ volatile uint32_t main_pll_nocdiv;
+ volatile uint32_t main_pll__pad_0x6c_0x80[5];
+
+ /* perpllgrp*/
+ volatile uint32_t per_pll_vco0;
+ volatile uint32_t per_pll_vco1;
+ volatile uint32_t per_pll_en;
+ volatile uint32_t per_pll_ens;
+ volatile uint32_t per_pll_enr;
+ volatile uint32_t per_pll_bypass;
+ volatile uint32_t per_pll_bypasss;
+ volatile uint32_t per_pll_bypassr;
+ volatile uint32_t per_pll__pad_0x20_0x27[2];
+ volatile uint32_t per_pll_cntr2clk;
+ volatile uint32_t per_pll_cntr3clk;
+ volatile uint32_t per_pll_cntr4clk;
+ volatile uint32_t per_pll_cntr5clk;
+ volatile uint32_t per_pll_cntr6clk;
+ volatile uint32_t per_pll_cntr7clk;
+ volatile uint32_t per_pll_cntr8clk;
+ volatile uint32_t per_pll_cntr9clk;
+ volatile uint32_t per_pll__pad_0x48_0x5f[6];
+ volatile uint32_t per_pll_outrst;
+ volatile uint32_t per_pll_outrststat;
+ volatile uint32_t per_pll_emacctl;
+ volatile uint32_t per_pll_gpiodiv;
+ volatile uint32_t per_pll__pad_0x70_0x80[4];
+};
+
+struct arria10_mainpll_cfg {
+ uint32_t vco0_psrc;
+ uint32_t vco1_denom;
+ uint32_t vco1_numer;
+ uint32_t mpuclk;
+ uint32_t mpuclk_cnt;
+ uint32_t mpuclk_src;
+ uint32_t nocclk;
+ uint32_t nocclk_cnt;
+ uint32_t nocclk_src;
+ uint32_t cntr2clk_cnt;
+ uint32_t cntr3clk_cnt;
+ uint32_t cntr4clk_cnt;
+ uint32_t cntr5clk_cnt;
+ uint32_t cntr6clk_cnt;
+ uint32_t cntr7clk_cnt;
+ uint32_t cntr7clk_src;
+ uint32_t cntr8clk_cnt;
+ uint32_t cntr9clk_cnt;
+ uint32_t cntr9clk_src;
+ uint32_t cntr15clk_cnt;
+ uint32_t nocdiv_l4mainclk;
+ uint32_t nocdiv_l4mpclk;
+ uint32_t nocdiv_l4spclk;
+ uint32_t nocdiv_csatclk;
+ uint32_t nocdiv_cstraceclk;
+ uint32_t nocdiv_cspdbgclk;
+};
+
+struct arria10_perpll_cfg {
+ uint32_t vco0_psrc;
+ uint32_t vco1_denom;
+ uint32_t vco1_numer;
+ uint32_t cntr2clk_cnt;
+ uint32_t cntr2clk_src;
+ uint32_t cntr3clk_cnt;
+ uint32_t cntr3clk_src;
+ uint32_t cntr4clk_cnt;
+ uint32_t cntr4clk_src;
+ uint32_t cntr5clk_cnt;
+ uint32_t cntr5clk_src;
+ uint32_t cntr6clk_cnt;
+ uint32_t cntr6clk_src;
+ uint32_t cntr7clk_cnt;
+ uint32_t cntr8clk_cnt;
+ uint32_t cntr8clk_src;
+ uint32_t cntr9clk_cnt;
+ uint32_t cntr9clk_src;
+ uint32_t emacctl_emac0sel;
+ uint32_t emacctl_emac1sel;
+ uint32_t emacctl_emac2sel;
+ uint32_t gpiodiv_gpiodbclk;
+};
+
+extern int arria10_cm_basic_init(struct arria10_mainpll_cfg *mainpll_cfg,
+ struct arria10_perpll_cfg *perpll_cfg);
+extern unsigned int cm_get_mmc_controller_clk_hz(void);
+extern void arria10_cm_use_intosc(void);
+extern uint32_t cm_l4_main_clk_hz;
+extern uint32_t cm_l4_sp_clk_hz;
+extern uint32_t cm_l4_mp_clk_hz;
+extern uint32_t cm_l4_sys_free_clk_hz;
+
+#define ARRIA10_CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140
+#define ARRIA10_CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144
+
+/* value */
+#define ARRIA10_CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_RESET 0x00010053
+#define ARRIA10_CLKMGR_MAINPLL_VCO1_RESET 0x00010001
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_EOSC 0x0
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_F2S 0x2
+#define ARRIA10_CLKMGR_PERPLL_BYPASS_RESET 0x000000ff
+#define ARRIA10_CLKMGR_PERPLL_VCO0_RESET 0x00010053
+#define ARRIA10_CLKMGR_PERPLL_VCO1_RESET 0x00010001
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_EOSC 0x0
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC 0x1
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_F2S 0x2
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MAIN 0x3
+
+/* mask */
+#define ARRIA10_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK 0x00000040
+#define ARRIA10_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK 0x00000080
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK 0x00000001
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK 0x00000002
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_EN_SET_MSK 0x00000004
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK 0x00000008
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK 0x00000010
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_MSK 0x00000003
+#define ARRIA10_CLKMGR_MAINPLL_VCO1_NUMER_MSK 0x00001fff
+#define ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_MSK 0x0000003f
+#define ARRIA10_CLKMGR_MAINPLL_CNTRCLK_MSK 0x000003ff
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_CNT_MSK 0x000003ff
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN 0
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI 1
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_OSC1 2
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC 3
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_FPGA 4
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_MSK 0x00000003
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_CNT_MSK 0x000003ff
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MSK 0x00000007
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN 0
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI 1
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_OSC1 2
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC 3
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_FPGA 4
+#define ARRIA10_CLKMGR_CLKMGR_STAT_BUSY_SET_MSK 0x00000001
+#define ARRIA10_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK 0x00000100
+#define ARRIA10_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK 0x00000200
+#define ARRIA10_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK 0x00020000
+#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK 0x00000800
+#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK 0x00000400
+#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK 0x00000200
+#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK 0x00000100
+#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK 0x00000008
+#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK 0x00000004
+#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK 0x00000001
+#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK 0x00000002
+#define ARRIA10_CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK 0x00000001
+#define ARRIA10_CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK 0x00000300
+#define ARRIA10_CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK 0x00000001
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK 0x00000002
+#define ARRIA10_CLKMGR_PERPLL_VCO0_EN_SET_MSK 0x00000004
+#define ARRIA10_CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK 0x00000008
+#define ARRIA10_CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK 0x00000010
+#define ARRIA10_CLKMGR_PERPLL_EN_RESET 0x00000f7f
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MSK 0x00000003
+#define ARRIA10_CLKMGR_PERPLL_VCO1_NUMER_MSK 0x00001fff
+#define ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_MSK 0x0000003f
+#define ARRIA10_CLKMGR_PERPLL_CNTRCLK_MSK 0x000003ff
+
+#define ARRIA10_CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020
+#define ARRIA10_CLKMGR_PERPLLGRP_SRC_MSK 0x00000007
+#define ARRIA10_CLKMGR_PERPLLGRP_SRC_MAIN 0
+#define ARRIA10_CLKMGR_PERPLLGRP_SRC_PERI 1
+#define ARRIA10_CLKMGR_PERPLLGRP_SRC_OSC1 2
+#define ARRIA10_CLKMGR_PERPLLGRP_SRC_INTOSC 3
+#define ARRIA10_CLKMGR_PERPLLGRP_SRC_FPGA 4
+
+/* bit shifting macro */
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_LSB 8
+#define ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB 16
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB 16
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB 0
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB 8
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB 16
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB 24
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB 26
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB 28
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB 16
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB 16
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_LSB 8
+#define ARRIA10_CLKMGR_PERPLL_CNTR2CLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_PERPLL_CNTR3CLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_PERPLL_CNTR4CLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_PERPLL_CNTR5CLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_PERPLL_CNTR6CLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_PERPLL_CNTR8CLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB 26
+#define ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB 27
+#define ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB 28
+
+/* PLL ramping work around */
+#define ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ 900000000
+#define ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ 300000000
+#define ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ 100000000
+#define ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ 33000000
+
+#endif /* _ARRIA10_CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-pinmux.h b/arch/arm/mach-socfpga/include/mach/arria10-pinmux.h
new file mode 100644
index 0000000..979e476
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/arria10-pinmux.h
@@ -0,0 +1,250 @@
+/*
+ * Copyright (C) 2017 Pengutronix, Steffen Trumtrar <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _ARRIA10_PINMUX_H_
+#define _ARRIA10_PINMUX_H_
+
+#include <mach/arria10-regs.h>
+
+#define ARRIA10_PINMUX_SHARED_IO_Q1_1_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x00
+#define ARRIA10_PINMUX_SHARED_IO_Q1_2_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x04
+#define ARRIA10_PINMUX_SHARED_IO_Q1_3_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x08
+#define ARRIA10_PINMUX_SHARED_IO_Q1_4_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x0c
+#define ARRIA10_PINMUX_SHARED_IO_Q1_5_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x10
+#define ARRIA10_PINMUX_SHARED_IO_Q1_6_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x14
+#define ARRIA10_PINMUX_SHARED_IO_Q1_7_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x18
+#define ARRIA10_PINMUX_SHARED_IO_Q1_8_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x1c
+#define ARRIA10_PINMUX_SHARED_IO_Q1_9_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x20
+#define ARRIA10_PINMUX_SHARED_IO_Q1_10_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x24
+#define ARRIA10_PINMUX_SHARED_IO_Q1_11_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x28
+#define ARRIA10_PINMUX_SHARED_IO_Q1_12_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x2c
+#define ARRIA10_PINMUX_SHARED_IO_Q2_1_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x30
+#define ARRIA10_PINMUX_SHARED_IO_Q2_2_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x34
+#define ARRIA10_PINMUX_SHARED_IO_Q2_3_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x38
+#define ARRIA10_PINMUX_SHARED_IO_Q2_4_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x3c
+#define ARRIA10_PINMUX_SHARED_IO_Q2_5_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x40
+#define ARRIA10_PINMUX_SHARED_IO_Q2_6_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x44
+#define ARRIA10_PINMUX_SHARED_IO_Q2_7_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x48
+#define ARRIA10_PINMUX_SHARED_IO_Q2_8_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x4c
+#define ARRIA10_PINMUX_SHARED_IO_Q2_9_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x50
+#define ARRIA10_PINMUX_SHARED_IO_Q2_10_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x54
+#define ARRIA10_PINMUX_SHARED_IO_Q2_11_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x58
+#define ARRIA10_PINMUX_SHARED_IO_Q2_12_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x5c
+#define ARRIA10_PINMUX_SHARED_IO_Q3_1_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x60
+#define ARRIA10_PINMUX_SHARED_IO_Q3_2_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x64
+#define ARRIA10_PINMUX_SHARED_IO_Q3_3_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x68
+#define ARRIA10_PINMUX_SHARED_IO_Q3_4_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x6c
+#define ARRIA10_PINMUX_SHARED_IO_Q3_5_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x70
+#define ARRIA10_PINMUX_SHARED_IO_Q3_6_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x74
+#define ARRIA10_PINMUX_SHARED_IO_Q3_7_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x78
+#define ARRIA10_PINMUX_SHARED_IO_Q3_8_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x7c
+#define ARRIA10_PINMUX_SHARED_IO_Q3_9_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x80
+#define ARRIA10_PINMUX_SHARED_IO_Q3_10_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x84
+#define ARRIA10_PINMUX_SHARED_IO_Q3_11_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x88
+#define ARRIA10_PINMUX_SHARED_IO_Q3_12_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x8c
+#define ARRIA10_PINMUX_SHARED_IO_Q4_1_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x90
+#define ARRIA10_PINMUX_SHARED_IO_Q4_2_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x94
+#define ARRIA10_PINMUX_SHARED_IO_Q4_3_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x98
+#define ARRIA10_PINMUX_SHARED_IO_Q4_4_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x9c
+#define ARRIA10_PINMUX_SHARED_IO_Q4_5_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xa0
+#define ARRIA10_PINMUX_SHARED_IO_Q4_6_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xa4
+#define ARRIA10_PINMUX_SHARED_IO_Q4_7_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xa8
+#define ARRIA10_PINMUX_SHARED_IO_Q4_8_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xac
+#define ARRIA10_PINMUX_SHARED_IO_Q4_9_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xb0
+#define ARRIA10_PINMUX_SHARED_IO_Q4_10_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xb4
+#define ARRIA10_PINMUX_SHARED_IO_Q4_11_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xb8
+#define ARRIA10_PINMUX_SHARED_IO_Q4_12_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xbc
+
+#define ARRIA10_PINMUX_SHARED_IO_Q1_I2C 0
+#define ARRIA10_PINMUX_SHARED_IO_Q1_EMAC 1
+#define ARRIA10_PINMUX_SHARED_IO_Q1_SPIS 2
+#define ARRIA10_PINMUX_SHARED_IO_Q1_SPIM 3
+#define ARRIA10_PINMUX_SHARED_IO_Q1_SDMMC 4
+#define ARRIA10_PINMUX_SHARED_IO_Q1_USB 8
+#define ARRIA10_PINMUX_SHARED_IO_Q1_QSPI 12
+#define ARRIA10_PINMUX_SHARED_IO_Q1_UART 13
+#define ARRIA10_PINMUX_SHARED_IO_Q1_NAND 14
+#define ARRIA10_PINMUX_SHARED_IO_Q1_GPIO 15
+
+#define ARRIA10_PINMUX_SHARED_IO_Q2_I2C 0
+#define ARRIA10_PINMUX_SHARED_IO_Q2_SPIS 2
+#define ARRIA10_PINMUX_SHARED_IO_Q2_SPIM 3
+#define ARRIA10_PINMUX_SHARED_IO_Q2_EMAC 4
+#define ARRIA10_PINMUX_SHARED_IO_Q2_USB 8
+#define ARRIA10_PINMUX_SHARED_IO_Q2_UART 13
+#define ARRIA10_PINMUX_SHARED_IO_Q2_NAND 14
+#define ARRIA10_PINMUX_SHARED_IO_Q2_GPIO 15
+
+#define ARRIA10_PINMUX_SHARED_IO_Q3_I2C 0
+#define ARRIA10_PINMUX_SHARED_IO_Q3_EMAC0 1
+#define ARRIA10_PINMUX_SHARED_IO_Q3_SPIS 2
+#define ARRIA10_PINMUX_SHARED_IO_Q3_SPIM 3
+#define ARRIA10_PINMUX_SHARED_IO_Q3_EMAC1 8
+#define ARRIA10_PINMUX_SHARED_IO_Q3_UART 13
+#define ARRIA10_PINMUX_SHARED_IO_Q3_NAND 14
+#define ARRIA10_PINMUX_SHARED_IO_Q3_GPIO 15
+
+#define ARRIA10_PINMUX_SHARED_IO_Q4_I2C 0
+#define ARRIA10_PINMUX_SHARED_IO_Q4_EMAC0 1
+#define ARRIA10_PINMUX_SHARED_IO_Q4_SPIS 2
+#define ARRIA10_PINMUX_SHARED_IO_Q4_SPIM 3
+#define ARRIA10_PINMUX_SHARED_IO_Q4_SDMMC 4
+#define ARRIA10_PINMUX_SHARED_IO_Q4_EMAC1 8
+#define ARRIA10_PINMUX_SHARED_IO_Q4_QSPI 12
+#define ARRIA10_PINMUX_SHARED_IO_Q4_UART 13
+#define ARRIA10_PINMUX_SHARED_IO_Q4_NAND 14
+#define ARRIA10_PINMUX_SHARED_IO_Q4_GPIO 15
+
+#define ARRIA10_PINMUX_DEDICATED_IO_1_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x00
+#define ARRIA10_PINMUX_DEDICATED_IO_2_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x04
+#define ARRIA10_PINMUX_DEDICATED_IO_3_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x08
+#define ARRIA10_PINMUX_DEDICATED_IO_4_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x0c
+#define ARRIA10_PINMUX_DEDICATED_IO_5_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x10
+#define ARRIA10_PINMUX_DEDICATED_IO_6_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x14
+#define ARRIA10_PINMUX_DEDICATED_IO_7_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x18
+#define ARRIA10_PINMUX_DEDICATED_IO_8_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x1c
+#define ARRIA10_PINMUX_DEDICATED_IO_9_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x20
+#define ARRIA10_PINMUX_DEDICATED_IO_10_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x24
+#define ARRIA10_PINMUX_DEDICATED_IO_11_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x28
+#define ARRIA10_PINMUX_DEDICATED_IO_12_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x2c
+#define ARRIA10_PINMUX_DEDICATED_IO_13_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x30
+#define ARRIA10_PINMUX_DEDICATED_IO_14_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x34
+#define ARRIA10_PINMUX_DEDICATED_IO_15_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x38
+#define ARRIA10_PINMUX_DEDICATED_IO_16_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x3c
+#define ARRIA10_PINMUX_DEDICATED_IO_17_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x40
+
+#define ARRIA10_PINCFG_DEDICATED_IO_BANK_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x00
+#define ARRIA10_PINCFG_DEDICATED_IO_1_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x04
+#define ARRIA10_PINCFG_DEDICATED_IO_2_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x08
+#define ARRIA10_PINCFG_DEDICATED_IO_3_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x0c
+#define ARRIA10_PINCFG_DEDICATED_IO_4_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x10
+#define ARRIA10_PINCFG_DEDICATED_IO_5_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x14
+#define ARRIA10_PINCFG_DEDICATED_IO_6_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x18
+#define ARRIA10_PINCFG_DEDICATED_IO_7_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x1c
+#define ARRIA10_PINCFG_DEDICATED_IO_8_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x20
+#define ARRIA10_PINCFG_DEDICATED_IO_9_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x24
+#define ARRIA10_PINCFG_DEDICATED_IO_10_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x28
+#define ARRIA10_PINCFG_DEDICATED_IO_11_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x2c
+#define ARRIA10_PINCFG_DEDICATED_IO_12_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x30
+#define ARRIA10_PINCFG_DEDICATED_IO_13_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x34
+#define ARRIA10_PINCFG_DEDICATED_IO_14_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x38
+#define ARRIA10_PINCFG_DEDICATED_IO_15_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x3c
+#define ARRIA10_PINCFG_DEDICATED_IO_16_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x40
+#define ARRIA10_PINCFG_DEDICATED_IO_17_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x44
+
+enum arria10_pinmux_io_addr {
+ arria10_pinmux_shared_io_q1_1,
+ arria10_pinmux_shared_io_q1_2,
+ arria10_pinmux_shared_io_q1_3,
+ arria10_pinmux_shared_io_q1_4,
+ arria10_pinmux_shared_io_q1_5,
+ arria10_pinmux_shared_io_q1_6,
+ arria10_pinmux_shared_io_q1_7,
+ arria10_pinmux_shared_io_q1_8,
+ arria10_pinmux_shared_io_q1_9,
+ arria10_pinmux_shared_io_q1_10,
+ arria10_pinmux_shared_io_q1_11,
+ arria10_pinmux_shared_io_q1_12,
+ arria10_pinmux_shared_io_q2_1,
+ arria10_pinmux_shared_io_q2_2,
+ arria10_pinmux_shared_io_q2_3,
+ arria10_pinmux_shared_io_q2_4,
+ arria10_pinmux_shared_io_q2_5,
+ arria10_pinmux_shared_io_q2_6,
+ arria10_pinmux_shared_io_q2_7,
+ arria10_pinmux_shared_io_q2_8,
+ arria10_pinmux_shared_io_q2_9,
+ arria10_pinmux_shared_io_q2_10,
+ arria10_pinmux_shared_io_q2_11,
+ arria10_pinmux_shared_io_q2_12,
+ arria10_pinmux_shared_io_q3_1,
+ arria10_pinmux_shared_io_q3_2,
+ arria10_pinmux_shared_io_q3_3,
+ arria10_pinmux_shared_io_q3_4,
+ arria10_pinmux_shared_io_q3_5,
+ arria10_pinmux_shared_io_q3_6,
+ arria10_pinmux_shared_io_q3_7,
+ arria10_pinmux_shared_io_q3_8,
+ arria10_pinmux_shared_io_q3_9,
+ arria10_pinmux_shared_io_q3_10,
+ arria10_pinmux_shared_io_q3_11,
+ arria10_pinmux_shared_io_q3_12,
+ arria10_pinmux_shared_io_q4_1,
+ arria10_pinmux_shared_io_q4_2,
+ arria10_pinmux_shared_io_q4_3,
+ arria10_pinmux_shared_io_q4_4,
+ arria10_pinmux_shared_io_q4_5,
+ arria10_pinmux_shared_io_q4_6,
+ arria10_pinmux_shared_io_q4_7,
+ arria10_pinmux_shared_io_q4_8,
+ arria10_pinmux_shared_io_q4_9,
+ arria10_pinmux_shared_io_q4_10,
+ arria10_pinmux_shared_io_q4_11,
+ arria10_pinmux_shared_io_q4_12,
+ arria10_pinmux_dedicated_io_1,
+ arria10_pinmux_dedicated_io_2,
+ arria10_pinmux_dedicated_io_3,
+ arria10_pinmux_dedicated_io_4,
+ arria10_pinmux_dedicated_io_5,
+ arria10_pinmux_dedicated_io_6,
+ arria10_pinmux_dedicated_io_7,
+ arria10_pinmux_dedicated_io_8,
+ arria10_pinmux_dedicated_io_9,
+ arria10_pinmux_dedicated_io_10,
+ arria10_pinmux_dedicated_io_11,
+ arria10_pinmux_dedicated_io_12,
+ arria10_pinmux_dedicated_io_13,
+ arria10_pinmux_dedicated_io_14,
+ arria10_pinmux_dedicated_io_15,
+ arria10_pinmux_dedicated_io_16,
+ arria10_pinmux_dedicated_io_17,
+ arria10_pincfg_dedicated_io_bank,
+ arria10_pincfg_dedicated_io_1,
+ arria10_pincfg_dedicated_io_2,
+ arria10_pincfg_dedicated_io_3,
+ arria10_pincfg_dedicated_io_4,
+ arria10_pincfg_dedicated_io_5,
+ arria10_pincfg_dedicated_io_6,
+ arria10_pincfg_dedicated_io_7,
+ arria10_pincfg_dedicated_io_8,
+ arria10_pincfg_dedicated_io_9,
+ arria10_pincfg_dedicated_io_10,
+ arria10_pincfg_dedicated_io_11,
+ arria10_pincfg_dedicated_io_12,
+ arria10_pincfg_dedicated_io_13,
+ arria10_pincfg_dedicated_io_14,
+ arria10_pincfg_dedicated_io_15,
+ arria10_pincfg_dedicated_io_16,
+ arria10_pincfg_dedicated_io_17,
+ arria10_pinmux_rgmii0_usefpga,
+ arria10_pinmux_rgmii1_usefpga,
+ arria10_pinmux_rgmii2_usefpga,
+ arria10_pinmux_i2c0_usefpga,
+ arria10_pinmux_i2c1_usefpga,
+ arria10_pinmux_i2cemac0_usefpga,
+ arria10_pinmux_i2cemac1_usefpga,
+ arria10_pinmux_i2cemac2_usefpga,
+ arria10_pinmux_nand_usefpga,
+ arria10_pinmux_qspi_usefpga,
+ arria10_pinmux_sdmmc_usefpga,
+ arria10_pinmux_spim0_usefpga,
+ arria10_pinmux_spim1_usefpga,
+ arria10_pinmux_spis0_usefpga,
+ arria10_pinmux_spis1_usefpga,
+ arria10_pinmux_uart0_usefpga,
+ arria10_pinmux_uart1_usefpga,
+ arria10_pinmux_max
+};
+#endif
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-regs.h b/arch/arm/mach-socfpga/include/mach/arria10-regs.h
new file mode 100644
index 0000000..5569574
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/arria10-regs.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ARRIA10_HARDWARE_H_
+#define _ARRIA10_HARDWARE_H_
+
+#define ARRIA10_EMAC0_ADDR (0xff800000)
+#define ARRIA10_EMAC1_ADDR (0xff802000)
+#define ARRIA10_EMAC2_ADDR (0xff804000)
+#define ARRIA10_SDMMC_ADDR (0xff808000)
+#define ARRIA10_QSPIREGS_ADDR (0xff809000)
+#define ARRIA10_ECC_OCRAM_ADDR (0xff8c3000)
+#define ARRIA10_QSPIDATA_ADDR (0xffa00000)
+#define ARRIA10_UART0_ADDR (0xffc02000)
+#define ARRIA10_UART1_ADDR (0xffc02100)
+#define ARRIA10_I2C0_ADDR (0xffc02200)
+#define ARRIA10_I2C1_ADDR (0xffc02300)
+#define ARRIA10_GPIO0_ADDR (0xffc02900)
+#define ARRIA10_GPIO1_ADDR (0xffc02a00)
+#define ARRIA10_GPIO2_ADDR (0xffc02b00)
+#define ARRIA10_HMC_MMR_IO48_ADDR (0xffcfa000)
+#define ARRIA10_SDR_ADDR (0xffcfb000)
+#define ARRIA10_FPGAMGRDATA_ADDR (0xffcfe400)
+#define ARRIA10_OSC1TIMER0_ADDR (0xffd00000)
+#define ARRIA10_L4WD0_ADDR (0xffd00200)
+#define ARRIA10_FPGAMGRREGS_ADDR (0xffd03000)
+#define ARRIA10_CLKMGR_ADDR (0xffd04000)
+#define ARRIA10_RSTMGR_ADDR (0xffd05000)
+#define ARRIA10_SYSMGR_ADDR (0xffd06000)
+#define ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR (0xffd07000)
+#define ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR (0xffd07200)
+#define ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR (0xffd07300)
+#define ARRIA10_PINMUX_FPGA_INTERFACE_ADDR (0xffd07400)
+#define ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR (0xffd11000)
+#define ARRIA10_SDR_SCHEDULER_ADDR (0xffd12400)
+#define ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR (0xffd13000)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR (0xffd13200)
+#define ARRIA10_SDR_FW_MPU_FPGA_ADDR (0xffd13300)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR (0xffd13400)
+#define ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_ADDR (0xffd13500)
+#define ARRIA10_DMANONSECURE_ADDR (0xffda0000)
+#define ARRIA10_DMASECURE_ADDR (0xffda1000)
+#define ARRIA10_MPUSCU_ADDR (0xffffc000)
+#define ARRIA10_MPUL2_ADDR (0xfffff000)
+
+/* L2 cache controller */
+#define ARRIA10_MPUL2_ADRFLTR_START (ARRIA10_MPUL2_ADDR + 0xC00)
+
+/* NOC L4 Priv */
+#define ARRIA10_NOC_L4_PRIV_L4_PRIV_L4_PRIV (ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR + 0x00)
+#define ARRIA10_NOC_L4_PRIV_L4_PRIV_L4_PRIV_SET (ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR + 0x04)
+#define ARRIA10_NOC_L4_PRIV_L4_PRIV_L4_PRIV_CLR (ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR + 0x08)
+
+/* NOC L4 Permissions */
+#define ARRIA10_NOC_FW_L4_PER_SCR_NAND_REG (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x00)
+#define ARRIA10_NOC_FW_L4_PER_SCR_NAND_DATA (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x04)
+#define ARRIA10_NOC_FW_L4_PER_SCR_QSPI_DATA (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x08)
+#define ARRIA10_NOC_FW_L4_PER_SCR_USB0_REG (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x0c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_USB1_REG (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x10)
+#define ARRIA10_NOC_FW_L4_PER_SCR_DMA_NONSECURE (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x14)
+#define ARRIA10_NOC_FW_L4_PER_SCR_DMA_SECURE (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x18)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SPIM0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x1c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SPIM1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x20)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SPIS0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x24)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SPIS1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x28)
+#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x2c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x30)
+#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC2 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x34)
+#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC3 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x38)
+#define ARRIA10_NOC_FW_L4_PER_SCR_QSPI (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x3c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SDMMC (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x40)
+#define ARRIA10_NOC_FW_L4_PER_SCR_GPIO0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x44)
+#define ARRIA10_NOC_FW_L4_PER_SCR_GPIO1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x48)
+#define ARRIA10_NOC_FW_L4_PER_SCR_GPIO2 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x4c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_I2C0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x50)
+#define ARRIA10_NOC_FW_L4_PER_SCR_I2C1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x54)
+#define ARRIA10_NOC_FW_L4_PER_SCR_I2C2 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x58)
+#define ARRIA10_NOC_FW_L4_PER_SCR_I2C3 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x5c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_I2C4 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x60)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SPTIMER0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x64)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SPTIMER1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x68)
+#define ARRIA10_NOC_FW_L4_PER_SCR_UART0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x6c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_UART1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x70)
+
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x00)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN_SET (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x04)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN_CLR (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x08)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION0 (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x0c)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION1 (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x10)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION2 (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x14)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION3 (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x18)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION4 (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x1c)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION5 (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x20)
+
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_EN (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x00)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_EN_SET (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x04)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_EN_CLR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x08)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION0 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x0c)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION1 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x10)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION2 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x14)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION3 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x18)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION4 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x1c)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION5 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x20)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION6 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x24)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION7 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x28)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_GLOBAL (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x2c)
+
+#define ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_LWSOC2FPGA (ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_ADDR + 0x00)
+#define ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_SOC2FPGA (ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_ADDR + 0x04)
+
+#endif
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h b/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h
new file mode 100644
index 0000000..ebd2043
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ARRIA10_RESET_MANAGER_H_
+#define _ARRIA10_RESET_MANAGER_H_
+
+#define ARRIA10_RSTMGR_STATUS 0x0
+#define ARRIA10_RSTMGR_RAMSTAT 0x4
+#define ARRIA10_RSTMGR_MISCSTAT 0x8
+#define ARRIA10_RSTMGR_CTRL 0xc
+#define ARRIA10_RSTMGR_HDSKEN 0x10
+#define ARRIA10_RSTMGR_HDSKREQ 0x14
+#define ARRIA10_RSTMGR_HDSKACK 0x18
+#define ARRIA10_RSTMGR_COUNTS 0x1c
+#define ARRIA10_RSTMGR_MPUMODRST 0x20
+#define ARRIA10_RSTMGR_PER0MODRST 0x24
+#define ARRIA10_RSTMGR_PER1MODRST 0x28
+#define ARRIA10_RSTMGR_BRGMODRST 0x2c
+#define ARRIA10_RSTMGR_SYSMODRST 0x30
+#define ARRIA10_RSTMGR_COLDMODRST 0x34
+#define ARRIA10_RSTMGR_NRSTMODRST 0x38
+#define ARRIA10_RSTMGR_DBGMODRST 0x3c
+#define ARRIA10_RSTMGR_MPUWARMMASK 0x40
+#define ARRIA10_RSTMGR_PER0WARMMASK 0x44
+#define ARRIA10_RSTMGR_PER1WARMMASK 0x48
+#define ARRIA10_RSTMGR_BRGWARMMASK 0x4c
+#define ARRIA10_RSTMGR_SYSWARMMASK 0x50
+#define ARRIA10_RSTMGR_NRSTWARMMASK 0x54
+#define ARRIA10_RSTMGR_L3WARMMASK 0x58
+#define ARRIA10_RSTMGR_TSTSTA 0x5c
+#define ARRIA10_RSTMGR_TSTSCRATCH 0x60
+#define ARRIA10_RSTMGR_HDSKTIMEOUT 0x64
+#define ARRIA10_RSTMGR_HMCINTR 0x68
+#define ARRIA10_RSTMGR_HMCINTREN 0x6c
+#define ARRIA10_RSTMGR_HMCINTRENS 0x70
+#define ARRIA10_RSTMGR_HMCINTRENR 0x74
+#define ARRIA10_RSTMGR_HMCGPOUT 0x78
+#define ARRIA10_RSTMGR_HMCGPIN 0x7c
+
+#define ARRIA10_RSTMGR_CTL_SWWARMRSTREQ BIT(1)
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC0 BIT(0)
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC1 BIT(1)
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC2 BIT(2)
+#define ARRIA10_RSTMGR_PER0MODRST_USB0 BIT(3)
+#define ARRIA10_RSTMGR_PER0MODRST_USB1 BIT(4)
+#define ARRIA10_RSTMGR_PER0MODRST_NAND BIT(5)
+#define ARRIA10_RSTMGR_PER0MODRST_QSPI BIT(6)
+#define ARRIA10_RSTMGR_PER0MODRST_SDMMC BIT(7)
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP BIT(8)
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP BIT(9)
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP BIT(10)
+#define ARRIA10_RSTMGR_PER0MODRST_USB0OCP BIT(11)
+#define ARRIA10_RSTMGR_PER0MODRST_USB1OCP BIT(12)
+#define ARRIA10_RSTMGR_PER0MODRST_NANDOCP BIT(13)
+#define ARRIA10_RSTMGR_PER0MODRST_QSPIOCP BIT(14)
+#define ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP BIT(15)
+#define ARRIA10_RSTMGR_PER0MODRST_DMA BIT(16)
+#define ARRIA10_RSTMGR_PER0MODRST_SPIM0 BIT(17)
+#define ARRIA10_RSTMGR_PER0MODRST_SPIM1 BIT(18)
+#define ARRIA10_RSTMGR_PER0MODRST_SPIS0 BIT(19)
+#define ARRIA10_RSTMGR_PER0MODRST_SPIS1 BIT(20)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAOCP BIT(21)
+#define ARRIA10_RSTMGR_PER0MODRST_EMACPTP BIT(22)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF0 BIT(24)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF1 BIT(25)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF2 BIT(26)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF3 BIT(27)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF4 BIT(28)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF5 BIT(29)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF6 BIT(30)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF7 BIT(31)
+
+#define ARRIA10_RSTMGR_PER1MODRST_WATCHDOG0 BIT(0)
+#define ARRIA10_RSTMGR_PER1MODRST_WATCHDOG1 BIT(1)
+#define ARRIA10_RSTMGR_PER1MODRST_L4SYSTIMER0 BIT(2)
+#define ARRIA10_RSTMGR_PER1MODRST_L4SYSTIMER1 BIT(3)
+#define ARRIA10_RSTMGR_PER1MODRST_SPTIMER0 BIT(4)
+#define ARRIA10_RSTMGR_PER1MODRST_SPTIMER1 BIT(5)
+#define ARRIA10_RSTMGR_PER1MODRST_I2C0 BIT(8)
+#define ARRIA10_RSTMGR_PER1MODRST_I2C1 BIT(9)
+#define ARRIA10_RSTMGR_PER1MODRST_I2C2 BIT(10)
+#define ARRIA10_RSTMGR_PER1MODRST_I2C3 BIT(11)
+#define ARRIA10_RSTMGR_PER1MODRST_I2C4 BIT(12)
+#define ARRIA10_RSTMGR_PER1MODRST_UART0 BIT(16)
+#define ARRIA10_RSTMGR_PER1MODRST_UART1 BIT(17)
+#define ARRIA10_RSTMGR_PER1MODRST_GPIO0 BIT(24)
+#define ARRIA10_RSTMGR_PER1MODRST_GPIO1 BIT(25)
+#define ARRIA10_RSTMGR_PER1MODRST_GPIO2 BIT(26)
+
+#define ARRIA10_RSTMGR_BRGMODRST_HPS2FPGA BIT(0)
+#define ARRIA10_RSTMGR_BRGMODRST_LWHPS2FPGA BIT(1)
+#define ARRIA10_RSTMGR_BRGMODRST_FPGA2HPS BIT(2)
+#define ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM0 BIT(3)
+#define ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM1 BIT(4)
+#define ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM2 BIT(5)
+#define ARRIA10_RSTMGR_BRGMODRST_DDRSCH BIT(6)
+
+#define ARRIA10_RSTMGR_OCP_MASK (ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP | \
+ ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP | \
+ ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP | \
+ ARRIA10_RSTMGR_PER0MODRST_NANDOCP | \
+ ARRIA10_RSTMGR_PER0MODRST_QSPIOCP | \
+ ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP)
+
+void arria10_reset_peripherals(void);
+void arria10_reset_deassert_dedicated_peripherals(void);
+void arria10_reset_deassert_shared_peripherals(void);
+void arria10_reset_deassert_fpga_peripherals(void);
+
+#endif
+
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-sdram.h b/arch/arm/mach-socfpga/include/mach/arria10-sdram.h
new file mode 100644
index 0000000..07e4dd0
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/arria10-sdram.h
@@ -0,0 +1,353 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <mach/arria10-system-manager.h>
+
+#ifndef _ARRIA10_SDRAM_H_
+#define _ARRIA10_SDRAM_H_
+
+#define ARRIA10_ECC_HMC_OCP_IP_REV_ID (ARRIA10_SDR_ADDR + 0x00)
+#define ARRIA10_ECC_HMC_OCP_DDRIOCTRL (ARRIA10_SDR_ADDR + 0x08)
+#define ARRIA10_ECC_HMC_OCP_DDRCALSTAT (ARRIA10_SDR_ADDR + 0x0c)
+#define ARRIA10_ECC_HMC_OCP_MPR_OBEAT1 (ARRIA10_SDR_ADDR + 0x10)
+#define ARRIA10_ECC_HMC_OCP_MPR_1BEAT1 (ARRIA10_SDR_ADDR + 0x14)
+#define ARRIA10_ECC_HMC_OCP_MPR_2BEAT1 (ARRIA10_SDR_ADDR + 0x18)
+#define ARRIA10_ECC_HMC_OCP_MPR_3BEAT1 (ARRIA10_SDR_ADDR + 0x1c)
+#define ARRIA10_ECC_HMC_OCP_MPR_4BEAT1 (ARRIA10_SDR_ADDR + 0x20)
+#define ARRIA10_ECC_HMC_OCP_MPR_5BEAT1 (ARRIA10_SDR_ADDR + 0x24)
+#define ARRIA10_ECC_HMC_OCP_MPR_6BEAT1 (ARRIA10_SDR_ADDR + 0x28)
+#define ARRIA10_ECC_HMC_OCP_MPR_7BEAT1 (ARRIA10_SDR_ADDR + 0x2c)
+#define ARRIA10_ECC_HMC_OCP_MPR_8BEAT1 (ARRIA10_SDR_ADDR + 0x30)
+#define ARRIA10_ECC_HMC_OCP_MPR_OBEAT2 (ARRIA10_SDR_ADDR + 0x34)
+#define ARRIA10_ECC_HMC_OCP_MPR_1BEAT2 (ARRIA10_SDR_ADDR + 0x38)
+#define ARRIA10_ECC_HMC_OCP_MPR_2BEAT2 (ARRIA10_SDR_ADDR + 0x3c)
+#define ARRIA10_ECC_HMC_OCP_MPR_3BEAT2 (ARRIA10_SDR_ADDR + 0x40)
+#define ARRIA10_ECC_HMC_OCP_MPR_4BEAT2 (ARRIA10_SDR_ADDR + 0x44)
+#define ARRIA10_ECC_HMC_OCP_MPR_5BEAT2 (ARRIA10_SDR_ADDR + 0x48)
+#define ARRIA10_ECC_HMC_OCP_MPR_6BEAT2 (ARRIA10_SDR_ADDR + 0x4c)
+#define ARRIA10_ECC_HMC_OCP_MPR_7BEAT2 (ARRIA10_SDR_ADDR + 0x50)
+#define ARRIA10_ECC_HMC_OCP_MPR_8BEAT2 (ARRIA10_SDR_ADDR + 0x54)
+#define ARRIA10_ECC_HMC_OCP_MPR_AUTO_PRECHARGE (ARRIA10_SDR_ADDR + 0x60)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL1 (ARRIA10_SDR_ADDR + 0x100)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL2 (ARRIA10_SDR_ADDR + 0x104)
+#define ARRIA10_ECC_HMC_OCP_MPR_ERRINTEN (ARRIA10_SDR_ADDR + 0x110)
+#define ARRIA10_ECC_HMC_OCP_MPR_ERRINTENS (ARRIA10_SDR_ADDR + 0x114)
+#define ARRIA10_ECC_HMC_OCP_MPR_ERRINTENR (ARRIA10_SDR_ADDR + 0x118)
+#define ARRIA10_ECC_HMC_OCP_MPR_INTMODE (ARRIA10_SDR_ADDR + 0x11c)
+#define ARRIA10_ECC_HMC_OCP_MPR_INTSTAT (ARRIA10_SDR_ADDR + 0x120)
+#define ARRIA10_ECC_HMC_OCP_MPR_DIAGINTTEST (ARRIA10_SDR_ADDR + 0x124)
+#define ARRIA10_ECC_HMC_OCP_MPR_MODSTAT (ARRIA10_SDR_ADDR + 0x128)
+#define ARRIA10_ECC_HMC_OCP_MPR_DERRADDRA (ARRIA10_SDR_ADDR + 0x12c)
+#define ARRIA10_ECC_HMC_OCP_MPR_SERRADDRA (ARRIA10_SDR_ADDR + 0x130)
+#define ARRIA10_ECC_HMC_OCP_MPR_AUTOWB_CORRADDR (ARRIA10_SDR_ADDR + 0x138)
+#define ARRIA10_ECC_HMC_OCP_MPR_SERRCNTREG (ARRIA10_SDR_ADDR + 0x13c)
+#define ARRIA10_ECC_HMC_OCP_MPR_AUTOWB_DROP_CNTREG (ARRIA10_SDR_ADDR + 0x140)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2WRECCDATABUS (ARRIA10_SDR_ADDR + 0x144)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_RDECCDATA2REGBUS (ARRIA10_SDR_ADDR + 0x148)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDECCDATABUS (ARRIA10_SDR_ADDR + 0x14c)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_DIAGON (ARRIA10_SDR_ADDR + 0x150)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_DECSTAT (ARRIA10_SDR_ADDR + 0x154)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_0 (ARRIA10_SDR_ADDR + 0x160)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_1 (ARRIA10_SDR_ADDR + 0x164)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_2 (ARRIA10_SDR_ADDR + 0x168)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_3 (ARRIA10_SDR_ADDR + 0x16c)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT0 (ARRIA10_SDR_ADDR + 0x170)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT1 (ARRIA10_SDR_ADDR + 0x174)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT2 (ARRIA10_SDR_ADDR + 0x178)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT3 (ARRIA10_SDR_ADDR + 0x17c)
+
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_ID_COREID (ARRIA10_SDR_SCHEDULER_ADDR + 0x00)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_ID_REVISIONID (ARRIA10_SDR_SCHEDULER_ADDR + 0x04)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRCONF (ARRIA10_SDR_SCHEDULER_ADDR + 0x08)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRTIMING (ARRIA10_SDR_SCHEDULER_ADDR + 0x0c)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRMODE (ARRIA10_SDR_SCHEDULER_ADDR + 0x10)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_READLATENCY (ARRIA10_SDR_SCHEDULER_ADDR + 0x14)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_ACTIVATE (ARRIA10_SDR_SCHEDULER_ADDR + 0x38)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DEVTODEV (ARRIA10_SDR_SCHEDULER_ADDR + 0x3c)
+
+#define ARRIA10_IO48_HMC_MMR_DBGCFG0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x00)
+#define ARRIA10_IO48_HMC_MMR_DBGCFG1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x04)
+#define ARRIA10_IO48_HMC_MMR_DBGCFG2 (ARRIA10_HMC_MMR_IO48_ADDR + 0x08)
+#define ARRIA10_IO48_HMC_MMR_DBGCFG3 (ARRIA10_HMC_MMR_IO48_ADDR + 0x0c)
+#define ARRIA10_IO48_HMC_MMR_DBGCFG4 (ARRIA10_HMC_MMR_IO48_ADDR + 0x10)
+#define ARRIA10_IO48_HMC_MMR_DBGCFG5 (ARRIA10_HMC_MMR_IO48_ADDR + 0x14)
+#define ARRIA10_IO48_HMC_MMR_DBGCFG6 (ARRIA10_HMC_MMR_IO48_ADDR + 0x18)
+#define ARRIA10_IO48_HMC_MMR_RESERVE0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x1c)
+#define ARRIA10_IO48_HMC_MMR_RESERVE1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x20)
+#define ARRIA10_IO48_HMC_MMR_RESERVE2 (ARRIA10_HMC_MMR_IO48_ADDR + 0x24)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x28)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x2c)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG2 (ARRIA10_HMC_MMR_IO48_ADDR + 0x30)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG3 (ARRIA10_HMC_MMR_IO48_ADDR + 0x34)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG4 (ARRIA10_HMC_MMR_IO48_ADDR + 0x38)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG5 (ARRIA10_HMC_MMR_IO48_ADDR + 0x3c)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG6 (ARRIA10_HMC_MMR_IO48_ADDR + 0x40)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG7 (ARRIA10_HMC_MMR_IO48_ADDR + 0x44)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG8 (ARRIA10_HMC_MMR_IO48_ADDR + 0x48)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG9 (ARRIA10_HMC_MMR_IO48_ADDR + 0x4c)
+#define ARRIA10_IO48_HMC_MMR_DRAMTIMING0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x50)
+#define ARRIA10_IO48_HMC_MMR_DRAMODT0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x54)
+#define ARRIA10_IO48_HMC_MMR_DRAMODT1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x58)
+#define ARRIA10_IO48_HMC_MMR_SBCFG0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x5c)
+#define ARRIA10_IO48_HMC_MMR_SBCFG1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x60)
+#define ARRIA10_IO48_HMC_MMR_SBCFG2 (ARRIA10_HMC_MMR_IO48_ADDR + 0x64)
+#define ARRIA10_IO48_HMC_MMR_SBCFG3 (ARRIA10_HMC_MMR_IO48_ADDR + 0x68)
+#define ARRIA10_IO48_HMC_MMR_SBCFG4 (ARRIA10_HMC_MMR_IO48_ADDR + 0x6c)
+#define ARRIA10_IO48_HMC_MMR_SBCFG5 (ARRIA10_HMC_MMR_IO48_ADDR + 0x70)
+#define ARRIA10_IO48_HMC_MMR_SBCFG6 (ARRIA10_HMC_MMR_IO48_ADDR + 0x74)
+#define ARRIA10_IO48_HMC_MMR_SBCFG7 (ARRIA10_HMC_MMR_IO48_ADDR + 0x78)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x7c)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x80)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING2 (ARRIA10_HMC_MMR_IO48_ADDR + 0x84)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING3 (ARRIA10_HMC_MMR_IO48_ADDR + 0x88)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING4 (ARRIA10_HMC_MMR_IO48_ADDR + 0x8c)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING5 (ARRIA10_HMC_MMR_IO48_ADDR + 0x90)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING6 (ARRIA10_HMC_MMR_IO48_ADDR + 0x94)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING7 (ARRIA10_HMC_MMR_IO48_ADDR + 0x98)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING8 (ARRIA10_HMC_MMR_IO48_ADDR + 0x9c)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING9 (ARRIA10_HMC_MMR_IO48_ADDR + 0xa0)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING10 (ARRIA10_HMC_MMR_IO48_ADDR + 0xa4)
+#define ARRIA10_IO48_HMC_MMR_DRAMADDRW (ARRIA10_HMC_MMR_IO48_ADDR + 0xa8)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND0 (ARRIA10_HMC_MMR_IO48_ADDR + 0xac)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND1 (ARRIA10_HMC_MMR_IO48_ADDR + 0xb0)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND2 (ARRIA10_HMC_MMR_IO48_ADDR + 0xb4)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND3 (ARRIA10_HMC_MMR_IO48_ADDR + 0xb8)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND4 (ARRIA10_HMC_MMR_IO48_ADDR + 0xbc)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND5 (ARRIA10_HMC_MMR_IO48_ADDR + 0xc0)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND6 (ARRIA10_HMC_MMR_IO48_ADDR + 0xc4)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND7 (ARRIA10_HMC_MMR_IO48_ADDR + 0xc8)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND8 (ARRIA10_HMC_MMR_IO48_ADDR + 0xcc)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND9 (ARRIA10_HMC_MMR_IO48_ADDR + 0xd0)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND10 (ARRIA10_HMC_MMR_IO48_ADDR + 0xd4)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND11 (ARRIA10_HMC_MMR_IO48_ADDR + 0xd8)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND12 (ARRIA10_HMC_MMR_IO48_ADDR + 0xdc)
+#define ARRIA10_IO48_HMC_MMR_SIDEBANB13 (ARRIA10_HMC_MMR_IO48_ADDR + 0xe0)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND14 (ARRIA10_HMC_MMR_IO48_ADDR + 0xe4)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND15 (ARRIA10_HMC_MMR_IO48_ADDR + 0xe8)
+#define ARRIA10_IO48_HMC_MMR_DRAMSTS (ARRIA10_HMC_MMR_IO48_ADDR + 0xec)
+#define ARRIA10_IO48_HMC_MMR_DBGDONE (ARRIA10_HMC_MMR_IO48_ADDR + 0xf0)
+#define ARRIA10_IO48_HMC_MMR_DBGSIGNALS (ARRIA10_HMC_MMR_IO48_ADDR + 0xf4)
+#define ARRIA10_IO48_HMC_MMR_DBGRESET (ARRIA10_HMC_MMR_IO48_ADDR + 0xf8)
+#define ARRIA10_IO48_HMC_MMR_DBGMATCH (ARRIA10_HMC_MMR_IO48_ADDR + 0xfc)
+#define ARRIA10_IO48_HMC_MMR_COUNTER0MASK (ARRIA10_HMC_MMR_IO48_ADDR + 0x100)
+#define ARRIA10_IO48_HMC_MMR_COUNTER1MASK (ARRIA10_HMC_MMR_IO48_ADDR + 0x104)
+#define ARRIA10_IO48_HMC_MMR_COUNTER0MATCH (ARRIA10_HMC_MMR_IO48_ADDR + 0x108)
+#define ARRIA10_IO48_HMC_MMR_COUNTER1MATCH (ARRIA10_HMC_MMR_IO48_ADDR + 0x10c)
+#define ARRIA10_IO48_HMC_MMR_NIOSRESERVE0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x110)
+#define ARRIA10_IO48_HMC_MMR_NIOSRESERVE1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x114)
+#define ARRIA10_IO48_HMC_MMR_NIOSRESERVE2 (ARRIA10_HMC_MMR_IO48_ADDR + 0x118)
+
+union dramaddrw_reg {
+ struct {
+ u32 cfg_col_addr_width:5;
+ u32 cfg_row_addr_width:5;
+ u32 cfg_bank_addr_width:4;
+ u32 cfg_bank_group_addr_width:2;
+ u32 cfg_cs_addr_width:3;
+ u32 reserved:13;
+ };
+ u32 word;
+};
+
+union ctrlcfg0_reg {
+ struct {
+ u32 cfg_mem_type:4;
+ u32 cfg_dimm_type:3;
+ u32 cfg_ac_pos:2;
+ u32 cfg_ctrl_burst_len:5;
+ u32 reserved:18; /* Other fields unused */
+ };
+ u32 word;
+};
+
+union ctrlcfg1_reg {
+ struct {
+ u32 cfg_dbc3_burst_len:5;
+ u32 cfg_addr_order:2;
+ u32 cfg_ctrl_enable_ecc:1;
+ u32 reserved:24; /* Other fields unused */
+ };
+ u32 word;
+};
+
+union caltiming0_reg {
+ struct {
+ u32 cfg_act_to_rdwr:6;
+ u32 cfg_act_to_pch:6;
+ u32 cfg_act_to_act:6;
+ u32 cfg_act_to_act_db:6;
+ u32 reserved:8; /* Other fields unused */
+ };
+ u32 word;
+};
+
+union caltiming1_reg {
+ struct {
+ u32 cfg_rd_to_rd:6;
+ u32 cfg_rd_to_rd_dc:6;
+ u32 cfg_rd_to_rd_db:6;
+ u32 cfg_rd_to_wr:6;
+ u32 cfg_rd_to_wr_dc:6;
+ u32 reserved:2;
+ };
+ u32 word;
+};
+
+union caltiming2_reg {
+ struct {
+ u32 cfg_rd_to_wr_db:6;
+ u32 cfg_rd_to_pch:6;
+ u32 cfg_rd_ap_to_valid:6;
+ u32 cfg_wr_to_wr:6;
+ u32 cfg_wr_to_wr_dc:6;
+ u32 reserved:2;
+ };
+ u32 word;
+};
+
+union caltiming3_reg {
+ struct {
+ u32 cfg_wr_to_wr_db:6;
+ u32 cfg_wr_to_rd:6;
+ u32 cfg_wr_to_rd_dc:6;
+ u32 cfg_wr_to_rd_db:6;
+ u32 cfg_wr_to_pch:6;
+ u32 reserved:2;
+ };
+ u32 word;
+};
+
+union caltiming4_reg {
+ struct {
+ u32 cfg_wr_ap_to_valid:6;
+ u32 cfg_pch_to_valid:6;
+ u32 cfg_pch_all_to_valid:6;
+ u32 cfg_arf_to_valid:8;
+ u32 cfg_pdn_to_valid:6;
+ };
+ u32 word;
+};
+
+union caltiming9_reg {
+ struct {
+ u32 cfg_4_act_to_act:8;
+ u32 reserved:24;
+ };
+ u32 word;
+};
+
+#define IRQ_ECC_SERR 34
+#define IRQ_ECC_DERR 32
+
+#define ARRIA10_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE 0x00000001
+
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_SERRPENA 0x00000001
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_DERRPENA 0x00000002
+#define ARRIA10_ECC_HMC_OCP_ERRINTEN_SERRINTEN 0x00000001
+#define ARRIA10_ECC_HMC_OCP_ERRINTEN_DERRINTEN 0x00000002
+#define ARRIA10_ECC_HMC_OCP_INTMOD_INTONCMP 0x00010000
+#define ARRIA10_ECC_HMC_OCP_INTMOD_SERR 0x00000001
+#define ARRIA10_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY 0x00000100
+#define ARRIA10_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST 0x00010000
+#define ARRIA10_ECC_HMC_OCP_ECCCTL_CNT_RST 0x00000100
+#define ARRIA10_ECC_HMC_OCP_ECCCTL_ECC_EN 0x00000000
+#define ARRIA10_ECC_HMC_OCP_ECCCTL2_RMW_EN 0x00000100
+#define ARRIA10_ECC_HMC_OCP_ECCCTL2_AWB_EN 0x00000001
+#define ARRIA10_ECC_HMC_OCP_ERRINTEN_SERR 0x00000001
+#define ARRIA10_ECC_HMC_OCP_ERRINTEN_DERR 0x00000002
+#define ARRIA10_ECC_HMC_OCP_ERRINTEN_HMI 0x00000004
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_SERR 0x00000001
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_DERR 0x00000002
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_HMI 0x00000004
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG 0x00010000
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_ADDRPARFLG 0x00020000
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_DERRBUSFLG 0x00040000
+
+#define ARRIA10_ECC_HMC_OCP_SERRCNTREG_VALUE 8
+
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB 22
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB 0
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB 0
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB 2
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB 6
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB 15
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB 0
+
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_LSB 0
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB 0
+
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB 4
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB 13
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB 4
+
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB 4
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB 6
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB 6
+
+#define ARRIA10_SDR_FW_MPU_FPGA_EN (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x00)
+#define ARRIA10_SDR_FW_MPU_FPGA_EN_SET (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x04)
+#define ARRIA10_SDR_FW_MPU_FPGA_EN_CLR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x08)
+#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION0ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x10)
+#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION1ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x14)
+#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION2ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x18)
+#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION3ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x1c)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION0ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x20)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION1ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x24)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION2ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x28)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION3ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x2c)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION0ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x30)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION1ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x34)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION2ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x38)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION3ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x3c)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION0ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x40)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION1ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x44)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION2ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x48)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION3ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x4c)
+
+#define ARRIA10_NOC_FW_DDR_MPU_MPUREG0EN BIT(0)
+#define ARRIA10_NOC_FW_DDR_MPU_MPUREG1EN BIT(1)
+#define ARRIA10_NOC_FW_DDR_MPU_MPUREG2EN BIT(2)
+#define ARRIA10_NOC_FW_DDR_MPU_MPUREG3EN BIT(3)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG0EN BIT(4)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG1EN BIT(5)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG2EN BIT(6)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG3EN BIT(7)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG0EN BIT(8)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG1EN BIT(9)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG2EN BIT(10)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG3EN BIT(11)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG0EN BIT(12)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG1EN BIT(13)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG2EN BIT(14)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG3EN BIT(15)
+
+#define ARRIA10_NOC_FW_DDR_L3_EN (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x00)
+#define ARRIA10_NOC_FW_DDR_L3_EN_SET (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x04)
+#define ARRIA10_NOC_FW_DDR_L3_EN_CLR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x08)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION0ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x0c)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION1ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x10)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION2ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x14)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION3ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x18)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION4ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x1c)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION5ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x20)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION6ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x24)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION7ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x28)
+#define ARRIA10_NOC_FW_DDR_L3_GLOBAL (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x2c)
+
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG0EN BIT(0)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG1EN BIT(1)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG2EN BIT(2)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG3EN BIT(3)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG4EN BIT(4)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG5EN BIT(5)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG6EN BIT(6)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG7EN BIT(7)
+
+#define ARRIA10_IO48_DRAMTIME_MEM_READ_LATENCY 0x0000003f
+
+int arria10_ddr_calibration_sequence(void);
+
+#endif
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-system-manager.h b/arch/arm/mach-socfpga/include/mach/arria10-system-manager.h
new file mode 100644
index 0000000..f98cc36
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/arria10-system-manager.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ARRIA10_SYSTEM_MANAGER_H_
+#define _ARRIA10_SYSTEM_MANAGER_H_
+
+#include <mach/arria10-regs.h>
+
+#define ARRIA10_SYSMGR_SILICONID1 (ARRIA10_SYSMGR_ADDR + 0x00)
+#define ARRIA10_SYSMGR_SILICONID2 (ARRIA10_SYSMGR_ADDR + 0x04)
+#define ARRIA10_SYSMGR_WDDBG (ARRIA10_SYSMGR_ADDR + 0x08)
+#define ARRIA10_SYSMGR_BOOTINFO (ARRIA10_SYSMGR_ADDR + 0x0c)
+#define ARRIA10_SYSMGR_MPU_CTRL_L2_ECC (ARRIA10_SYSMGR_ADDR + 0x10)
+#define ARRIA10_SYSMGR_DMA (ARRIA10_SYSMGR_ADDR + 0x20)
+#define ARRIA10_SYSMGR_DMA_PERIPH (ARRIA10_SYSMGR_ADDR + 0x24)
+#define ARRIA10_SYSMGR_SDMMC (ARRIA10_SYSMGR_ADDR + 0x28)
+#define ARRIA10_SYSMGR_SDMMC_L3MASTER (ARRIA10_SYSMGR_ADDR + 0x2c)
+#define ARRIA10_SYSMGR_NAND_BOOTSTRAP (ARRIA10_SYSMGR_ADDR + 0x30)
+#define ARRIA10_SYSMGR_NAND_L3MASTER (ARRIA10_SYSMGR_ADDR + 0x34)
+#define ARRIA10_SYSMGR_USB0_L3MASTER (ARRIA10_SYSMGR_ADDR + 0x38)
+#define ARRIA10_SYSMGR_USB1_L3MASTER (ARRIA10_SYSMGR_ADDR + 0x3c)
+#define ARRIA10_SYSMGR_EMAC_GLOBAL (ARRIA10_SYSMGR_ADDR + 0x40)
+#define ARRIA10_SYSMGR_EMAC0 (ARRIA10_SYSMGR_ADDR + 0x44)
+#define ARRIA10_SYSMGR_EMAC1 (ARRIA10_SYSMGR_ADDR + 0x48)
+#define ARRIA10_SYSMGR_EMAC2 (ARRIA10_SYSMGR_ADDR + 0x4c)
+#define ARRIA10_SYSMGR_FPGAINTF_GLOBAL (ARRIA10_SYSMGR_ADDR + 0x60)
+#define ARRIA10_SYSMGR_FPGAINTF_EN_0 (ARRIA10_SYSMGR_ADDR + 0x64)
+#define ARRIA10_SYSMGR_FPGAINTF_EN_1 (ARRIA10_SYSMGR_ADDR + 0x68)
+#define ARRIA10_SYSMGR_FPGAINTF_EN_2 (ARRIA10_SYSMGR_ADDR + 0x6c)
+#define ARRIA10_SYSMGR_FPGAINTF_EN_3 (ARRIA10_SYSMGR_ADDR + 0x70)
+#define ARRIA10_SYSMGR_NOC_ADDR_REMAP_VALUE (ARRIA10_SYSMGR_ADDR + 0x80)
+#define ARRIA10_SYSMGR_NOC_ADDR_REMAP_SET (ARRIA10_SYSMGR_ADDR + 0x84)
+#define ARRIA10_SYSMGR_NOC_ADDR_REMAP_CLEAR (ARRIA10_SYSMGR_ADDR + 0x88)
+#define ARRIA10_SYSMGR_ECC_INTMASK_VALUE (ARRIA10_SYSMGR_ADDR + 0x90)
+#define ARRIA10_SYSMGR_ECC_INTMASK_SET (ARRIA10_SYSMGR_ADDR + 0x94)
+#define ARRIA10_SYSMGR_ECC_INTMASK_CLR (ARRIA10_SYSMGR_ADDR + 0x98)
+#define ARRIA10_SYSMGR_ECC_INTSTATUS_SERR (ARRIA10_SYSMGR_ADDR + 0x9c)
+#define ARRIA10_SYSMGR_ECC_INTSTATUS_DERR (ARRIA10_SYSMGR_ADDR + 0xa0)
+#define ARRIA10_SYSMGR_MPU_STATUS_L2_ECC (ARRIA10_SYSMGR_ADDR + 0xa4)
+#define ARRIA10_SYSMGR_MPU_CLEAR_L2_ECC (ARRIA10_SYSMGR_ADDR + 0xa8)
+#define ARRIA10_SYSMGR_MPU_STATUS_L1_PARITY (ARRIA10_SYSMGR_ADDR + 0xac)
+#define ARRIA10_SYSMGR_MPU_CLEAR_L1_PARITY (ARRIA10_SYSMGR_ADDR + 0xb0)
+#define ARRIA10_SYSMGR_MPU_SET_L1_PARITY (ARRIA10_SYSMGR_ADDR + 0xb4)
+#define ARRIA10_SYSMGR_NOC_TIMEOUT (ARRIA10_SYSMGR_ADDR + 0xc0)
+#define ARRIA10_SYSMGR_NOC_IDLEREQ_SET (ARRIA10_SYSMGR_ADDR + 0xc4)
+#define ARRIA10_SYSMGR_NOC_IDLEREQ_CLR (ARRIA10_SYSMGR_ADDR + 0xc8)
+#define ARRIA10_SYSMGR_NOC_IDLEREQ_VALUE (ARRIA10_SYSMGR_ADDR + 0xcc)
+#define ARRIA10_SYSMGR_NOC_IDLEACK (ARRIA10_SYSMGR_ADDR + 0xd0)
+#define ARRIA10_SYSMGR_NOC_IDLESTATUS (ARRIA10_SYSMGR_ADDR + 0xd4)
+#define ARRIA10_SYSMGR_FPGA2SOC_CTRL (ARRIA10_SYSMGR_ADDR + 0xd8)
+
+/* pin mux */
+#define ARRIA10_SYSMGR_PINMUXGRP (ARRIA10_SYSMGR_ADDR + 0x400)
+#define ARRIA10_SYSMGR_PINMUXGRP_NANDUSEFPGA (ARRIA10_SYSMGR_PINMUXGRP + 0x2F0)
+#define ARRIA10_SYSMGR_PINMUXGRP_EMAC1USEFPGA (ARRIA10_SYSMGR_PINMUXGRP + 0x2F8)
+#define ARRIA10_SYSMGR_PINMUXGRP_SDMMCUSEFPGA (ARRIA10_SYSMGR_PINMUXGRP + 0x308)
+#define ARRIA10_SYSMGR_PINMUXGRP_EMAC0USEFPGA (ARRIA10_SYSMGR_PINMUXGRP + 0x314)
+#define ARRIA10_SYSMGR_PINMUXGRP_SPIM1USEFPGA (ARRIA10_SYSMGR_PINMUXGRP + 0x330)
+#define ARRIA10_SYSMGR_PINMUXGRP_SPIM0USEFPGA (ARRIA10_SYSMGR_PINMUXGRP + 0x338)
+
+/* bit fields */
+#define ARRIA10_SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
+#define ARRIA10_SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1)
+#define ARRIA10_SYSMGR_ECC_OCRAM_EN BIT(0)
+#define ARRIA10_SYSMGR_ECC_OCRAM_SERR BIT(3)
+#define ARRIA10_SYSMGR_ECC_OCRAM_DERR BIT(4)
+#define ARRIA10_SYSMGR_FPGAINTF_USEFPGA BIT(1)
+#define ARRIA10_SYSMGR_FPGAINTF_SPIM0 BIT(0)
+#define ARRIA10_SYSMGR_FPGAINTF_SPIM1 BIT(1)
+#define ARRIA10_SYSMGR_FPGAINTF_EMAC0 BIT(2)
+#define ARRIA10_SYSMGR_FPGAINTF_EMAC1 BIT(3)
+#define ARRIA10_SYSMGR_FPGAINTF_NAND BIT(4)
+#define ARRIA10_SYSMGR_FPGAINTF_SDMMC BIT(5)
+
+#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
+#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
+#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
+#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_LSB 0
+#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
+
+#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC0 BIT(0)
+#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC0_SW BIT(4)
+#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC1 BIT(8)
+#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC1_SW BIT(12)
+#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC2 BIT(16)
+#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC2_SW BIT(20)
+
+#define ARRIA10_SYSMGR_SDMMC_SMPLSEL(smplsel) (((smplsel) & 0x7) << 4)
+#define ARRIA10_SYSMGR_SDMMC_DRVSEL(drvsel) ((drvsel) & 0x7)
+
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
+ ((drvsel << 0) & 0x7) | ((smplsel << 4) & 0x70)
+
+#endif
diff --git a/arch/arm/mach-socfpga/include/mach/barebox-arm-head.h b/arch/arm/mach-socfpga/include/mach/barebox-arm-head.h
new file mode 100644
index 0000000..28fb1c9
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/barebox-arm-head.h
@@ -0,0 +1,42 @@
+static inline void __barebox_arm_head(void)
+{
+ __asm__ __volatile__ (
+#ifdef CONFIG_THUMB2_BAREBOX
+ ".arm\n"
+ "adr r9, 1f + 1\n"
+ "bx r9\n"
+ ".thumb\n"
+ "1:\n"
+ "bl 2f\n"
+ ".rept 10\n"
+ "1: b 1b\n"
+ ".endr\n"
+#else
+ "b 2f\n"
+ "1: b 1b\n"
+ "1: b 1b\n"
+ "1: b 1b\n"
+ "1: b 1b\n"
+ "1: b 1b\n"
+ "1: b 1b\n"
+ "1: b 1b\n"
+#endif
+ ".asciz \"barebox\"\n"
+ ".word _text\n" /* text base. If copied there,
+ * barebox can skip relocation
+ */
+ ".word _barebox_image_size\n" /* image size to copy */
+
+ ".rept 10\n"
+ ".word 0x55555555\n"
+ ".endr\n"
+ "2:\n"
+ );
+}
+static inline void barebox_arm_head(void)
+{
+ __barebox_arm_head();
+ __asm__ __volatile__ (
+ "b barebox_arm_reset_vector\n"
+ );
+}
diff --git a/arch/arm/mach-socfpga/include/mach/clock-manager.h b/arch/arm/mach-socfpga/include/mach/cyclone5-clock-manager.h
index 45800de..797aa5d 100644
--- a/arch/arm/mach-socfpga/include/mach/clock-manager.h
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-clock-manager.h
@@ -15,8 +15,8 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef _CLOCK_MANAGER_H_
-#define _CLOCK_MANAGER_H_
+#ifndef _CLOCK_MANAGER_CYCLONE5_H_
+#define _CLOCK_MANAGER_CYCLONE5_H_
struct socfpga_cm_config {
/* main group */
@@ -197,4 +197,4 @@ void socfpga_cm_basic_init(const struct socfpga_cm_config *cfg);
CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
-#endif /* _CLOCK_MANAGER_H_ */
+#endif
diff --git a/arch/arm/mach-socfpga/include/mach/freeze-controller.h b/arch/arm/mach-socfpga/include/mach/cyclone5-freeze-controller.h
index 4253f5b..93ce515 100644
--- a/arch/arm/mach-socfpga/include/mach/freeze-controller.h
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-freeze-controller.h
@@ -15,10 +15,10 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef _FREEZE_CONTROLLER_H_
-#define _FREEZE_CONTROLLER_H_
+#ifndef _CYCLONE5_FREEZE_CONTROLLER_H_
+#define _CYCLONE5_FREEZE_CONTROLLER_H_
-#include <mach/socfpga-regs.h>
+#include <mach/cyclone5-regs.h>
#define SYSMGR_FRZCTRL_ADDRESS 0x40
#define SYSMGR_FRZCTRL_VIOCTRL_ADDRESS 0x40
diff --git a/arch/arm/mach-socfpga/include/mach/socfpga-regs.h b/arch/arm/mach-socfpga/include/mach/cyclone5-regs.h
index e88daf7..e88daf7 100644
--- a/arch/arm/mach-socfpga/include/mach/socfpga-regs.h
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-regs.h
diff --git a/arch/arm/mach-socfpga/include/mach/reset-manager.h b/arch/arm/mach-socfpga/include/mach/cyclone5-reset-manager.h
index 899401c..899401c 100644
--- a/arch/arm/mach-socfpga/include/mach/reset-manager.h
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-reset-manager.h
diff --git a/arch/arm/mach-socfpga/include/mach/scan-manager.h b/arch/arm/mach-socfpga/include/mach/cyclone5-scan-manager.h
index 568bedf..df720a7 100644
--- a/arch/arm/mach-socfpga/include/mach/scan-manager.h
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-scan-manager.h
@@ -19,7 +19,7 @@
#define _SCAN_MANAGER_H_
#include <io.h>
-#include <mach/socfpga-regs.h>
+#include <mach/cyclone5-regs.h>
/***********************************************************
* *
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_config.h b/arch/arm/mach-socfpga/include/mach/cyclone5-sdram-config.h
index 2af797a..a19a837 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_config.h
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-sdram-config.h
@@ -1,9 +1,9 @@
#ifndef __MACH_SDRAM_CONFIG_H
#define __MACH_SDRAM_CONFIG_H
-#include <mach/sdram.h>
-#include <mach/socfpga-regs.h>
-#include <mach/system-manager.h>
+#include <mach/cyclone5-sdram.h>
+#include <mach/cyclone5-regs.h>
+#include <mach/cyclone5-system-manager.h>
static inline void sdram_write(unsigned register_offset, unsigned val)
{
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/cyclone5-sdram.h
index ebd331e..ebd331e 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-sdram.h
diff --git a/arch/arm/mach-socfpga/include/mach/sequencer.c b/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c
index d2338e6..e5ecb0f 100644
--- a/arch/arm/mach-socfpga/include/mach/sequencer.c
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c
@@ -26,11 +26,9 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "sequencer_defines.h"
-
#include "system.h"
#include "sdram_io.h"
-#include "sequencer.h"
+#include "cyclone5-sequencer.h"
#include "tclrpt.h"
/******************************************************************************
@@ -57,7 +55,7 @@ asm(".global __alt_stack_pointer");
asm("__alt_stack_pointer = " STRINGIFY(STACK_POINTER));
#endif
-#include <mach/sdram.h>
+#include <mach/cyclone5-sdram.h>
#define NEWVERSION_RDDESKEW 1
#define NEWVERSION_WRDESKEW 1
diff --git a/arch/arm/mach-socfpga/include/mach/sequencer.h b/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.h
index d2da21d..d2da21d 100644
--- a/arch/arm/mach-socfpga/include/mach/sequencer.h
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.h
diff --git a/arch/arm/mach-socfpga/include/mach/system-manager.h b/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h
index 9efc37a..9efc37a 100644
--- a/arch/arm/mach-socfpga/include/mach/system-manager.h
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h
diff --git a/arch/arm/mach-socfpga/include/mach/debug_ll.h b/arch/arm/mach-socfpga/include/mach/debug_ll.h
index f378435..f41258c 100644
--- a/arch/arm/mach-socfpga/include/mach/debug_ll.h
+++ b/arch/arm/mach-socfpga/include/mach/debug_ll.h
@@ -2,24 +2,33 @@
#define __MACH_DEBUG_LL_H__
#include <io.h>
+#include <errno.h>
-#define UART_BASE 0xffc02000
+#ifdef CONFIG_DEBUG_LL
+#define UART_BASE CONFIG_DEBUG_SOCFPGA_UART_PHYS_ADDR
+#endif
#define LSR_THRE 0x20 /* Xmit holding register empty */
-#define LSR (5 << 2)
-#define THR (0 << 2)
+#define LSR_TEMT 0x40
#define LCR_BKSE 0x80 /* Bank select enable */
-#define LSR (5 << 2)
-#define THR (0 << 2)
-#define DLL (0 << 2)
-#define IER (1 << 2)
-#define DLM (1 << 2)
-#define FCR (2 << 2)
-#define LCR (3 << 2)
-#define MCR (4 << 2)
-#define MDR (8 << 2)
+#define LCRVAL 0x3
+#define MCRVAL 0x3
+#define FCRVAL 0xc1
+
+#define RBR 0x0
+#define DLL 0x0
+#define IER 0x4
+#define DLM 0x4
+#define FCR 0x8
+#define LCR 0xc
+#define MCR 0x10
+#define LSR 0x14
+#define MSR 0x18
+#define SCR 0x1c
+#define THR 0x30
+#ifdef CONFIG_DEBUG_LL
static inline unsigned int ns16550_calc_divisor(unsigned int clk,
unsigned int baudrate)
{
@@ -28,21 +37,33 @@ static inline unsigned int ns16550_calc_divisor(unsigned int clk,
static inline void INIT_LL(void)
{
- unsigned int clk = 100000000;
- unsigned int divisor = clk / 16 / 115200;
-
- writeb(0x00, UART_BASE + LCR);
- writeb(0x00, UART_BASE + IER);
- writeb(0x07, UART_BASE + MDR);
- writeb(LCR_BKSE, UART_BASE + LCR);
- writeb(divisor & 0xff, UART_BASE + DLL);
- writeb(divisor >> 8, UART_BASE + DLM);
- writeb(0x03, UART_BASE + LCR);
- writeb(0x03, UART_BASE + MCR);
- writeb(0x07, UART_BASE + FCR);
- writeb(0x00, UART_BASE + MDR);
+ unsigned int div = ns16550_calc_divisor(CONFIG_DEBUG_SOCFPGA_UART_CLOCK,
+ 115200);
+
+ while ((readl(UART_BASE + LSR) & LSR_TEMT) == 0);
+
+ writel(0x00, UART_BASE + IER);
+
+ writel(LCR_BKSE, UART_BASE + LCR);
+ writel(div & 0xff, UART_BASE + DLL);
+ writel((div >> 8) & 0xff, UART_BASE + DLM);
+ writel(LCRVAL, UART_BASE + LCR);
+
+ writel(MCRVAL, UART_BASE + MCR);
+ writel(FCRVAL, UART_BASE + FCR);
}
+#ifdef CONFIG_ARCH_SOCFPGA_ARRIA10
+static inline void PUTC_LL(char c)
+{
+ /* Wait until there is space in the FIFO */
+ while ((readl(UART_BASE + LSR) & LSR_THRE) == 0);
+ /* Send the character */
+ writel(c, UART_BASE + THR);
+ /* Wait to make sure it hits the line, in case we die too soon. */
+ while ((readl(UART_BASE + LSR) & LSR_THRE) == 0);
+}
+#else
static inline void PUTC_LL(char c)
{
/* Wait until there is space in the FIFO */
@@ -53,3 +74,13 @@ static inline void PUTC_LL(char c)
while ((readb(UART_BASE + LSR) & LSR_THRE) == 0);
}
#endif
+
+#else
+static inline unsigned int ns16550_calc_divisor(unsigned int clk,
+ unsigned int baudrate) {
+ return -ENOSYS;
+}
+static inline void INIT_LL(void) {}
+static inline void PUTC_LL(char c) {}
+#endif
+#endif
diff --git a/arch/arm/mach-socfpga/include/mach/generic.h b/arch/arm/mach-socfpga/include/mach/generic.h
index 2a7e0ea..9d6dd1f 100644
--- a/arch/arm/mach-socfpga/include/mach/generic.h
+++ b/arch/arm/mach-socfpga/include/mach/generic.h
@@ -1,13 +1,49 @@
#ifndef __MACH_SOCFPGA_GENERIC_H
#define __MACH_SOCFPGA_GENERIC_H
+#include <linux/types.h>
+
struct socfpga_cm_config;
struct socfpga_io_config;
+struct arria10_mainpll_cfg;
+struct arria10_perpll_cfg;
+struct arria10_pinmux_cfg;
+
+void arria10_init(struct arria10_mainpll_cfg *mainpll,
+ struct arria10_perpll_cfg *perpll, uint32_t *pinmux);
+
void socfpga_lowlevel_init(struct socfpga_cm_config *cm_config,
struct socfpga_io_config *io_config);
+#if defined(CONFIG_ARCH_SOCFPGA_CYCLONE5)
+void socfpga_cyclone5_mmc_init(void);
+void socfpga_cyclone5_uart_init(void);
+void socfpga_cyclone5_timer_init(void);
+void socfpga_cyclone5_qspi_init(void);
+#else
+static inline void socfpga_cyclone5_mmc_init(void)
+{
+ return;
+}
+
+static inline void socfpga_cyclone5_uart_init(void)
+{
+ return;
+}
+
+static inline void socfpga_cyclone5_timer_init(void)
+{
+ return;
+}
+
+static inline void socfpga_cyclone5_qspi_init(void)
+{
+ return;
+}
+#endif
+
static inline void __udelay(unsigned us)
{
volatile unsigned int i;
diff --git a/arch/arm/mach-socfpga/include/mach/pll_config.h b/arch/arm/mach-socfpga/include/mach/pll_config.h
index bb491d8..1a7e851 100644
--- a/arch/arm/mach-socfpga/include/mach/pll_config.h
+++ b/arch/arm/mach-socfpga/include/mach/pll_config.h
@@ -1,5 +1,5 @@
-#include <mach/clock-manager.h>
+#include <mach/cyclone5-clock-manager.h>
static struct socfpga_cm_config cm_default_cfg = {
/* main group */
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_io.h b/arch/arm/mach-socfpga/include/mach/sdram_io.h
index 6269800..ef87bda 100755..100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_io.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_io.h
@@ -26,7 +26,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include <mach/sdram.h>
+#include <mach/cyclone5-sdram.h>
#define MGR_SELECT_MASK 0xf8000
diff --git a/arch/arm/mach-socfpga/include/mach/sequencer_defines.h b/arch/arm/mach-socfpga/include/mach/sequencer_defines.h
deleted file mode 100644
index 5059844..0000000
--- a/arch/arm/mach-socfpga/include/mach/sequencer_defines.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#define TINIT_CNTR1_VAL 32
-#define TINIT_CNTR2_VAL 32
-#define TINIT_CNTR0_VAL 99
-#define TRESET_CNTR1_VAL 99
-#define TRESET_CNTR2_VAL 10
-#define TRESET_CNTR0_VAL 99
diff --git a/arch/arm/mach-socfpga/include/mach/system.h b/arch/arm/mach-socfpga/include/mach/system.h
index 89527b2..89527b2 100755..100644
--- a/arch/arm/mach-socfpga/include/mach/system.h
+++ b/arch/arm/mach-socfpga/include/mach/system.h
diff --git a/arch/arm/mach-socfpga/include/mach/tclrpt.h b/arch/arm/mach-socfpga/include/mach/tclrpt.h
index 4345b23..6b332c8 100755..100644
--- a/arch/arm/mach-socfpga/include/mach/tclrpt.h
+++ b/arch/arm/mach-socfpga/include/mach/tclrpt.h
@@ -28,7 +28,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "sequencer.h"
+#include "cyclone5-sequencer.h"
#define TCLRPT_SET(item, value)