ARM: socfpga: add arria10 support

Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that
is already supported in barebox.
Both a the same in some parts, but totaly different in
others. Most of the hardware blocks are the same in the
SoC parts. The OCRAM is larger on the Arria10 and the
SDRAM controller is different.
The serial core only supports 32bit accesses (different to
the 8bit accesses on the Cyclone5).

As Arria10 has 256KB of OCRAM, it is possible to fit a larger
barebox (and/or use PBL) instead of the two stage bootprocess
used on the Cyclone5 and its 64KB OCRAM.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

20 files changed, 3420 insertions, 196 deletions

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 04b5416b64..0a33e88644 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -12,16 +12,35 @@ config ARCH_TEXT_BASE
 	hex
 	default 0x00100000 if MACH_SOCFPGA_CYCLONE5
 
+comment "Altera SoCFPGA System-on-Chip"
+
+config ARCH_SOCFPGA_CYCLONE5
+	bool
+	select CPU_V7
+
+config ARCH_SOCFPGA_ARRIA10
+	bool
+	select CPU_V7
+	select HAVE_MACH_ARM_HEAD
+
 config MACH_SOCFPGA_ALTERA_SOCDK
+	select HAVE_DEFAULT_ENVIRONMENT_NEW
+	select ARCH_SOCFPGA_CYCLONE5
 	bool "Altera SoCFPGA Development Kit"
 
 config MACH_SOCFPGA_EBV_SOCRATES
+	select HAVE_DEFAULT_ENVIRONMENT_NEW
+	select ARCH_SOCFPGA_CYCLONE5
 	bool "EBV Socrates"
 
 config MACH_SOCFPGA_TERASIC_DE0_NANO_SOC
+	select HAVE_DEFAULT_ENVIRONMENT_NEW
+	select ARCH_SOCFPGA_CYCLONE5
 	bool "Terasic DE0-NANO-SoC aka Atlas"
 
 config MACH_SOCFPGA_TERASIC_SOCKIT
+	select HAVE_DEFAULT_ENVIRONMENT_NEW
+	select ARCH_SOCFPGA_CYCLONE5
 	bool "Terasic SoCKit"
 
 endif
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 30b796dd3b..cbb47fa206 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -1,4 +1,8 @@
-pbl-y += cyclone5-init.o cyclone5-freeze-controller.o cyclone5-scan-manager.o cyclone5-system-manager.o
-pbl-y += cyclone5-clock-manager.o
-obj-y += cyclone5-generic.o nic301.o cyclone5-bootsource.o cyclone5-reset-manager.o
+pbl-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-init.o cyclone5-freeze-controller.o cyclone5-scan-manager.o cyclone5-system-manager.o
+pbl-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-clock-manager.o
+obj-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-generic.o nic301.o cyclone5-bootsource.o cyclone5-reset-manager.o
+
+pbl-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += arria10-init.o arria10-clock-manager.o arria10-sdram.o arria10-reset-manager.o arria10-bootsource.o
+obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += arria10-bootsource.o arria10-generic.o arria10-reset-manager.o
+
 obj-$(CONFIG_ARCH_SOCFPGA_XLOAD) += xload.o
diff --git a/arch/arm/mach-socfpga/arria10-bootsource.c b/arch/arm/mach-socfpga/arria10-bootsource.c
new file mode 100644
index 0000000000..26af64a1a4
--- /dev/null
+++ b/arch/arm/mach-socfpga/arria10-bootsource.c
@@ -0,0 +1,53 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <bootsource.h>
+#include <init.h>
+#include <io.h>
+#include <mach/arria10-system-manager.h>
+
+static int arria10_boot_save_loc(void)
+{
+	enum bootsource src = BOOTSOURCE_UNKNOWN;
+	uint32_t val;
+
+	val = readl(ARRIA10_SYSMGR_BOOTINFO);
+
+	switch ((val & 0x7000) >> 12) {
+	case 0:
+		/* reserved */
+		break;
+	case 1:
+		/* FPGA, currently not decoded */
+		break;
+	case 2:
+	case 3:
+		src = BOOTSOURCE_NAND;
+		break;
+	case 4:
+	case 5:
+		src = BOOTSOURCE_MMC;
+		break;
+	case 6:
+	case 7:
+		src = BOOTSOURCE_SPI;
+		break;
+	}
+
+	bootsource_set(src);
+	bootsource_set_instance(0);
+
+	return 0;
+}
+core_initcall(arria10_boot_save_loc);
diff --git a/arch/arm/mach-socfpga/arria10-clock-manager.c b/arch/arm/mach-socfpga/arria10-clock-manager.c
new file mode 100644
index 0000000000..8052afe2d8
--- /dev/null
+++ b/arch/arm/mach-socfpga/arria10-clock-manager.c
@@ -0,0 +1,815 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/generic.h>
+#include <mach/arria10-regs.h>
+#include <mach/arria10-clock-manager.h>
+
+static const struct arria10_clock_manager *arria10_clkmgr_base =
+	(void *)ARRIA10_CLKMGR_ADDR;
+
+static uint32_t eosc1_hz;
+static uint32_t cb_intosc_hz;
+static uint32_t f2s_free_hz;
+#define LOCKED_MASK	(ARRIA10_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
+			 ARRIA10_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
+
+static inline void arria10_cm_wait_for_lock(uint32_t mask)
+{
+	register uint32_t inter_val;
+
+	do {
+		inter_val = readl(&arria10_clkmgr_base->stat) & mask;
+	} while (inter_val != mask);
+}
+
+/* function to poll in the fsm busy bit */
+static inline void arria10_cm_wait4fsm(void)
+{
+	register uint32_t inter_val;
+
+	do {
+		inter_val = readl(&arria10_clkmgr_base->stat) &
+			ARRIA10_CLKMGR_CLKMGR_STAT_BUSY_SET_MSK;
+	} while (inter_val);
+}
+
+static uint32_t arria10_cm_get_main_vco(void)
+{
+	uint32_t vco1, src_hz, numer, denom, vco;
+	uint32_t clk_src = readl(&arria10_clkmgr_base->main_pll_vco0);
+
+	clk_src = (clk_src >> ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_LSB) &
+		ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_MSK;
+
+	switch (clk_src) {
+	case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_EOSC:
+		src_hz = eosc1_hz;
+		break;
+	case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC:
+		src_hz = cb_intosc_hz;
+		break;
+	case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_F2S:
+		src_hz = f2s_free_hz;
+		break;
+	default:
+		pr_err("arria10_cm_get_main_vco invalid clk_src %d\n", clk_src);
+		return 0;
+	}
+
+	vco1 = readl(&arria10_clkmgr_base->main_pll_vco1);
+	numer = vco1 & ARRIA10_CLKMGR_MAINPLL_VCO1_NUMER_MSK;
+	denom = (vco1 >> ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB) &
+		 ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_MSK;
+	vco = src_hz * (1 + numer);
+	vco /= 1 + denom;
+
+	return vco;
+}
+
+static uint32_t arria10_cm_get_peri_vco(void)
+{
+	uint32_t vco1, src_hz, numer, denom, vco;
+	uint32_t clk_src = readl(&arria10_clkmgr_base->per_pll_vco0);
+
+	clk_src = (clk_src >> ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_LSB) &
+		ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MSK;
+
+	switch (clk_src) {
+	case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_EOSC:
+		src_hz = eosc1_hz;
+		break;
+	case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC:
+		src_hz = cb_intosc_hz;
+		break;
+	case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_F2S:
+		src_hz = f2s_free_hz;
+		break;
+	case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MAIN:
+		src_hz = arria10_cm_get_main_vco();
+		src_hz /= (readl(&arria10_clkmgr_base->main_pll_cntr15clk) &
+			   ARRIA10_CLKMGR_MAINPLL_CNTRCLK_MSK) + 1;
+		break;
+	default:
+		pr_err("arria10_cm_get_peri_vco invalid clk_src %d\n", clk_src);
+		return 0;
+	}
+
+	vco1 = readl(&arria10_clkmgr_base->per_pll_vco1);
+	numer = vco1 & ARRIA10_CLKMGR_PERPLL_VCO1_NUMER_MSK;
+	denom = (vco1 >> ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB) &
+		ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_MSK;
+	vco = src_hz * (1 + numer);
+	vco /= 1 + denom;
+
+	return vco;
+}
+
+unsigned int arria10_cm_get_mmc_controller_clk_hz(void)
+{
+	uint32_t clk_hz = 0;
+	uint32_t clk_input = readl(&arria10_clkmgr_base->per_pll_cntr6clk);
+	clk_input = (clk_input >> ARRIA10_CLKMGR_PERPLL_CNTR6CLK_SRC_LSB) &
+		ARRIA10_CLKMGR_PERPLLGRP_SRC_MSK;
+
+	switch (clk_input) {
+	case ARRIA10_CLKMGR_PERPLLGRP_SRC_MAIN:
+		clk_hz = arria10_cm_get_main_vco();
+		clk_hz /= 1 + (readl(&arria10_clkmgr_base->main_pll_cntr6clk) &
+			       ARRIA10_CLKMGR_MAINPLL_CNTRCLK_MSK);
+		break;
+
+	case ARRIA10_CLKMGR_PERPLLGRP_SRC_PERI:
+		clk_hz = arria10_cm_get_peri_vco();
+		clk_hz /= 1 + (readl(&arria10_clkmgr_base->per_pll_cntr6clk) &
+			       ARRIA10_CLKMGR_PERPLL_CNTRCLK_MSK);
+		break;
+
+	case ARRIA10_CLKMGR_PERPLLGRP_SRC_OSC1:
+		clk_hz = eosc1_hz;
+		break;
+
+	case ARRIA10_CLKMGR_PERPLLGRP_SRC_INTOSC:
+		clk_hz = cb_intosc_hz;
+		break;
+
+	case ARRIA10_CLKMGR_PERPLLGRP_SRC_FPGA:
+		clk_hz = f2s_free_hz;
+		break;
+	}
+
+	return clk_hz/4;
+}
+
+/* calculate the intended main VCO frequency based on handoff */
+static uint32_t arria10_cm_calc_handoff_main_vco_clk_hz(struct arria10_mainpll_cfg *main_cfg)
+{
+	uint32_t clk_hz;
+
+	/* Check main VCO clock source: eosc, intosc or f2s? */
+	switch (main_cfg->vco0_psrc) {
+	case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_EOSC:
+		clk_hz = eosc1_hz;
+		break;
+	case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC:
+		clk_hz = cb_intosc_hz;
+		break;
+	case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_F2S:
+		clk_hz = f2s_free_hz;
+		break;
+	default:
+		return 0;
+	}
+
+	/* calculate the VCO frequency */
+	clk_hz *= 1 + main_cfg->vco1_numer;
+	clk_hz /= 1 + main_cfg->vco1_denom;
+
+	return clk_hz;
+}
+
+/* calculate the intended periph VCO frequency based on handoff */
+static uint32_t arria10_cm_calc_handoff_periph_vco_clk_hz(struct arria10_mainpll_cfg *main_cfg,
+							  struct arria10_perpll_cfg *per_cfg)
+{
+	uint32_t clk_hz;
+
+	/* Check periph VCO clock source: eosc, intosc, f2s or mainpll? */
+	switch (per_cfg->vco0_psrc) {
+	case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_EOSC:
+		clk_hz = eosc1_hz;
+		break;
+	case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC:
+		clk_hz = cb_intosc_hz;
+		break;
+	case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_F2S:
+		clk_hz = f2s_free_hz;
+		break;
+	case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MAIN:
+		clk_hz = arria10_cm_calc_handoff_main_vco_clk_hz(main_cfg);
+		clk_hz /= main_cfg->cntr15clk_cnt;
+		break;
+	default:
+		return 0;
+	}
+
+	/* calculate the VCO frequency */
+	clk_hz *= 1 + per_cfg->vco1_numer;
+	clk_hz /= 1 + per_cfg->vco1_denom;
+
+	return clk_hz;
+}
+
+/* calculate the intended MPU clock frequency based on handoff */
+static uint32_t arria10_cm_calc_handoff_mpu_clk_hz(struct arria10_mainpll_cfg *main_cfg,
+						   struct arria10_perpll_cfg *per_cfg)
+{
+	uint32_t clk_hz;
+
+	/* Check MPU clock source: main, periph, osc1, intosc or f2s? */
+	switch (main_cfg->mpuclk_src) {
+	case ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN:
+		clk_hz = arria10_cm_calc_handoff_main_vco_clk_hz(main_cfg);
+		clk_hz /= ((main_cfg->mpuclk & ARRIA10_CLKMGR_MAINPLL_MPUCLK_CNT_MSK)
+			   + 1);
+		break;
+	case ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI:
+		clk_hz = arria10_cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);
+		clk_hz /= (((main_cfg->mpuclk >>
+			   ARRIA10_CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) &
+			   ARRIA10_CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1);
+		break;
+	case ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_OSC1:
+		clk_hz = eosc1_hz;
+		break;
+	case ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC:
+		clk_hz = cb_intosc_hz;
+		break;
+	case ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_FPGA:
+		clk_hz = f2s_free_hz;
+		break;
+	default:
+		return 0;
+	}
+
+	clk_hz /= (main_cfg->mpuclk_cnt + 1);
+
+	return clk_hz;
+}
+
+/* calculate the intended NOC clock frequency based on handoff */
+static uint32_t arria10_cm_calc_handoff_noc_clk_hz(struct arria10_mainpll_cfg *main_cfg,
+						   struct arria10_perpll_cfg *per_cfg)
+{
+	uint32_t clk_hz;
+
+	/* Check MPU clock source: main, periph, osc1, intosc or f2s? */
+	switch (main_cfg->nocclk_src) {
+	case ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN:
+		clk_hz = arria10_cm_calc_handoff_main_vco_clk_hz(main_cfg);
+		clk_hz /= ((main_cfg->nocclk & ARRIA10_CLKMGR_MAINPLL_NOCCLK_CNT_MSK)
+			   + 1);
+		break;
+	case ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI:
+		clk_hz = arria10_cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);
+		clk_hz /= (((main_cfg->nocclk >>
+			   ARRIA10_CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) &
+			   ARRIA10_CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1);
+		break;
+	case ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_OSC1:
+		clk_hz = eosc1_hz;
+		break;
+	case ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC:
+		clk_hz = cb_intosc_hz;
+		break;
+	case ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_FPGA:
+		clk_hz = f2s_free_hz;
+		break;
+	default:
+		return 0;
+	}
+
+	clk_hz /= (main_cfg->nocclk_cnt + 1);
+
+	return clk_hz;
+}
+
+/* return 1 if PLL ramp is required */
+static int arria10_cm_is_pll_ramp_required(int main0periph1,
+					   struct arria10_mainpll_cfg *main_cfg,
+					   struct arria10_perpll_cfg *per_cfg)
+{
+
+	/* Check for main PLL */
+	if (main0periph1 == 0) {
+		/*
+		 * PLL ramp is not required if both MPU clock and NOC clock are
+		 * not sourced from main PLL
+		 */
+		if (main_cfg->mpuclk_src != ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
+		    main_cfg->nocclk_src != ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN)
+			return 0;
+
+		/*
+		 * PLL ramp is required if MPU clock is sourced from main PLL
+		 * and MPU clock is over 900MHz (as advised by HW team)
+		 */
+		if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
+		    (arria10_cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
+		     ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
+			return 1;
+
+		/*
+		 * PLL ramp is required if NOC clock is sourced from main PLL
+		 * and NOC clock is over 300MHz (as advised by HW team)
+		 */
+		if (main_cfg->nocclk_src == ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN &&
+		    (arria10_cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
+		     ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
+			return 1;
+
+	} else if (main0periph1 == 1) {
+		/*
+		 * PLL ramp is not required if both MPU clock and NOC clock are
+		 * not sourced from periph PLL
+		 */
+		if (main_cfg->mpuclk_src != ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
+		    main_cfg->nocclk_src != ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI)
+			return 0;
+
+		/*
+		 * PLL ramp is required if MPU clock are source from periph PLL
+		 * and MPU clock is over 900MHz (as advised by HW team)
+		 */
+		if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
+		    (arria10_cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
+		     ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
+			return 1;
+
+		/*
+		 * PLL ramp is required if NOC clock are source from periph PLL
+		 * and NOC clock is over 300MHz (as advised by HW team)
+		 */
+		if (main_cfg->nocclk_src == ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI &&
+		    (arria10_cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
+		     ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
+			return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * Calculate the new PLL numerator which is based on existing DTS hand off and
+ * intended safe frequency (safe_hz). Note that PLL ramp is only modifying the
+ * numerator while maintaining denominator as denominator will influence the
+ * jitter condition. Please refer A10 HPS TRM for the jitter guide. Note final
+ * value for numerator is minus with 1 to cater our register value
+ * representation.
+ */
+static uint32_t arria10_cm_calc_safe_pll_numer(int main0periph1,
+					       struct arria10_mainpll_cfg *main_cfg,
+					       struct arria10_perpll_cfg *per_cfg,
+					       uint32_t safe_hz)
+{
+	uint32_t clk_hz = 0;
+
+	/* Check for main PLL */
+	if (main0periph1 == 0) {
+		/* Check main VCO clock source: eosc, intosc or f2s? */
+		switch (main_cfg->vco0_psrc) {
+		case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_EOSC:
+			clk_hz = eosc1_hz;
+			break;
+		case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC:
+			clk_hz = cb_intosc_hz;
+			break;
+		case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_F2S:
+			clk_hz = f2s_free_hz;
+			break;
+		default:
+			return 0;
+		}
+
+		/* Applicable if MPU clock is from main PLL */
+		if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) {
+			/* calculate the safe numer value */
+			clk_hz = (safe_hz / clk_hz) *
+				(main_cfg->mpuclk_cnt + 1) *
+				((main_cfg->mpuclk &
+				  ARRIA10_CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1) *
+				(1 + main_cfg->vco1_denom) - 1;
+		}
+		/* Reach here if MPU clk not from main PLL but NOC clk is */
+		else if (main_cfg->nocclk_src ==
+			 ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) {
+			/* calculate the safe numer value */
+			clk_hz = (safe_hz / clk_hz) *
+				(main_cfg->nocclk_cnt + 1) *
+				((main_cfg->nocclk &
+				  ARRIA10_CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1) *
+				(1 + main_cfg->vco1_denom) - 1;
+		} else {
+			clk_hz = 0;
+		}
+
+	} else if (main0periph1 == 1) {
+		/* Check periph VCO clock source: eosc, intosc, f2s, mainpll */
+		switch (per_cfg->vco0_psrc) {
+		case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_EOSC:
+			clk_hz = eosc1_hz;
+			break;
+		case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC:
+			clk_hz = cb_intosc_hz;
+			break;
+		case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_F2S:
+			clk_hz = f2s_free_hz;
+			break;
+		case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MAIN:
+			clk_hz = arria10_cm_calc_handoff_main_vco_clk_hz(
+				 main_cfg);
+			clk_hz /= main_cfg->cntr15clk_cnt;
+			break;
+		default:
+			return 0;
+		}
+		/* Applicable if MPU clock is from periph PLL */
+		if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI) {
+			/* calculate the safe numer value */
+			clk_hz = (safe_hz / clk_hz) *
+				(main_cfg->mpuclk_cnt + 1) *
+				(((main_cfg->mpuclk >>
+				  ARRIA10_CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) &
+				  ARRIA10_CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1) *
+				(1 + per_cfg->vco1_denom) - 1;
+		}
+		/* Reach here if MPU clk not from periph PLL but NOC clk is */
+		else if (main_cfg->nocclk_src ==
+			 ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI) {
+			/* calculate the safe numer value */
+			clk_hz = (safe_hz / clk_hz) *
+				(main_cfg->nocclk_cnt + 1) *
+				(((main_cfg->nocclk >>
+				  ARRIA10_CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) &
+				  ARRIA10_CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1) *
+				(1 + per_cfg->vco1_denom) - 1;
+		} else {
+			clk_hz = 0;
+		}
+	}
+
+	return clk_hz;
+}
+
+/* ramping the main PLL to final value */
+static void arria10_cm_pll_ramp_main(struct arria10_mainpll_cfg *main_cfg,
+				     struct arria10_perpll_cfg *per_cfg,
+				     uint32_t pll_ramp_main_hz)
+{
+	uint32_t clk_hz = 0;
+	uint32_t clk_incr_hz = 0;
+	uint32_t clk_final_hz = 0;
+
+	/* find out the increment value */
+	if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) {
+		clk_incr_hz = ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ;
+		clk_final_hz = arria10_cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg);
+	} else if (main_cfg->nocclk_src == ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) {
+		clk_incr_hz = ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ;
+		clk_final_hz = arria10_cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg);
+	}
+
+	/* execute the ramping here */
+	for (clk_hz = pll_ramp_main_hz + clk_incr_hz;
+	     clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
+		writel((main_cfg->vco1_denom << ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
+		       arria10_cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
+		       &arria10_clkmgr_base->main_pll_vco1);
+		__udelay(1000);
+		arria10_cm_wait_for_lock(LOCKED_MASK);
+	}
+
+	writel((main_cfg->vco1_denom << ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
+	       main_cfg->vco1_numer, &arria10_clkmgr_base->main_pll_vco1);
+
+	__udelay(1000);
+	arria10_cm_wait_for_lock(LOCKED_MASK);
+}
+
+/* ramping the periph PLL to final value */
+static void arria10_cm_pll_ramp_periph(struct arria10_mainpll_cfg *main_cfg,
+				       struct arria10_perpll_cfg *per_cfg,
+				       uint32_t pll_ramp_periph_hz)
+{
+	uint32_t clk_hz = 0;
+	uint32_t clk_incr_hz = 0;
+	uint32_t clk_final_hz = 0;
+
+	/* find out the increment value */
+	if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI) {
+		clk_incr_hz = ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ;
+		clk_final_hz = arria10_cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg);
+	} else if (main_cfg->nocclk_src == ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI) {
+		clk_incr_hz = ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ;
+		clk_final_hz = arria10_cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg);
+	}
+
+	/* execute the ramping here */
+	for (clk_hz = pll_ramp_periph_hz + clk_incr_hz;
+	     clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
+		writel((per_cfg->vco1_denom << ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+		       arria10_cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz),
+		       &arria10_clkmgr_base->per_pll_vco1);
+		__udelay(1000);
+		arria10_cm_wait_for_lock(LOCKED_MASK);
+	}
+
+	writel((per_cfg->vco1_denom << ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+	       per_cfg->vco1_numer, &arria10_clkmgr_base->per_pll_vco1);
+	__udelay(1000);
+	arria10_cm_wait_for_lock(LOCKED_MASK);
+}
+
+/*
+ * Setup clocks while making no assumptions of the
+ * previous state of the clocks.
+ *
+ * - Start by being paranoid and gate all sw managed clocks
+ * - Put all plls in bypass
+ * - Put all plls VCO registers back to reset value (bgpwr dwn).
+ * - Put peripheral and main pll src to reset value to avoid glitch.
+ * - Delay 5 us.
+ * - Deassert bg pwr dn and set numerator and denominator
+ * - Start 7 us timer.
+ * - set internal dividers
+ * - Wait for 7 us timer.
+ * - Enable plls
+ * - Set external dividers while plls are locking
+ * - Wait for pll lock
+ * - Assert/deassert outreset all.
+ * - Take all pll's out of bypass
+ * - Clear safe mode
+ * - set source main and peripheral clocks
+ * - Ungate clocks
+ */
+static int arria10_cm_full_cfg(struct arria10_mainpll_cfg *main_cfg,
+			       struct arria10_perpll_cfg *per_cfg)
+{
+	uint32_t pll_ramp_main_hz = 0;
+	uint32_t pll_ramp_periph_hz = 0;
+
+	/* gate off all mainpll clock excpet HW managed clock */
+	writel(ARRIA10_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
+	       ARRIA10_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
+	       &arria10_clkmgr_base->main_pll_enr);
+
+	/* now we can gate off the rest of the peripheral clocks */
+	writel(0, &arria10_clkmgr_base->per_pll_en);
+
+	/* Put all plls in external bypass */
+	writel(ARRIA10_CLKMGR_MAINPLL_BYPASS_RESET,
+	       &arria10_clkmgr_base->main_pll_bypasss);
+	writel(ARRIA10_CLKMGR_PERPLL_BYPASS_RESET,
+	       &arria10_clkmgr_base->per_pll_bypasss);
+
+	/*
+	 * Put all plls VCO registers back to reset value.
+	 * Some code might have messed with them. At same time set the
+	 * desired clock source
+	 */
+	writel(ARRIA10_CLKMGR_MAINPLL_VCO0_RESET |
+	       ARRIA10_CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK |
+	       (main_cfg->vco0_psrc << ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_LSB),
+	       &arria10_clkmgr_base->main_pll_vco0);
+
+	writel(ARRIA10_CLKMGR_PERPLL_VCO0_RESET |
+	       ARRIA10_CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK |
+	       (per_cfg->vco0_psrc << ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_LSB),
+	       &arria10_clkmgr_base->per_pll_vco0);
+
+	writel(ARRIA10_CLKMGR_MAINPLL_VCO1_RESET,
+	       &arria10_clkmgr_base->main_pll_vco1);
+	writel(ARRIA10_CLKMGR_PERPLL_VCO1_RESET,
+	       &arria10_clkmgr_base->per_pll_vco1);
+
+	/* clear the interrupt register status register */
+	writel(ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
+	       ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK |
+	       ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK |
+	       ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
+	       ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
+	       ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK |
+	       ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK |
+	       ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK,
+	       &arria10_clkmgr_base->intr);
+
+	/* Program VCO “Numerator” and “Denominator” for main PLL */
+	if (arria10_cm_is_pll_ramp_required(0, main_cfg, per_cfg)) {
+		/* set main PLL to safe starting threshold frequency */
+		if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN)
+			pll_ramp_main_hz = ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ;
+		else if (main_cfg->nocclk_src == ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN)
+			pll_ramp_main_hz = ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
+
+		writel((main_cfg->vco1_denom << ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
+		       arria10_cm_calc_safe_pll_numer(0, main_cfg, per_cfg,
+						      pll_ramp_main_hz),
+		       &arria10_clkmgr_base->main_pll_vco1);
+	} else {
+		writel((main_cfg->vco1_denom << ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
+		       main_cfg->vco1_numer,
+		       &arria10_clkmgr_base->main_pll_vco1);
+	}
+
+	/* Program VCO “Numerator” and “Denominator” for periph PLL */
+	if (arria10_cm_is_pll_ramp_required(1, main_cfg, per_cfg)) {
+		/* set periph PLL to safe starting threshold frequency */
+		if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI)
+			pll_ramp_periph_hz = ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ;
+		else if (main_cfg->nocclk_src == ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI)
+			pll_ramp_periph_hz = ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
+
+		writel((per_cfg->vco1_denom << ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+		       arria10_cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
+						      pll_ramp_periph_hz),
+		       &arria10_clkmgr_base->per_pll_vco1);
+	} else {
+		writel((per_cfg->vco1_denom << ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+		       per_cfg->vco1_numer, &arria10_clkmgr_base->per_pll_vco1);
+	}
+
+	/* Wait for at least 5 us */
+	__udelay(5);
+
+	/* Now deassert BGPWRDN and PWRDN */
+	clrbits_le32(&arria10_clkmgr_base->main_pll_vco0,
+		     ARRIA10_CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK |
+		     ARRIA10_CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK);
+	clrbits_le32(&arria10_clkmgr_base->per_pll_vco0,
+		     ARRIA10_CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK |
+		     ARRIA10_CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
+
+	/* Wait for at least 7 us */
+	__udelay(7);
+
+	/* enable the VCO and disable the external regulator to PLL */
+	writel((readl(&arria10_clkmgr_base->main_pll_vco0) &
+		~ARRIA10_CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) |
+	       ARRIA10_CLKMGR_MAINPLL_VCO0_EN_SET_MSK,
+	       &arria10_clkmgr_base->main_pll_vco0);
+	writel((readl(&arria10_clkmgr_base->per_pll_vco0) &
+		~ARRIA10_CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) |
+	       ARRIA10_CLKMGR_PERPLL_VCO0_EN_SET_MSK,
+	       &arria10_clkmgr_base->per_pll_vco0);
+
+	/* setup all the main PLL counter and clock source */
+	writel(main_cfg->nocclk,
+	       ARRIA10_CLKMGR_ADDR + ARRIA10_CLKMGR_MAINPLL_NOC_CLK_OFFSET);
+	writel(main_cfg->mpuclk,
+	       ARRIA10_CLKMGR_ADDR + ARRIA10_CLKMGR_ALTERAGRP_MPU_CLK_OFFSET);
+
+	/* main_emaca_clk divider */
+	writel(main_cfg->cntr2clk_cnt, &arria10_clkmgr_base->main_pll_cntr2clk);
+	/* main_emacb_clk divider */
+	writel(main_cfg->cntr3clk_cnt, &arria10_clkmgr_base->main_pll_cntr3clk);
+	/* main_emac_ptp_clk divider */
+	writel(main_cfg->cntr4clk_cnt, &arria10_clkmgr_base->main_pll_cntr4clk);
+	/* main_gpio_db_clk divider */
+	writel(main_cfg->cntr5clk_cnt, &arria10_clkmgr_base->main_pll_cntr5clk);
+	/* main_sdmmc_clk divider */
+	writel(main_cfg->cntr6clk_cnt, &arria10_clkmgr_base->main_pll_cntr6clk);
+	/* main_s2f_user0_clk divider */
+	writel(main_cfg->cntr7clk_cnt |
+	       (main_cfg->cntr7clk_src << ARRIA10_CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB),
+	       &arria10_clkmgr_base->main_pll_cntr7clk);
+	/* main_s2f_user1_clk divider */
+	writel(main_cfg->cntr8clk_cnt, &arria10_clkmgr_base->main_pll_cntr8clk);
+	/* main_hmc_pll_clk divider */
+	writel(main_cfg->cntr9clk_cnt |
+	       (main_cfg->cntr9clk_src << ARRIA10_CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB),
+	       &arria10_clkmgr_base->main_pll_cntr9clk);
+	/* main_periph_ref_clk divider */
+	writel(main_cfg->cntr15clk_cnt,	&arria10_clkmgr_base->main_pll_cntr15clk);
+
+	/* setup all the peripheral PLL counter and clock source */
+	/* peri_emaca_clk divider */
+	writel(per_cfg->cntr2clk_cnt |
+	       (per_cfg->cntr2clk_src << ARRIA10_CLKMGR_PERPLL_CNTR2CLK_SRC_LSB),
+	       &arria10_clkmgr_base->per_pll_cntr2clk);
+	/* peri_emacb_clk divider */
+	writel(per_cfg->cntr3clk_cnt |
+	       (per_cfg->cntr3clk_src << ARRIA10_CLKMGR_PERPLL_CNTR3CLK_SRC_LSB),
+	       &arria10_clkmgr_base->per_pll_cntr3clk);
+	/* peri_emac_ptp_clk divider */
+	writel(per_cfg->cntr4clk_cnt |
+	       (per_cfg->cntr4clk_src << ARRIA10_CLKMGR_PERPLL_CNTR4CLK_SRC_LSB),
+	       &arria10_clkmgr_base->per_pll_cntr4clk);
+	/* peri_gpio_db_clk divider */
+	writel(per_cfg->cntr5clk_cnt |
+	       (per_cfg->cntr5clk_src << ARRIA10_CLKMGR_PERPLL_CNTR5CLK_SRC_LSB),
+	       &arria10_clkmgr_base->per_pll_cntr5clk);
+	/* peri_sdmmc_clk divider */
+	writel(per_cfg->cntr6clk_cnt |
+	       (per_cfg->cntr6clk_src << ARRIA10_CLKMGR_PERPLL_CNTR6CLK_SRC_LSB),
+	       &arria10_clkmgr_base->per_pll_cntr6clk);
+	/* peri_s2f_user0_clk divider */
+	writel(per_cfg->cntr7clk_cnt, &arria10_clkmgr_base->per_pll_cntr7clk);
+	/* peri_s2f_user1_clk divider */
+	writel(per_cfg->cntr8clk_cnt |
+	       (per_cfg->cntr8clk_src << ARRIA10_CLKMGR_PERPLL_CNTR8CLK_SRC_LSB),
+	       &arria10_clkmgr_base->per_pll_cntr8clk);
+	/* peri_hmc_pll_clk divider */
+	writel(per_cfg->cntr9clk_cnt, &arria10_clkmgr_base->per_pll_cntr9clk);
+
+	/* setup all the external PLL counter */
+	/* mpu wrapper / external divider */
+	writel(main_cfg->mpuclk_cnt |
+	       (main_cfg->mpuclk_src << ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_LSB),
+	       &arria10_clkmgr_base->main_pll_mpuclk);
+	/* NOC wrapper / external divider */
+	writel(main_cfg->nocclk_cnt |
+	       (main_cfg->nocclk_src << ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_LSB),
+	       &arria10_clkmgr_base->main_pll_nocclk);
+	/* NOC subclock divider such as l4 */
+	writel(main_cfg->nocdiv_l4mainclk |
+	       (main_cfg->nocdiv_l4mpclk << ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) |
+	       (main_cfg->nocdiv_l4spclk << ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB) |
+	       (main_cfg->nocdiv_csatclk << ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB) |
+	       (main_cfg->nocdiv_cstraceclk << ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) |
+	       (main_cfg->nocdiv_cspdbgclk << ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB),
+	       &arria10_clkmgr_base->main_pll_nocdiv);
+	/* gpio_db external divider */
+	writel(per_cfg->gpiodiv_gpiodbclk, &arria10_clkmgr_base->per_pll_gpiodiv);
+
+	/* setup the EMAC clock mux select */
+	writel((per_cfg->emacctl_emac0sel < ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB) |
+	       (per_cfg->emacctl_emac1sel << ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) |
+	       (per_cfg->emacctl_emac2sel << ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB),
+	       &arria10_clkmgr_base->per_pll_emacctl);
+
+	/* at this stage, check for PLL lock status */
+	arria10_cm_wait_for_lock(LOCKED_MASK);
+
+	/*
+	 * after locking, but before taking out of bypass,
+	 * assert/deassert outresetall
+	 */
+
+	/* assert mainpll outresetall */
+	setbits_le32(&arria10_clkmgr_base->main_pll_vco0,
+		     ARRIA10_CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
+	/* assert perpll outresetall */
+	setbits_le32(&arria10_clkmgr_base->per_pll_vco0,
+		     ARRIA10_CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
+	/* de-assert mainpll outresetall */
+	clrbits_le32(&arria10_clkmgr_base->main_pll_vco0,
+		     ARRIA10_CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
+	/* de-assert perpll outresetall */
+	clrbits_le32(&arria10_clkmgr_base->per_pll_vco0,
+		     ARRIA10_CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
+
+	/*
+	 * Take all PLLs out of bypass when boot mode is cleared.
+	 * release mainpll from bypass
+	 */
+	writel(ARRIA10_CLKMGR_MAINPLL_BYPASS_RESET,
+	       &arria10_clkmgr_base->main_pll_bypassr);
+	/* wait till Clock Manager is not busy */
+	arria10_cm_wait4fsm();
+
+	/* release perpll from bypass */
+	writel(ARRIA10_CLKMGR_PERPLL_BYPASS_RESET,
+	       &arria10_clkmgr_base->per_pll_bypassr);
+	/* wait till Clock Manager is not busy */
+	arria10_cm_wait4fsm();
+
+	/* clear boot mode */
+	clrbits_le32(&arria10_clkmgr_base->ctrl,
+		     ARRIA10_CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK);
+	/* wait till Clock Manager is not busy */
+	arria10_cm_wait4fsm();
+
+	/* At here, we need to ramp to final value if needed */
+	if (pll_ramp_main_hz != 0)
+		arria10_cm_pll_ramp_main(main_cfg, per_cfg, pll_ramp_main_hz);
+	if (pll_ramp_periph_hz != 0)
+		arria10_cm_pll_ramp_periph(main_cfg, per_cfg, pll_ramp_periph_hz);
+
+	/* Now ungate non-hw-managed clocks */
+	writel(ARRIA10_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
+	       ARRIA10_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
+	       &arria10_clkmgr_base->main_pll_ens);
+	writel(ARRIA10_CLKMGR_PERPLL_EN_RESET,
+	       &arria10_clkmgr_base->per_pll_ens);
+
+	/*
+	 * Clear the loss lock and slip bits as they might set during
+	 * clock reconfiguration
+	 */
+	writel(ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
+	       ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK |
+	       ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK |
+	       ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
+	       ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
+	       ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK,
+	       &arria10_clkmgr_base->intr);
+
+	return 0;
+}
+
+int arria10_cm_basic_init(struct arria10_mainpll_cfg *mainpll,
+			  struct arria10_perpll_cfg *perpll)
+{
+	return arria10_cm_full_cfg(mainpll, perpll);
+}
+
+void arria10_cm_use_intosc(void)
+{
+	setbits_le32(&arria10_clkmgr_base->ctrl,
+		     ARRIA10_CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK);
+}
diff --git a/arch/arm/mach-socfpga/arria10-generic.c b/arch/arm/mach-socfpga/arria10-generic.c
new file mode 100644
index 0000000000..b8129eaf23
--- /dev/null
+++ b/arch/arm/mach-socfpga/arria10-generic.c
@@ -0,0 +1,85 @@
+#include <common.h>
+#include <io.h>
+#include <init.h>
+#include <restart.h>
+#include <mach/generic.h>
+#include <mach/arria10-reset-manager.h>
+#include <mach/arria10-system-manager.h>
+#include <mach/arria10-regs.h>
+
+/* Some initialization for the EMAC */
+static void arria10_init_emac(void)
+{
+	uint32_t rst, val;
+
+	/* No need for this without network support, e.g. xloader build */
+	if (!IS_ENABLED(CONFIG_NET))
+		return;
+
+	rst = readl(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST);
+	rst |= ARRIA10_RSTMGR_PER0MODRST_EMAC0 |
+	       ARRIA10_RSTMGR_PER0MODRST_EMAC1 |
+	       ARRIA10_RSTMGR_PER0MODRST_EMAC2;
+
+	writel(rst, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST);
+	val = readl(ARRIA10_SYSMGR_EMAC0);
+	val &= ~(ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_MASK);
+	val |= ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+	writel(val, ARRIA10_SYSMGR_EMAC0);
+
+	val = readl(ARRIA10_SYSMGR_EMAC1);
+	val &= ~(ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_MASK);
+	val |= ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+	writel(val, ARRIA10_SYSMGR_EMAC1);
+
+	val = readl(ARRIA10_SYSMGR_EMAC2);
+	val &= ~(ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_MASK);
+	val |= ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+	writel(val, ARRIA10_SYSMGR_EMAC2);
+
+	val = readl(ARRIA10_SYSMGR_FPGAINTF_EN_3);
+	val &= ~(ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC0 |
+		 ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC0_SW |
+		 ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC1 |
+		 ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC1_SW |
+		 ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC2 |
+		 ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC2_SW);
+
+	rst = readl(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST);
+	rst &= ~(ARRIA10_RSTMGR_PER0MODRST_EMAC0 |
+		 ARRIA10_RSTMGR_PER0MODRST_EMAC1 |
+		 ARRIA10_RSTMGR_PER0MODRST_EMAC2);
+	writel(rst, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST);
+}
+
+/* Write the reset manager register to cause reset */
+static void __noreturn arria10_restart_soc(struct restart_handler *rst)
+{
+	/* request a warm reset */
+	writel(ARRIA10_RSTMGR_CTL_SWWARMRSTREQ,
+	       ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_CTRL);
+	/*
+	 * infinite loop here as watchdog will trigger and reset
+	 * the processor
+	 */
+	hang();
+}
+
+static int arria10_generic_init(void)
+{
+	barebox_set_model("SoCFPGA Arria10");
+
+	pr_debug("Setting SDMMC phase shifts for Arria10\n");
+	writel(ARRIA10_SYSMGR_SDMMC_DRVSEL(3) |
+	       ARRIA10_SYSMGR_SDMMC_SMPLSEL(0),
+	       ARRIA10_SYSMGR_SDMMC);
+
+	pr_debug("Initialize EMACs\n");
+	arria10_init_emac();
+
+	pr_debug("Register restart handler\n");
+	restart_handler_register_fn(arria10_restart_soc);
+
+	return 0;
+}
+postcore_initcall(arria10_generic_init);
diff --git a/arch/arm/mach-socfpga/arria10-init.c b/arch/arm/mach-socfpga/arria10-init.c
new file mode 100644
index 0000000000..07256da1db
--- /dev/null
+++ b/arch/arm/mach-socfpga/arria10-init.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <debug_ll.h>
+#include <mach/arria10-regs.h>
+#include <mach/arria10-clock-manager.h>
+#include <mach/arria10-pinmux.h>
+#include <mach/arria10-reset-manager.h>
+#include <mach/arria10-system-manager.h>
+#include <mach/generic.h>
+#include <asm/io.h>
+#include <asm/cache-l2x0.h>
+#include <asm/system.h>
+
+#define L310_AUX_CTRL_EARLY_BRESP		BIT(30)	/* R2P0+ */
+#define L310_AUX_CTRL_NS_LOCKDOWN		BIT(26)
+#define L310_AUX_CTRL_FULL_LINE_ZERO		BIT(0)	/* R2P0+ */
+
+static inline void set_auxcr(unsigned int val)
+{
+	asm volatile("mcr p15, 0, %0, c1, c0, 1	@ set AUXCR"
+		     : : "r" (val));
+	isb();
+}
+
+static inline unsigned int get_auxcr(void)
+{
+	unsigned int val;
+
+	asm("mrc p15, 0, %0, c1, c0, 1	@ get AUXCR" : "=r" (val));
+	return val;
+}
+
+static void l2c310_disable(void __iomem *base)
+{
+	u32 aux;
+	int ways = 8;
+
+	aux = readl(base + L2X0_AUX_CTRL);
+
+	/*
+	 * If full-line-of-zeros is enabled, we must first disable it in the
+	 * Cortex-A9 auxiliary control register before disabling the L2 cache.
+	 */
+	if (aux & L310_AUX_CTRL_FULL_LINE_ZERO)
+		set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1)));
+
+	/* flush all ways */
+	writel((1 << ways) - 1, base + L2X0_INV_WAY);
+
+	while (readl(base + L2X0_INV_WAY) & ways)
+		;
+
+	/* sync */
+	writel(0, base + L2X0_CACHE_SYNC);
+
+	/* disable */
+	writel(0, base + L2X0_CTRL);
+	dsb();
+}
+
+static void arria10_initialize_security_policies(void)
+{
+	void __iomem *l2x0_base = (void __iomem *) 0xfffff000;
+
+	/* BootROM leaves the L2X0 in a weird state. Always disable L2X0 for now. */
+	l2c310_disable(l2x0_base);
+
+	/* Put OCRAM in non-secure */
+	writel(0x003f0000, ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION0);
+	writel(0x1, ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN);
+
+	/* Put DDR in non-secure */
+	writel(0xffff0000, ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION0);
+	writel(0x1, ARRIA10_NOC_FW_DDR_L3_DDR_SCR_EN);
+
+	/* Enable priviledge and non priviledge access to L4 peripherals */
+	writel(0xffffffff, ARRIA10_NOC_L4_PRIV_L4_PRIV_L4_PRIV);
+
+	/* Enable secure and non secure transaction to bridges */
+	writel(0xffffffff, ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_LWSOC2FPGA);
+	writel(0xffffffff, ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_SOC2FPGA);
+
+	/* allow non-secure and secure transaction from/to all peripherals */
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_NAND_REG);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_NAND_DATA);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_QSPI_DATA);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_USB0_REG);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_USB1_REG);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SPIM0);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SPIM1);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SPIS0);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SPIS1);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_EMAC0);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_EMAC1);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_EMAC2);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_EMAC3);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_QSPI);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SDMMC);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_GPIO0);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_GPIO1);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_GPIO2);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_I2C0);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_I2C1);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_I2C2);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_I2C3);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_I2C4);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SPTIMER0);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SPTIMER1);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_UART0);
+	writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_UART1);
+
+	/* Return error instead of random data */
+	writel(0x1, ARRIA10_NOC_FW_DDR_L3_DDR_SCR_GLOBAL);
+}
+
+static void arria10_mask_ecc_errors(void)
+{
+	writel(0x0007FFFF, ARRIA10_SYSMGR_ADDR + 0x94);
+}
+
+/*
+ * First C function to initialize the critical hardware early
+ */
+void arria10_init(struct arria10_mainpll_cfg *mainpll,
+		  struct arria10_perpll_cfg *perpll,
+		  uint32_t *pinmux)
+{
+	int i;
+
+	arria10_cm_use_intosc();
+
+	arria10_initialize_security_policies();
+
+	arria10_mask_ecc_errors();
+
+	/*
+	 * Configure the L2 controller to make SDRAM start at 0.
+	 * Set address filtering start to 0x0 (Bits [31:20]),
+	 * Enable address filtering (Bit[0])
+	 */
+	writel(0x00000001, ARRIA10_MPUL2_ADRFLTR_START);
+	writel(0x00000002, ARRIA10_SYSMGR_NOC_ADDR_REMAP_VALUE);
+
+	arria10_reset_peripherals();
+
+	/* timer init */
+	writel(0xffffffff, ARRIA10_OSC1TIMER0_ADDR);
+	writel(0xffffffff, ARRIA10_OSC1TIMER0_ADDR + 0x4);
+	writel(0x00000003, ARRIA10_OSC1TIMER0_ADDR + 0x8);
+
+	/* configuring the clock based on handoff */
+	arria10_cm_basic_init(mainpll, perpll);
+
+	/* dedicated pins */
+	for (i = arria10_pinmux_dedicated_io_4;
+	     i <= arria10_pinmux_dedicated_io_17; i++)
+		writel(pinmux[i], ARRIA10_PINMUX_DEDICATED_IO_4_ADDR +
+		       (i - arria10_pinmux_dedicated_io_4) * sizeof(uint32_t));
+
+	for (i = arria10_pincfg_dedicated_io_bank;
+	     i <= arria10_pincfg_dedicated_io_17; i++)
+		writel(pinmux[i], ARRIA10_PINCFG_DEDICATED_IO_BANK_ADDR +
+		       (i - arria10_pincfg_dedicated_io_bank) * sizeof(uint32_t));
+
+	/* deassert peripheral resets */
+	arria10_reset_deassert_dedicated_peripherals();
+
+	/* wait for fpga_usermode */
+	while ((readl(0xffd03080) & 0x6) == 0);
+
+	/* shared pins */
+	for (i = arria10_pinmux_shared_io_q1_1;
+	     i <= arria10_pinmux_shared_io_q4_12; i++)
+		writel(pinmux[i], ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR +
+		       (i - arria10_pinmux_shared_io_q1_1) * sizeof(uint32_t));
+
+	arria10_reset_deassert_shared_peripherals();
+
+	/* usefpga: select source for signals: hps or fpga */
+	for (i = arria10_pinmux_rgmii0_usefpga;
+	     i < arria10_pinmux_max; i++)
+		writel(pinmux[i], ARRIA10_PINMUX_FPGA_INTERFACE_ADDR +
+		       (i - arria10_pinmux_rgmii0_usefpga) * sizeof(uint32_t));
+
+	arria10_reset_deassert_fpga_peripherals();
+
+	INIT_LL();
+}
diff --git a/arch/arm/mach-socfpga/arria10-reset-manager.c b/arch/arm/mach-socfpga/arria10-reset-manager.c
new file mode 100644
index 0000000000..a7e4bd603e
--- /dev/null
+++ b/arch/arm/mach-socfpga/arria10-reset-manager.c
@@ -0,0 +1,398 @@
+/*
+ * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <io.h>
+#include <mach/arria10-pinmux.h>
+#include <mach/arria10-regs.h>
+#include <mach/arria10-reset-manager.h>
+#include <mach/arria10-system-manager.h>
+
+void arria10_reset_peripherals(void)
+{
+	unsigned mask_ecc_ocp = ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP |
+		ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP |
+		ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP |
+		ARRIA10_RSTMGR_PER0MODRST_USB0OCP |
+		ARRIA10_RSTMGR_PER0MODRST_USB1OCP |
+		ARRIA10_RSTMGR_PER0MODRST_NANDOCP |
+		ARRIA10_RSTMGR_PER0MODRST_QSPIOCP |
+		ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP;
+
+	/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
+	writel(0xffffffff, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST);
+	setbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST,
+		     ~mask_ecc_ocp);
+
+	/* Finally disable the ECC_OCP */
+	setbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST,
+		     mask_ecc_ocp);
+}
+
+void arria10_reset_deassert_dedicated_peripherals(void)
+{
+	uint32_t mask;
+
+	mask = ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP |
+	       ARRIA10_RSTMGR_PER0MODRST_QSPIOCP |
+	       ARRIA10_RSTMGR_PER0MODRST_NANDOCP |
+	       ARRIA10_RSTMGR_PER0MODRST_DMAOCP;
+
+	/* enable ECC OCP first */
+	clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask);
+
+	mask = ARRIA10_RSTMGR_PER0MODRST_SDMMC |
+	       ARRIA10_RSTMGR_PER0MODRST_QSPI |
+	       ARRIA10_RSTMGR_PER0MODRST_NAND |
+	       ARRIA10_RSTMGR_PER0MODRST_DMA;
+
+	clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask);
+
+	mask = ARRIA10_RSTMGR_PER1MODRST_L4SYSTIMER0 |
+	       ARRIA10_RSTMGR_PER1MODRST_UART1 |
+	       ARRIA10_RSTMGR_PER1MODRST_UART0;
+
+	clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST, mask);
+
+	clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST,
+		     ARRIA10_RSTMGR_OCP_MASK);
+	mask = ARRIA10_RSTMGR_PER0MODRST_EMAC1 |
+		ARRIA10_RSTMGR_PER0MODRST_EMAC2 |
+		ARRIA10_RSTMGR_PER0MODRST_EMAC0 |
+		ARRIA10_RSTMGR_PER0MODRST_SPIS0 |
+		ARRIA10_RSTMGR_PER0MODRST_SPIM0;
+	clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask);
+
+	mask = ARRIA10_RSTMGR_PER1MODRST_I2C3 |
+	       ARRIA10_RSTMGR_PER1MODRST_I2C4 |
+	       ARRIA10_RSTMGR_PER1MODRST_I2C2 |
+	       ARRIA10_RSTMGR_PER1MODRST_UART1 |
+	       ARRIA10_RSTMGR_PER1MODRST_GPIO2;
+	clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST, mask);
+}
+
+static const uint32_t per0fpgamasks[] = {
+	ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP | ARRIA10_RSTMGR_PER0MODRST_EMAC0,
+	ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP | ARRIA10_RSTMGR_PER0MODRST_EMAC1,
+	ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP | ARRIA10_RSTMGR_PER0MODRST_EMAC2,
+	0, /* i2c0 per0mod */
+	0, /* i2c1 per0mod */
+	0, /* i2c0_emac */
+	0, /* i2c1_emac */
+	0, /* i2c2_emac */
+	ARRIA10_RSTMGR_PER0MODRST_NANDOCP | ARRIA10_RSTMGR_PER0MODRST_NAND,
+	ARRIA10_RSTMGR_PER0MODRST_QSPIOCP | ARRIA10_RSTMGR_PER0MODRST_QSPI,
+	ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP | ARRIA10_RSTMGR_PER0MODRST_SDMMC,
+	ARRIA10_RSTMGR_PER0MODRST_SPIM0,
+	ARRIA10_RSTMGR_PER0MODRST_SPIM1,
+	ARRIA10_RSTMGR_PER0MODRST_SPIS0,
+	ARRIA10_RSTMGR_PER0MODRST_SPIS1,
+	0, /* uart0 per0mod */
+	0, /* uart1 per0mod */
+};
+
+static const uint32_t per1fpgamasks[] = {
+	0, /* emac0 per0mod */
+	0, /* emac1 per0mod */
+	0, /* emac2 per0mod */
+	ARRIA10_RSTMGR_PER1MODRST_I2C0,
+	ARRIA10_RSTMGR_PER1MODRST_I2C1,
+	ARRIA10_RSTMGR_PER1MODRST_I2C2,
+	ARRIA10_RSTMGR_PER1MODRST_I2C3,
+	ARRIA10_RSTMGR_PER1MODRST_I2C4,
+	0, /* nand per0mod */
+	0, /* qspi per0mod */
+	0, /* sdmmc per0mod */
+	0, /* spim0 per0mod */
+	0, /* spim1 per0mod */
+	0, /* spis0 per0mod */
+	0, /* spis1 per0mod */
+	ARRIA10_RSTMGR_PER1MODRST_UART0,
+	ARRIA10_RSTMGR_PER1MODRST_UART1,
+};
+
+void arria10_reset_deassert_fpga_peripherals(void)
+{
+	uint32_t mask0 = 0;
+	uint32_t mask1 = 0;
+	uint32_t fpga_pinux_addr = ARRIA10_PINMUX_FPGA_INTERFACE_ADDR;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(per1fpgamasks); i++) {
+		if (readl(fpga_pinux_addr)) {
+			mask0 |= per0fpgamasks[i];
+			mask1 |= per1fpgamasks[i];
+		}
+		fpga_pinux_addr += sizeof(uint32_t);
+	}
+
+	clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST,
+		     mask0 & ARRIA10_RSTMGR_OCP_MASK);
+	clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask0);
+	clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST, mask1);
+}
+
+void arria10_reset_deassert_shared_peripherals_q1(uint32_t *mask0,
+						  uint32_t *mask1)
+{
+	uint32_t pinmux_addr = ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR;
+	int q1;
+
+	for (q1 = 1; q1 <= 12; q1++, pinmux_addr += sizeof(uint32_t)) {
+		switch (readl(pinmux_addr)) {
+		case ARRIA10_PINMUX_SHARED_IO_Q1_GPIO:
+			*mask1 |= ARRIA10_RSTMGR_PER1MODRST_GPIO0;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q1_NAND:
+			*mask0 |= ARRIA10_RSTMGR_PER0MODRST_NANDOCP|
+				ARRIA10_RSTMGR_PER0MODRST_NAND;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q1_UART:
+			if ((q1 >= 1) && (q1 <= 4))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART0;
+			else if ((q1 >= 5) && (q1 <= 8))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART1;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q1_QSPI:
+			if ((q1 >= 5) && (q1 <= 6))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_QSPIOCP |
+					  ARRIA10_RSTMGR_PER0MODRST_QSPI;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q1_USB:
+			*mask0 |= ARRIA10_RSTMGR_PER0MODRST_USB0OCP |
+			    ARRIA10_RSTMGR_PER0MODRST_USB0;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q1_SDMMC:
+			if ((q1 >= 1) && (q1 <= 10))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP |
+					  ARRIA10_RSTMGR_PER0MODRST_SDMMC;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q1_SPIM:
+			if ((q1 == 1) || ((q1 >= 5) && (q1 <= 8)))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIM0;
+			else if ((q1 == 2) || ((q1 >= 9) && (q1 <= 12)))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIM1;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q1_SPIS:
+			if ((q1 >= 1) && (q1 <= 4))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS0;
+			else if ((q1 >= 9) && (q1 <= 12))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS1;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q1_EMAC:
+			if ((q1 == 7) || (q1 == 8))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP |
+					  ARRIA10_RSTMGR_PER0MODRST_EMAC2;
+			else if ((q1 == 9) || (q1 == 10))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP |
+					  ARRIA10_RSTMGR_PER0MODRST_EMAC1;
+			else if ((q1 == 11) || (1 == 12))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP |
+					  ARRIA10_RSTMGR_PER0MODRST_EMAC0;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q1_I2C:
+			if ((q1 == 3) || (q1 == 4))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C1;
+			else if ((q1 == 5) || (q1 == 6))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C0;
+			else if ((q1 == 7) || (q1 == 8))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C4;
+			else if ((q1 == 9) || (q1 == 10))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C3;
+			else if ((q1 == 11) || (q1 == 12))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C2;
+			break;
+		}
+	}
+}
+
+void arria10_reset_deassert_shared_peripherals_q2(uint32_t *mask0,
+						  uint32_t *mask1)
+{
+	uint32_t pinmux_addr = ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR;
+	int q2;
+
+	for (q2 = 1; q2 <= 12; q2++, pinmux_addr += sizeof(uint32_t)) {
+		switch (readl(pinmux_addr)) {
+		case ARRIA10_PINMUX_SHARED_IO_Q2_GPIO:
+			*mask1 |= ARRIA10_RSTMGR_PER1MODRST_GPIO0;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q2_NAND:
+			if ((q2 != 4) && (q2 != 5))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_NANDOCP |
+					  ARRIA10_RSTMGR_PER0MODRST_NAND;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q2_UART:
+			if ((q2 >= 9) && (q2 <= 12))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART0;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q2_USB:
+			*mask0 |= ARRIA10_RSTMGR_PER0MODRST_USB1OCP |
+				  ARRIA10_RSTMGR_PER0MODRST_USB1;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q2_EMAC:
+			*mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP |
+				  ARRIA10_RSTMGR_PER0MODRST_EMAC0;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q2_SPIM:
+			if ((q2 >= 8) && (q2 <= 12))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIM1;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q2_SPIS:
+			if ((q2 >= 9) && (q2 <= 12))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS0;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q2_I2C:
+			if ((q2 == 9) || (q2 == 10))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C1;
+			else if ((q2 == 11) || (q2 == 12))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C0;
+			break;
+		}
+	}
+}
+
+void arria10_reset_deassert_shared_peripherals_q3(uint32_t *mask0,
+						  uint32_t *mask1)
+{
+	uint32_t pinmux_addr = ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR;
+	int q3;
+
+	for (q3 = 1; q3 <= 12; q3++, pinmux_addr += sizeof(uint32_t)) {
+		switch (readl(pinmux_addr)) {
+		case ARRIA10_PINMUX_SHARED_IO_Q3_GPIO:
+			*mask1 |= ARRIA10_RSTMGR_PER1MODRST_GPIO1;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q3_NAND:
+			*mask0 |= ARRIA10_RSTMGR_PER0MODRST_NANDOCP |
+				  ARRIA10_RSTMGR_PER0MODRST_NAND;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q3_UART:
+			if ((q3 >= 1) && (q3 <= 4))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART0;
+			else if ((q3 >= 5) && (q3 <= 8))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART1;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q3_EMAC1:
+			*mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP |
+				  ARRIA10_RSTMGR_PER0MODRST_EMAC1;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q3_SPIM:
+			if ((q3 >= 1) && (q3 <= 5))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIM1;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q3_SPIS:
+			if ((q3 >= 5) && (q3 <= 8))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS1;
+			else if ((q3 >= 9) && (q3 <= 12))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS0;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q3_EMAC0:
+			if ((q3 == 9) || (q3 == 10))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP |
+					  ARRIA10_RSTMGR_PER0MODRST_EMAC2;
+			else if ((q3 == 11) || (q3 == 12))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP |
+					  ARRIA10_RSTMGR_PER0MODRST_EMAC0;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q3_I2C:
+			if ((q3 == 7) || (q3 == 8))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C1;
+			else if ((q3 == 3) || (q3 == 4))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C0;
+			else if ((q3 == 9) || (q3 == 10))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C4;
+			else if ((q3 == 11) || (q3 == 12))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C2;
+			break;
+		}
+	}
+}
+
+void arria10_reset_deassert_shared_peripherals_q4(uint32_t *mask0, uint32_t *mask1)
+{
+	uint32_t pinmux_addr = ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR;
+	int q4;
+
+	for (q4 = 1; q4 <= 12; q4++, pinmux_addr += sizeof(uint32_t)) {
+		switch (readl(pinmux_addr)) {
+		case ARRIA10_PINMUX_SHARED_IO_Q4_GPIO:
+			*mask1 |= ARRIA10_RSTMGR_PER1MODRST_GPIO1;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q4_NAND:
+			if (q4 != 4)
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_NANDOCP |
+					  ARRIA10_RSTMGR_PER0MODRST_NAND;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q4_UART:
+			if ((q4 >= 3) && (q4 <= 6))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART1;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q4_QSPI:
+			if ((q4 == 5) || (q4 == 6))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_QSPIOCP |
+					  ARRIA10_RSTMGR_PER0MODRST_QSPI;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q4_EMAC1:
+			*mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP |
+				  ARRIA10_RSTMGR_PER0MODRST_EMAC2;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q4_SDMMC:
+			if ((q4 >= 1) && (q4 <= 6))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP |
+					  ARRIA10_RSTMGR_PER0MODRST_SDMMC;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q4_SPIM:
+			if ((q4 >= 6) && (q4 <= 12))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIM0;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q4_SPIS:
+			if ((q4 >= 9) && (q4 <= 12))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS1;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q4_EMAC0:
+			if ((q4 == 7) || (q4 == 8))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP |
+					  ARRIA10_RSTMGR_PER0MODRST_EMAC1;
+			else if ((q4 == 11) || (q4 == 12))
+				*mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP |
+					  ARRIA10_RSTMGR_PER0MODRST_EMAC0;
+			break;
+		case ARRIA10_PINMUX_SHARED_IO_Q4_I2C:
+			if ((q4 == 1) || (q4 == 2))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C1;
+			else if ((q4 == 7) || (q4 == 8))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C3;
+			else if ((q4 == 9) || (q4 == 10))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C4;
+			else if ((q4 == 11) || (q4 == 12))
+				*mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C2;
+			break;
+		}
+	}
+}
+
+void arria10_reset_deassert_shared_peripherals(void)
+{
+	uint32_t mask0 = 0;
+	uint32_t mask1 = 0;
+
+	arria10_reset_deassert_shared_peripherals_q1(&mask0, &mask1);
+	arria10_reset_deassert_shared_peripherals_q2(&mask0, &mask1);
+	arria10_reset_deassert_shared_peripherals_q3(&mask0, &mask1);
+	arria10_reset_deassert_shared_peripherals_q4(&mask0, &mask1);
+
+	mask1 |= ARRIA10_RSTMGR_PER1MODRST_WATCHDOG1 |
+		 ARRIA10_RSTMGR_PER1MODRST_L4SYSTIMER1 |
+		 ARRIA10_RSTMGR_PER1MODRST_SPTIMER0 |
+		 ARRIA10_RSTMGR_PER1MODRST_SPTIMER1;
+
+	clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST,
+		     mask0 & ARRIA10_RSTMGR_OCP_MASK);
+	clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST, mask1);
+	clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask0);
+}
diff --git a/arch/arm/mach-socfpga/arria10-sdram.c b/arch/arm/mach-socfpga/arria10-sdram.c
new file mode 100644
index 0000000000..08de0e32cd
--- /dev/null
+++ b/arch/arm/mach-socfpga/arria10-sdram.c
@@ -0,0 +1,535 @@
+/*
+ * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <io.h>
+#include <debug_ll.h>
+#include <mach/generic.h>
+#include <mach/arria10-sdram.h>
+#include <mach/arria10-regs.h>
+#include <mach/arria10-reset-manager.h>
+
+
+/* FAWBANK - Number of Bank of a given device involved in the FAW period. */
+#define ARRIA10_SDR_ACTIVATE_FAWBANK	(0x1)
+
+#define ARRIA10_EMIF_RST	BIT(31)
+#define ARRIA10_OCT_CAL_REQ	BIT(30)
+#define ARRIA10_OCT_CAL_ACK	31
+
+#define ARRIA10_NIOS_OCT_DONE	BIT(7)
+#define ARRIA10_NIOS_OCT_ACK	7
+
+/* Engineering sample silicon */
+#define ARRIA10_ES_SILICON_VER	0x00010001
+
+#define DDR_REG_SEQ2CORE        0xFFD0507C
+#define DDR_REG_CORE2SEQ        0xFFD05078
+#define DDR_REG_GPOUT           0xFFD03010
+#define DDR_REG_GPIN            0xFFD03014
+#define DDR_MAX_TRIES		0x00100000
+#define IO48_MMR_DRAMSTS	0xFFCFA0EC
+#define IO48_MMR_NIOS2_RESERVE0	0xFFCFA110
+#define IO48_MMR_NIOS2_RESERVE1	0xFFCFA114
+#define IO48_MMR_NIOS2_RESERVE2	0xFFCFA118
+
+#define SEQ2CORE_MASK		0xF
+#define CORE2SEQ_INT_REQ	0xF
+#define SEQ2CORE_INT_RESP_BIT	3
+
+#define DDR_ECC_DMA_SIZE	1500
+#define DDR_READ_LATENCY_DELAY	40
+
+#define ARRIA_DDR_CONFIG(A, B, C, R)	((A<<24)|(B<<16)|(C<<8)|R)
+/* The followring are the supported configurations */
+uint32_t ddr_config[] = {
+	/* Chip - Row - Bank - Column Style */
+	/* All Types */
+	ARRIA_DDR_CONFIG(0, 3, 10, 12),
+	ARRIA_DDR_CONFIG(0, 3, 10, 13),
+	ARRIA_DDR_CONFIG(0, 3, 10, 14),
+	ARRIA_DDR_CONFIG(0, 3, 10, 15),
+	ARRIA_DDR_CONFIG(0, 3, 10, 16),
+	ARRIA_DDR_CONFIG(0, 3, 10, 17),
+	/* LPDDR x16 */
+	ARRIA_DDR_CONFIG(0, 3, 11, 14),
+	ARRIA_DDR_CONFIG(0, 3, 11, 15),
+	ARRIA_DDR_CONFIG(0, 3, 11, 16),
+	ARRIA_DDR_CONFIG(0, 3, 12, 15),
+	/* DDR4 Only */
+	ARRIA_DDR_CONFIG(0, 4, 10, 14),
+	ARRIA_DDR_CONFIG(0, 4, 10, 15),
+	ARRIA_DDR_CONFIG(0, 4, 10, 16),
+	ARRIA_DDR_CONFIG(0, 4, 10, 17),	/* 14 */
+	/* Chip - Bank - Row - Column Style */
+	ARRIA_DDR_CONFIG(1, 3, 10, 12),
+	ARRIA_DDR_CONFIG(1, 3, 10, 13),
+	ARRIA_DDR_CONFIG(1, 3, 10, 14),
+	ARRIA_DDR_CONFIG(1, 3, 10, 15),
+	ARRIA_DDR_CONFIG(1, 3, 10, 16),
+	ARRIA_DDR_CONFIG(1, 3, 10, 17),
+	ARRIA_DDR_CONFIG(1, 3, 11, 14),
+	ARRIA_DDR_CONFIG(1, 3, 11, 15),
+	ARRIA_DDR_CONFIG(1, 3, 11, 16),
+	ARRIA_DDR_CONFIG(1, 3, 12, 15),
+	/* DDR4 Only */
+	ARRIA_DDR_CONFIG(1, 4, 10, 14),
+	ARRIA_DDR_CONFIG(1, 4, 10, 15),
+	ARRIA_DDR_CONFIG(1, 4, 10, 16),
+	ARRIA_DDR_CONFIG(1, 4, 10, 17),
+};
+#define DDR_CONFIG_ELEMENTS	ARRAY_SIZE(ddr_config)
+
+static int match_ddr_conf(uint32_t ddr_conf)
+{
+	int i;
+
+	for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
+		if (ddr_conf == ddr_config[i])
+			return i;
+	}
+	return 0;
+}
+
+/* Check whether SDRAM is successfully Calibrated */
+static int is_sdram_cal_success(void)
+{
+	return readl(ARRIA10_ECC_HMC_OCP_DDRCALSTAT);
+}
+
+static unsigned char ddr_get_bit(uint32_t ereg, unsigned char bit)
+{
+	unsigned int reg = readl(ereg);
+
+	return (reg & (1 << bit)) ? 1 : 0;
+}
+
+static unsigned char ddr_wait_bit(uint32_t ereg, uint32_t bit,
+				  uint32_t expected, uint32_t timeout_usec)
+{
+	unsigned int tmr;
+
+	for (tmr = 0; tmr < timeout_usec; tmr += 100) {
+		__udelay(100);
+		if (ddr_get_bit(ereg, bit) == expected)
+			return 0;
+	}
+
+	return 1;
+}
+
+static void ddr_delay(uint32_t delay)
+{
+	int tmr;
+
+	for (tmr = 0; tmr < delay; tmr++)
+		__udelay(1000);
+}
+
+/*
+ * Diagram of OCT Workaround:
+ *
+ * EMIF Core                     HPS Processor              OCT FSM
+ * =================================================================
+ *
+ * seq2core      ==============>
+ * [0x?????????]   OCT Request   [0xFFD0507C]
+ *
+ * core2seq
+ * [0x?????????] <==============
+ *                 OCT Ready     [0xFFD05078]
+ *
+ *                               [0xFFD03010] ============> Request
+ *                                             OCT Request
+ *
+ *                               [0xFFD03014] <============ Ready
+ *                                              OCT Ready
+ * Signal definitions:
+ *
+ * seq2core[7] - OCT calibration request (act-high)
+ * core2seq[7] - Signals OCT FSM is ready (active high)
+ * gpout[31]   - EMIF Reset override (active low)
+ * gpout[30]   - OCT calibration request (act-high)
+ * gpin[31]    - OCT calibration ready (act-high)
+ */
+
+static int ddr_calibration_es_workaround(void)
+{
+	ddr_delay(500);
+	/* Step 1 - Initiating Reset Sequence */
+	clrbits_le32(DDR_REG_GPOUT, ARRIA10_EMIF_RST);
+	ddr_delay(10);
+
+	/* Step 2 - Clearing registers to EMIF core */
+	writel(0, DDR_REG_CORE2SEQ);	/*Clear the HPS->NIOS COM reg.*/
+
+	/* Step 3 - Clearing registers to OCT core */
+	clrbits_le32(DDR_REG_GPOUT, ARRIA10_OCT_CAL_REQ);
+	ddr_delay(5);
+
+	/* Step 4 - Taking EMIF out of reset */
+	setbits_le32(DDR_REG_GPOUT, ARRIA10_EMIF_RST);
+	ddr_delay(10);
+
+	/* Step 5 - Waiting for OCT circuitry to come out of reset */
+	if (ddr_wait_bit(DDR_REG_GPIN, ARRIA10_OCT_CAL_ACK, 1, 1000000))
+		return -1;
+
+	/* Step 6 - Allowing EMIF to proceed with OCT calibration */
+	setbits_le32(DDR_REG_CORE2SEQ, ARRIA10_NIOS_OCT_DONE);
+
+	/* Step 7 - Waiting for EMIF request */
+	if (ddr_wait_bit(DDR_REG_SEQ2CORE, ARRIA10_NIOS_OCT_ACK, 1, 2000000))
+		return -2;
+
+	/* Step 8 - Acknowledging EMIF OCT request */
+	clrbits_le32(DDR_REG_CORE2SEQ, ARRIA10_NIOS_OCT_DONE);
+
+	/* Step 9 - Waiting for EMIF response */
+	if (ddr_wait_bit(DDR_REG_SEQ2CORE, ARRIA10_NIOS_OCT_ACK, 0, 2000000))
+		return -3;
+
+	/* Step 10 - Triggering OCT Calibration */
+	setbits_le32(DDR_REG_GPOUT, ARRIA10_OCT_CAL_REQ);
+
+	/* Step 11 - Waiting for OCT response */
+	if (ddr_wait_bit(DDR_REG_GPIN, ARRIA10_OCT_CAL_ACK, 0, 1000))
+		return -4;
+
+	/* Step 12 - Clearing OCT Request bit */
+	clrbits_le32(DDR_REG_GPOUT, ARRIA10_OCT_CAL_REQ);
+
+	/* Step 13 - Waiting for OCT Engine */
+	if (ddr_wait_bit(DDR_REG_GPIN, ARRIA10_OCT_CAL_ACK, 1, 200000))
+		return -5;
+
+	/* Step 14 - Proceeding with EMIF calibration */
+	setbits_le32(DDR_REG_CORE2SEQ, ARRIA10_NIOS_OCT_DONE);
+
+	ddr_delay(100);
+
+	return 0;
+}
+
+static int emif_clear(void)
+{
+	uint32_t s2c;
+	uint32_t i = DDR_MAX_TRIES;
+
+	writel(0, DDR_REG_CORE2SEQ);
+	do {
+		ddr_delay(50);
+		s2c = readl(DDR_REG_SEQ2CORE);
+	} while ((s2c & SEQ2CORE_MASK) && (--i > 0));
+
+	return !i;
+}
+static int emif_reset(void)
+{
+	uint32_t c2s, s2c;
+
+	c2s = readl(DDR_REG_CORE2SEQ);
+	s2c = readl(DDR_REG_SEQ2CORE);
+
+	pr_debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
+		c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
+		readl(IO48_MMR_NIOS2_RESERVE1),
+		readl(IO48_MMR_NIOS2_RESERVE2),
+		readl(IO48_MMR_DRAMSTS));
+
+	if ((s2c & SEQ2CORE_MASK) && emif_clear()) {
+		printf("failed emif_clear()\n");
+		return -1;
+	}
+
+	writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
+
+	if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {
+		printf("emif_reset failed to see interrupt acknowledge\n");
+		return -2;
+	} else {
+		printf("emif_reset interrupt acknowledged\n");
+	}
+
+	if (emif_clear()) {
+		printf("emif_clear() failed\n");
+		return -3;
+	}
+	pr_debug("emif_reset interrupt cleared\n");
+
+	pr_debug("nr0=%08x nr1=%08x nr2=%08x\n",
+		readl(IO48_MMR_NIOS2_RESERVE0),
+		readl(IO48_MMR_NIOS2_RESERVE1),
+		readl(IO48_MMR_NIOS2_RESERVE2));
+
+	return 0;
+}
+
+static int arria10_ddr_setup(void)
+{
+	int i, j, retcode, ddr_setup_complete = 0;
+	int chip_version = readl(ARRIA10_SYSMGR_SILICONID1);
+
+	/* Try 3 times to do a calibration */
+	for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
+		/* Only engineering sample needs calibration workaround */
+		if (ARRIA10_ES_SILICON_VER == chip_version) {
+			retcode = ddr_calibration_es_workaround();
+			if (retcode) {
+				printf("DDRCAL: Failure: %d\n", retcode);
+				continue;
+			}
+		}
+
+		/* A delay to wait for calibration bit to set */
+		for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
+			ddr_delay(500);
+			ddr_setup_complete = is_sdram_cal_success();
+		}
+
+		if (!ddr_setup_complete &&
+			(ARRIA10_ES_SILICON_VER != chip_version)) {
+			emif_reset();
+		}
+	}
+
+	if (!ddr_setup_complete) {
+		puts_ll("Error: Could Not Calibrate SDRAM\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+/* Function to startup the SDRAM*/
+static int arria10_sdram_startup(void)
+{
+	uint32_t val;
+
+	/* Release NOC ddr scheduler from reset */
+	val = readl(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_BRGMODRST);
+	val &= ~ARRIA10_RSTMGR_BRGMODRST_DDRSCH;
+	writel(val, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_BRGMODRST);
+
+	/* Bringup the DDR (calibration and configuration) */
+	return arria10_ddr_setup();
+}
+
+/* Function to initialize SDRAM MMR and NOC DDR scheduler*/
+static void arria10_sdram_mmr_init(void)
+{
+	uint32_t update_value, io48_value;
+	union ctrlcfg0_reg ctrlcfg0 =
+		(union ctrlcfg0_reg)readl(ARRIA10_IO48_HMC_MMR_CTRLCFG0);
+	union ctrlcfg1_reg ctrlcfg1 =
+		(union ctrlcfg1_reg)readl(ARRIA10_IO48_HMC_MMR_CTRLCFG1);
+	union dramaddrw_reg dramaddrw =
+		(union dramaddrw_reg)readl(ARRIA10_IO48_HMC_MMR_DRAMADDRW);
+	union caltiming0_reg caltim0 =
+		(union caltiming0_reg)readl(ARRIA10_IO48_HMC_MMR_CALTIMING0);
+	union caltiming1_reg caltim1 =
+		(union caltiming1_reg)readl(ARRIA10_IO48_HMC_MMR_CALTIMING1);
+	union caltiming2_reg caltim2 =
+		(union caltiming2_reg)readl(ARRIA10_IO48_HMC_MMR_CALTIMING2);
+	union caltiming3_reg caltim3 =
+		(union caltiming3_reg)readl(ARRIA10_IO48_HMC_MMR_CALTIMING3);
+	union caltiming4_reg caltim4 =
+		(union caltiming4_reg)readl(ARRIA10_IO48_HMC_MMR_CALTIMING4);
+	union caltiming9_reg caltim9 =
+		(union caltiming9_reg)readl(ARRIA10_IO48_HMC_MMR_CALTIMING9);
+	uint32_t ddrioctl;
+
+	/*
+	 * Configure the DDR IO size [0xFFCFB008]
+	 * niosreserve0: Used to indicate DDR width &
+	 *	bit[7:0] = Number of data bits (0x20 for 32bit)
+	 *	bit[8]   = 1 if user-mode OCT is present
+	 *	bit[9]   = 1 if warm reset compiled into EMIF Cal Code
+	 *	bit[10]  = 1 if warm reset is on during generation in EMIF Cal
+	 * niosreserve1: IP ADCDS version encoded as 16 bit value
+	 *	bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
+	 *			    3=EAP, 4-6 are reserved)
+	 *	bit[5:3] = Service Pack # (e.g. 1)
+	 *	bit[9:6] = Minor Release #
+	 *	bit[14:10] = Major Release #
+	 */
+	if ((readl(ARRIA10_IO48_HMC_MMR_NIOSRESERVE1) >> 6) & 0x1FF) {
+		update_value = readl(ARRIA10_IO48_HMC_MMR_NIOSRESERVE0);
+		writel(((update_value & 0xFF) >> 5),
+		       ARRIA10_ECC_HMC_OCP_DDRIOCTRL);
+	}
+
+	ddrioctl = readl(ARRIA10_ECC_HMC_OCP_DDRIOCTRL);
+
+	/* Set the DDR Configuration [0xFFD12400] */
+	io48_value = ARRIA_DDR_CONFIG(ctrlcfg1.cfg_addr_order,
+				      (dramaddrw.cfg_bank_addr_width +
+				       dramaddrw.cfg_bank_group_addr_width),
+				      dramaddrw.cfg_col_addr_width,
+				      dramaddrw.cfg_row_addr_width);
+
+	update_value = match_ddr_conf(io48_value);
+	if (update_value)
+		writel(update_value, ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRCONF);
+
+	/*
+	 * Configure DDR timing [0xFFD1240C]
+	 *  RDTOMISS = tRTP + tRP + tRCD - BL/2
+	 *  WRTOMISS = WL + tWR + tRP + tRCD and
+	 *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
+	 *  First part of equation is in memory clock units so divide by 2
+	 *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
+	 *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
+	 */
+	update_value = (caltim2.cfg_rd_to_pch +  caltim4.cfg_pch_to_valid +
+			caltim0.cfg_act_to_rdwr -
+			(ctrlcfg0.cfg_ctrl_burst_len >> 2));
+	io48_value = ((((readl(ARRIA10_IO48_HMC_MMR_DRAMTIMING0) &
+			 ARRIA10_IO48_DRAMTIME_MEM_READ_LATENCY) + 2 + 15 +
+			(ctrlcfg0.cfg_ctrl_burst_len >> 1)) >> 1) -
+		      /* Up to here was in memory cycles so divide by 2 */
+		      caltim1.cfg_rd_to_wr + caltim0.cfg_act_to_rdwr +
+		      caltim4.cfg_pch_to_valid);
+
+	writel(((caltim0.cfg_act_to_act <<
+		 ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
+		(update_value <<
+		 ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
+		(io48_value <<
+		 ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
+		((ctrlcfg0.cfg_ctrl_burst_len >> 2) <<
+		 ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
+		(caltim1.cfg_rd_to_wr <<
+		 ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
+		(caltim3.cfg_wr_to_rd <<
+		 ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
+		(((ddrioctl == 1) ? 1 : 0) <<
+		 ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
+	       ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRTIMING);
+
+	/* Configure DDR mode [0xFFD12410] [precharge = 0] */
+	writel(((ddrioctl ? 0 : 1) <<
+		ARRIA10_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
+	       ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRMODE);
+
+	/* Configure the read latency [0xFFD12414] */
+	writel(((readl(ARRIA10_IO48_HMC_MMR_DRAMTIMING0) &
+		 ARRIA10_IO48_DRAMTIME_MEM_READ_LATENCY) >> 1) +
+	       DDR_READ_LATENCY_DELAY,
+	       ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_READLATENCY);
+
+	/*
+	 * Configuring timing values concerning activate commands
+	 * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
+	 */
+	writel(((caltim0.cfg_act_to_act_db <<
+		 ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
+		(caltim9.cfg_4_act_to_act <<
+		 ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
+		(ARRIA10_SDR_ACTIVATE_FAWBANK <<
+		 ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
+	       ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_ACTIVATE);
+
+	/*
+	 * Configuring timing values concerning device to device data bus
+	 * ownership change [0xFFD1243C]
+	 */
+	writel(((caltim1.cfg_rd_to_rd_dc <<
+		 ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
+		(caltim1.cfg_rd_to_wr_dc <<
+		 ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
+		(caltim3.cfg_wr_to_rd_dc <<
+		 ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
+	       ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DEVTODEV);
+
+	/* Enable or disable the SDRAM ECC */
+	if (ctrlcfg1.cfg_ctrl_enable_ecc) {
+		setbits_le32(ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL1,
+			     (ARRIA10_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST |
+			      ARRIA10_ECC_HMC_OCP_ECCCTL_CNT_RST |
+			      ARRIA10_ECC_HMC_OCP_ECCCTL_ECC_EN));
+		clrbits_le32(ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL1,
+			     (ARRIA10_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST |
+			      ARRIA10_ECC_HMC_OCP_ECCCTL_CNT_RST));
+		setbits_le32(ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL2,
+			     (ARRIA10_ECC_HMC_OCP_ECCCTL2_RMW_EN |
+			      ARRIA10_ECC_HMC_OCP_ECCCTL2_AWB_EN));
+	} else {
+		clrbits_le32(ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL1,
+			     (ARRIA10_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST |
+			      ARRIA10_ECC_HMC_OCP_ECCCTL_CNT_RST |
+			      ARRIA10_ECC_HMC_OCP_ECCCTL_ECC_EN));
+		clrbits_le32(ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL2,
+			     (ARRIA10_ECC_HMC_OCP_ECCCTL2_RMW_EN |
+			      ARRIA10_ECC_HMC_OCP_ECCCTL2_AWB_EN));
+	}
+}
+
+static int arria10_sdram_firewall_setup(void)
+{
+	uint32_t mpu_en = 0;
+
+	/* set to default state */
+	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_EN);
+	writel(0x00000000, ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x00);
+
+	writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION0ADDR);
+
+	mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG0EN;
+
+	writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
+	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION1ADDR);
+	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION2ADDR);
+	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION3ADDR);
+	writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION0ADDR);
+
+	mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG1EN;
+	writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
+
+	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION1ADDR);
+	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION2ADDR);
+	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION3ADDR);
+	writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION0ADDR);
+
+	mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG2EN;
+	writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
+
+	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION1ADDR);
+	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION2ADDR);
+	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION3ADDR);
+	writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION0ADDR);
+
+	mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG3EN;
+	writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
+
+	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION1ADDR);
+	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION2ADDR);
+	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION3ADDR);
+
+	writel(0xffff0000, ARRIA10_NOC_FW_DDR_L3_HPSREGION0ADDR);
+	writel(ARRIA10_NOC_FW_DDR_L3_HPSREG0EN, ARRIA10_NOC_FW_DDR_L3_EN);
+
+	return 0;
+}
+
+int arria10_ddr_calibration_sequence(void)
+{
+	/* Check to see if SDRAM cal was success */
+	if (arria10_sdram_startup()) {
+		puts_ll("DDRCAL: Failed\n");
+		return -1;
+	}
+
+	puts_ll("DDRCAL: Success\n");
+
+	/* initialize the MMR register */
+	arria10_sdram_mmr_init();
+
+	if (arria10_sdram_firewall_setup())
+		puts_ll("FW: Error Configuring Firewall\n");
+
+	return 0;
+}
diff --git a/arch/arm/mach-socfpga/cyclone5-bootsource.c b/arch/arm/mach-socfpga/cyclone5-bootsource.c
index da4102c4f5..717a003425 100644
--- a/arch/arm/mach-socfpga/cyclone5-bootsource.c
+++ b/arch/arm/mach-socfpga/cyclone5-bootsource.c
@@ -18,6 +18,7 @@
 #include <io.h>
 #include <mach/cyclone5-system-manager.h>
 #include <mach/cyclone5-regs.h>
+#include <mach/arria10-system-manager.h>
 
 #define CYCLONE5_SYSMGR_BOOTINFO	0x14
 
@@ -54,4 +55,46 @@ static int cyclone5_boot_save_loc(void)
 
 	return 0;
 }
-core_initcall(cyclone5_boot_save_loc);
+
+static int arria10_boot_save_loc(void)
+{
+	enum bootsource src = BOOTSOURCE_UNKNOWN;
+	uint32_t val;
+
+	val = readl(ARRIA10_SYSMGR_BOOTINFO);
+
+	switch ((val & 0x7000) >> 12) {
+	case 0:
+		/* reserved */
+		break;
+	case 1:
+		/* FPGA, currently not decoded */
+		break;
+	case 2:
+	case 3:
+		src = BOOTSOURCE_NAND;
+		break;
+	case 4:
+	case 5:
+		src = BOOTSOURCE_MMC;
+		break;
+	case 6:
+	case 7:
+		src = BOOTSOURCE_SPI;
+		break;
+	}
+
+	bootsource_set(src);
+	bootsource_set_instance(0);
+
+	return 0;
+}
+
+static int socfpga_boot_save_loc(void)
+{
+	if (IS_ENABLED(CONFIG_ARCH_SOCFPGA_ARRIA10))
+		return arria10_boot_save_loc();
+	else
+		return cyclone5_boot_save_loc();
+}
+core_initcall(socfpga_boot_save_loc);
diff --git a/arch/arm/mach-socfpga/generic.c b/arch/arm/mach-socfpga/generic.c
deleted file mode 100644
index c920bd658f..0000000000
--- a/arch/arm/mach-socfpga/generic.c
+++ /dev/null
@@ -1,104 +0,0 @@
-#include <common.h>
-#include <malloc.h>
-#include <envfs.h>
-#include <init.h>
-#include <io.h>
-#include <fs.h>
-#include <linux/clkdev.h>
-#include <linux/clk.h>
-#include <linux/stat.h>
-#include <asm/memory.h>
-#include <mach/system-manager.h>
-#include <mach/reset-manager.h>
-#include <mach/socfpga-regs.h>
-#include <mach/nic301.h>
-
-#define SYSMGR_SDMMCGRP_CTRL_REG	(CYCLONE5_SYSMGR_ADDRESS + 0x108)
-#define SYSMGR_SDMMC_CTRL_SMPLSEL(smplsel)	(((smplsel) & 0x7) << 3)
-#define SYSMGR_SDMMC_CTRL_DRVSEL(drvsel)	((drvsel) & 0x7)
-
-static int socfpga_detect_sdram(void)
-{
-	void __iomem *base = (void *)CYCLONE5_SDR_ADDRESS;
-	uint32_t dramaddrw, ctrlwidth, memsize;
-	int colbits, rowbits, bankbits;
-	int width_bytes;
-
-	dramaddrw = readl(base + 0x5000 + 0x2c);
-
-	colbits = dramaddrw & 0x1f;
-	rowbits = (dramaddrw >> 5) & 0x1f;
-	bankbits = (dramaddrw >> 10) & 0x7;
-
-	ctrlwidth = readl(base + 0x5000 + 0x60);
-
-	switch (ctrlwidth & 0x3) {
-	default:
-	case 0:
-		width_bytes = 1;
-		break;
-	case 1:
-		width_bytes = 2;
-		break;
-	case 2:
-		width_bytes = 4;
-		break;
-	}
-
-	memsize = (1 << colbits) * (1 << rowbits) * (1 << bankbits) * width_bytes;
-
-	pr_debug("%s: colbits: %d rowbits: %d bankbits: %d width: %d => memsize: 0x%08x\n",
-			__func__, colbits, rowbits, bankbits, width_bytes, memsize);
-
-	arm_add_mem_device("ram0", 0x0, memsize);
-
-	return 0;
-}
-
-/* Some initialization for the EMAC */
-static void socfpga_init_emac(void)
-{
-	uint32_t rst, val;
-
-	/* No need for this without network support, e.g. xloader build */
-	if (!IS_ENABLED(CONFIG_NET))
-		return;
-
-	/* According to Cyclone V datasheet, 17-60 "EMAC HPS Interface
-	 * Initialization", changing PHYSEL should be done with EMAC in reset
-	 * via permodrst.  */
-
-	/* Everything, except L4WD0/1, is out of reset via socfpga_lowlevel_init() */
-	rst = readl(CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS);
-	rst |= RSTMGR_PERMODRST_EMAC0 | RSTMGR_PERMODRST_EMAC1;
-	writel(rst, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS);
-
-	/* Set emac0/1 PHY interface select to RGMII.  We could read phy-mode
-	 * from the device tree, if it was desired to support interfaces other
-	 * than RGMII. */
-	val = readl(CONFIG_SYSMGR_EMAC_CTRL);
-	val &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB);
-	val &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB);
-	val |= SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
-	val |= SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
-	writel(val, CONFIG_SYSMGR_EMAC_CTRL);
-
-	/* Take emac0 and emac1 out of reset */
-	rst &= ~(RSTMGR_PERMODRST_EMAC0 | RSTMGR_PERMODRST_EMAC1);
-	writel(rst, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS);
-}
-
-static int socfpga_init(void)
-{
-	socfpga_init_emac();
-
-	writel(SYSMGR_SDMMC_CTRL_DRVSEL(3) | SYSMGR_SDMMC_CTRL_SMPLSEL(0),
-		SYSMGR_SDMMCGRP_CTRL_REG);
-
-	nic301_slave_ns();
-
-	socfpga_detect_sdram();
-
-	return 0;
-}
-core_initcall(socfpga_init);
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h b/arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h
new file mode 100644
index 0000000000..ee2b9b3c5e
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h
@@ -0,0 +1,249 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_ARRIA10_CLOCK_MANAGER_H_
+#define	_ARRIA10_CLOCK_MANAGER_H_
+
+struct arria10_clock_manager {
+	/* clkmgr */
+	volatile uint32_t  ctrl;
+	volatile uint32_t  intr;
+	volatile uint32_t  intrs;
+	volatile uint32_t  intrr;
+	volatile uint32_t  intren;
+	volatile uint32_t  intrens;
+	volatile uint32_t  intrenr;
+	volatile uint32_t  stat;
+	volatile uint32_t  testioctrl;
+	volatile uint32_t  _pad_0x24_0x40[7];
+
+	/* mainpllgrp*/
+	volatile uint32_t  main_pll_vco0;
+	volatile uint32_t  main_pll_vco1;
+	volatile uint32_t  main_pll_en;
+	volatile uint32_t  main_pll_ens;
+	volatile uint32_t  main_pll_enr;
+	volatile uint32_t  main_pll_bypass;
+	volatile uint32_t  main_pll_bypasss;
+	volatile uint32_t  main_pll_bypassr;
+	volatile uint32_t  main_pll_mpuclk;
+	volatile uint32_t  main_pll_nocclk;
+	volatile uint32_t  main_pll_cntr2clk;
+	volatile uint32_t  main_pll_cntr3clk;
+	volatile uint32_t  main_pll_cntr4clk;
+	volatile uint32_t  main_pll_cntr5clk;
+	volatile uint32_t  main_pll_cntr6clk;
+	volatile uint32_t  main_pll_cntr7clk;
+	volatile uint32_t  main_pll_cntr8clk;
+	volatile uint32_t  main_pll_cntr9clk;
+	volatile uint32_t  main_pll__pad_0x48_0x5b[5];
+	volatile uint32_t  main_pll_cntr15clk;
+	volatile uint32_t  main_pll_outrst;
+	volatile uint32_t  main_pll_outrststat;
+	volatile uint32_t  main_pll_nocdiv;
+	volatile uint32_t  main_pll__pad_0x6c_0x80[5];
+
+	/* perpllgrp*/
+	volatile uint32_t  per_pll_vco0;
+	volatile uint32_t  per_pll_vco1;
+	volatile uint32_t  per_pll_en;
+	volatile uint32_t  per_pll_ens;
+	volatile uint32_t  per_pll_enr;
+	volatile uint32_t  per_pll_bypass;
+	volatile uint32_t  per_pll_bypasss;
+	volatile uint32_t  per_pll_bypassr;
+	volatile uint32_t  per_pll__pad_0x20_0x27[2];
+	volatile uint32_t  per_pll_cntr2clk;
+	volatile uint32_t  per_pll_cntr3clk;
+	volatile uint32_t  per_pll_cntr4clk;
+	volatile uint32_t  per_pll_cntr5clk;
+	volatile uint32_t  per_pll_cntr6clk;
+	volatile uint32_t  per_pll_cntr7clk;
+	volatile uint32_t  per_pll_cntr8clk;
+	volatile uint32_t  per_pll_cntr9clk;
+	volatile uint32_t  per_pll__pad_0x48_0x5f[6];
+	volatile uint32_t  per_pll_outrst;
+	volatile uint32_t  per_pll_outrststat;
+	volatile uint32_t  per_pll_emacctl;
+	volatile uint32_t  per_pll_gpiodiv;
+	volatile uint32_t  per_pll__pad_0x70_0x80[4];
+};
+
+struct arria10_mainpll_cfg {
+	uint32_t vco0_psrc;
+	uint32_t vco1_denom;
+	uint32_t vco1_numer;
+	uint32_t mpuclk;
+	uint32_t mpuclk_cnt;
+	uint32_t mpuclk_src;
+	uint32_t nocclk;
+	uint32_t nocclk_cnt;
+	uint32_t nocclk_src;
+	uint32_t cntr2clk_cnt;
+	uint32_t cntr3clk_cnt;
+	uint32_t cntr4clk_cnt;
+	uint32_t cntr5clk_cnt;
+	uint32_t cntr6clk_cnt;
+	uint32_t cntr7clk_cnt;
+	uint32_t cntr7clk_src;
+	uint32_t cntr8clk_cnt;
+	uint32_t cntr9clk_cnt;
+	uint32_t cntr9clk_src;
+	uint32_t cntr15clk_cnt;
+	uint32_t nocdiv_l4mainclk;
+	uint32_t nocdiv_l4mpclk;
+	uint32_t nocdiv_l4spclk;
+	uint32_t nocdiv_csatclk;
+	uint32_t nocdiv_cstraceclk;
+	uint32_t nocdiv_cspdbgclk;
+};
+
+struct arria10_perpll_cfg {
+	uint32_t vco0_psrc;
+	uint32_t vco1_denom;
+	uint32_t vco1_numer;
+	uint32_t cntr2clk_cnt;
+	uint32_t cntr2clk_src;
+	uint32_t cntr3clk_cnt;
+	uint32_t cntr3clk_src;
+	uint32_t cntr4clk_cnt;
+	uint32_t cntr4clk_src;
+	uint32_t cntr5clk_cnt;
+	uint32_t cntr5clk_src;
+	uint32_t cntr6clk_cnt;
+	uint32_t cntr6clk_src;
+	uint32_t cntr7clk_cnt;
+	uint32_t cntr8clk_cnt;
+	uint32_t cntr8clk_src;
+	uint32_t cntr9clk_cnt;
+	uint32_t cntr9clk_src;
+	uint32_t emacctl_emac0sel;
+	uint32_t emacctl_emac1sel;
+	uint32_t emacctl_emac2sel;
+	uint32_t gpiodiv_gpiodbclk;
+};
+
+extern int arria10_cm_basic_init(struct arria10_mainpll_cfg *mainpll_cfg,
+				 struct arria10_perpll_cfg *perpll_cfg);
+extern unsigned int cm_get_mmc_controller_clk_hz(void);
+extern void arria10_cm_use_intosc(void);
+extern uint32_t cm_l4_main_clk_hz;
+extern uint32_t cm_l4_sp_clk_hz;
+extern uint32_t cm_l4_mp_clk_hz;
+extern uint32_t cm_l4_sys_free_clk_hz;
+
+#define ARRIA10_CLKMGR_ALTERAGRP_MPU_CLK_OFFSET			0x140
+#define ARRIA10_CLKMGR_MAINPLL_NOC_CLK_OFFSET			0x144
+
+/* value */
+#define ARRIA10_CLKMGR_MAINPLL_BYPASS_RESET			0x0000003f
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_RESET			0x00010053
+#define ARRIA10_CLKMGR_MAINPLL_VCO1_RESET			0x00010001
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_EOSC			0x0
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC		0x1
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_F2S			0x2
+#define ARRIA10_CLKMGR_PERPLL_BYPASS_RESET			0x000000ff
+#define ARRIA10_CLKMGR_PERPLL_VCO0_RESET			0x00010053
+#define ARRIA10_CLKMGR_PERPLL_VCO1_RESET			0x00010001
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_EOSC			0x0
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC		0x1
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_F2S			0x2
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MAIN			0x3
+
+/* mask */
+#define ARRIA10_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK		0x00000040
+#define ARRIA10_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK	0x00000080
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK		0x00000001
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK		0x00000002
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_EN_SET_MSK			0x00000004
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK		0x00000008
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK		0x00000010
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_MSK			0x00000003
+#define ARRIA10_CLKMGR_MAINPLL_VCO1_NUMER_MSK			0x00001fff
+#define ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_MSK			0x0000003f
+#define ARRIA10_CLKMGR_MAINPLL_CNTRCLK_MSK			0x000003ff
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_CNT_MSK			0x000003ff
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN			0
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI			1
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_OSC1			2
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC		3
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_FPGA			4
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_MSK			0x00000003
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_CNT_MSK			0x000003ff
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MSK			0x00000007
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN			0
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI			1
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_OSC1			2
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC		3
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_FPGA			4
+#define ARRIA10_CLKMGR_CLKMGR_STAT_BUSY_SET_MSK			0x00000001
+#define ARRIA10_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK	0x00000100
+#define ARRIA10_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK		0x00000200
+#define ARRIA10_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK		0x00020000
+#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK		0x00000800
+#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK	0x00000400
+#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK		0x00000200
+#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK	0x00000100
+#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK		0x00000008
+#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK		0x00000004
+#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK	0x00000001
+#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK	0x00000002
+#define ARRIA10_CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK		0x00000001
+#define ARRIA10_CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK	0x00000300
+#define ARRIA10_CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK		0x00000001
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK		0x00000002
+#define ARRIA10_CLKMGR_PERPLL_VCO0_EN_SET_MSK			0x00000004
+#define ARRIA10_CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK		0x00000008
+#define ARRIA10_CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK		0x00000010
+#define ARRIA10_CLKMGR_PERPLL_EN_RESET				0x00000f7f
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MSK			0x00000003
+#define ARRIA10_CLKMGR_PERPLL_VCO1_NUMER_MSK			0x00001fff
+#define ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_MSK			0x0000003f
+#define ARRIA10_CLKMGR_PERPLL_CNTRCLK_MSK			0x000003ff
+
+#define ARRIA10_CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK		0x00000020
+#define ARRIA10_CLKMGR_PERPLLGRP_SRC_MSK			0x00000007
+#define ARRIA10_CLKMGR_PERPLLGRP_SRC_MAIN			0
+#define ARRIA10_CLKMGR_PERPLLGRP_SRC_PERI			1
+#define ARRIA10_CLKMGR_PERPLLGRP_SRC_OSC1			2
+#define ARRIA10_CLKMGR_PERPLLGRP_SRC_INTOSC			3
+#define ARRIA10_CLKMGR_PERPLLGRP_SRC_FPGA			4
+
+/* bit shifting macro */
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_LSB			8
+#define ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB			16
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB		16
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_LSB			16
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB		0
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB		8
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB		16
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB		24
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB		26
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB		28
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_LSB			16
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB		16
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_LSB			16
+#define ARRIA10_CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB			16
+#define ARRIA10_CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB			16
+#define ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB			16
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_LSB			8
+#define ARRIA10_CLKMGR_PERPLL_CNTR2CLK_SRC_LSB			16
+#define ARRIA10_CLKMGR_PERPLL_CNTR3CLK_SRC_LSB			16
+#define ARRIA10_CLKMGR_PERPLL_CNTR4CLK_SRC_LSB			16
+#define ARRIA10_CLKMGR_PERPLL_CNTR5CLK_SRC_LSB			16
+#define ARRIA10_CLKMGR_PERPLL_CNTR6CLK_SRC_LSB			16
+#define ARRIA10_CLKMGR_PERPLL_CNTR8CLK_SRC_LSB			16
+#define ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB		26
+#define ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB		27
+#define ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB		28
+
+/* PLL ramping work around */
+#define ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ		900000000
+#define ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ		300000000
+#define ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ		100000000
+#define ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ		 33000000
+
+#endif /* _ARRIA10_CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-pinmux.h b/arch/arm/mach-socfpga/include/mach/arria10-pinmux.h
new file mode 100644
index 0000000000..979e4769db
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/arria10-pinmux.h
@@ -0,0 +1,250 @@
+/*
+ *  Copyright (C) 2017 Pengutronix, Steffen Trumtrar <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _ARRIA10_PINMUX_H_
+#define _ARRIA10_PINMUX_H_
+
+#include <mach/arria10-regs.h>
+
+#define ARRIA10_PINMUX_SHARED_IO_Q1_1_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x00
+#define ARRIA10_PINMUX_SHARED_IO_Q1_2_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x04
+#define ARRIA10_PINMUX_SHARED_IO_Q1_3_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x08
+#define ARRIA10_PINMUX_SHARED_IO_Q1_4_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x0c
+#define ARRIA10_PINMUX_SHARED_IO_Q1_5_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x10
+#define ARRIA10_PINMUX_SHARED_IO_Q1_6_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x14
+#define ARRIA10_PINMUX_SHARED_IO_Q1_7_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x18
+#define ARRIA10_PINMUX_SHARED_IO_Q1_8_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x1c
+#define ARRIA10_PINMUX_SHARED_IO_Q1_9_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x20
+#define ARRIA10_PINMUX_SHARED_IO_Q1_10_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x24
+#define ARRIA10_PINMUX_SHARED_IO_Q1_11_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x28
+#define ARRIA10_PINMUX_SHARED_IO_Q1_12_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x2c
+#define ARRIA10_PINMUX_SHARED_IO_Q2_1_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x30
+#define ARRIA10_PINMUX_SHARED_IO_Q2_2_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x34
+#define ARRIA10_PINMUX_SHARED_IO_Q2_3_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x38
+#define ARRIA10_PINMUX_SHARED_IO_Q2_4_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x3c
+#define ARRIA10_PINMUX_SHARED_IO_Q2_5_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x40
+#define ARRIA10_PINMUX_SHARED_IO_Q2_6_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x44
+#define ARRIA10_PINMUX_SHARED_IO_Q2_7_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x48
+#define ARRIA10_PINMUX_SHARED_IO_Q2_8_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x4c
+#define ARRIA10_PINMUX_SHARED_IO_Q2_9_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x50
+#define ARRIA10_PINMUX_SHARED_IO_Q2_10_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x54
+#define ARRIA10_PINMUX_SHARED_IO_Q2_11_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x58
+#define ARRIA10_PINMUX_SHARED_IO_Q2_12_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x5c
+#define ARRIA10_PINMUX_SHARED_IO_Q3_1_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x60
+#define ARRIA10_PINMUX_SHARED_IO_Q3_2_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x64
+#define ARRIA10_PINMUX_SHARED_IO_Q3_3_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x68
+#define ARRIA10_PINMUX_SHARED_IO_Q3_4_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x6c
+#define ARRIA10_PINMUX_SHARED_IO_Q3_5_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x70
+#define ARRIA10_PINMUX_SHARED_IO_Q3_6_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x74
+#define ARRIA10_PINMUX_SHARED_IO_Q3_7_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x78
+#define ARRIA10_PINMUX_SHARED_IO_Q3_8_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x7c
+#define ARRIA10_PINMUX_SHARED_IO_Q3_9_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x80
+#define ARRIA10_PINMUX_SHARED_IO_Q3_10_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x84
+#define ARRIA10_PINMUX_SHARED_IO_Q3_11_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x88
+#define ARRIA10_PINMUX_SHARED_IO_Q3_12_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x8c
+#define ARRIA10_PINMUX_SHARED_IO_Q4_1_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x90
+#define ARRIA10_PINMUX_SHARED_IO_Q4_2_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x94
+#define ARRIA10_PINMUX_SHARED_IO_Q4_3_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x98
+#define ARRIA10_PINMUX_SHARED_IO_Q4_4_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x9c
+#define ARRIA10_PINMUX_SHARED_IO_Q4_5_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xa0
+#define ARRIA10_PINMUX_SHARED_IO_Q4_6_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xa4
+#define ARRIA10_PINMUX_SHARED_IO_Q4_7_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xa8
+#define ARRIA10_PINMUX_SHARED_IO_Q4_8_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xac
+#define ARRIA10_PINMUX_SHARED_IO_Q4_9_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xb0
+#define ARRIA10_PINMUX_SHARED_IO_Q4_10_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xb4
+#define ARRIA10_PINMUX_SHARED_IO_Q4_11_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xb8
+#define ARRIA10_PINMUX_SHARED_IO_Q4_12_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xbc
+
+#define ARRIA10_PINMUX_SHARED_IO_Q1_I2C		0
+#define ARRIA10_PINMUX_SHARED_IO_Q1_EMAC	1
+#define ARRIA10_PINMUX_SHARED_IO_Q1_SPIS	2
+#define ARRIA10_PINMUX_SHARED_IO_Q1_SPIM	3
+#define ARRIA10_PINMUX_SHARED_IO_Q1_SDMMC	4
+#define ARRIA10_PINMUX_SHARED_IO_Q1_USB		8
+#define ARRIA10_PINMUX_SHARED_IO_Q1_QSPI	12
+#define ARRIA10_PINMUX_SHARED_IO_Q1_UART	13
+#define ARRIA10_PINMUX_SHARED_IO_Q1_NAND	14
+#define ARRIA10_PINMUX_SHARED_IO_Q1_GPIO	15
+
+#define ARRIA10_PINMUX_SHARED_IO_Q2_I2C		0
+#define ARRIA10_PINMUX_SHARED_IO_Q2_SPIS	2
+#define ARRIA10_PINMUX_SHARED_IO_Q2_SPIM	3
+#define ARRIA10_PINMUX_SHARED_IO_Q2_EMAC	4
+#define ARRIA10_PINMUX_SHARED_IO_Q2_USB		8
+#define ARRIA10_PINMUX_SHARED_IO_Q2_UART	13
+#define ARRIA10_PINMUX_SHARED_IO_Q2_NAND	14
+#define ARRIA10_PINMUX_SHARED_IO_Q2_GPIO	15
+
+#define ARRIA10_PINMUX_SHARED_IO_Q3_I2C		0
+#define ARRIA10_PINMUX_SHARED_IO_Q3_EMAC0	1
+#define ARRIA10_PINMUX_SHARED_IO_Q3_SPIS	2
+#define ARRIA10_PINMUX_SHARED_IO_Q3_SPIM	3
+#define ARRIA10_PINMUX_SHARED_IO_Q3_EMAC1	8
+#define ARRIA10_PINMUX_SHARED_IO_Q3_UART	13
+#define ARRIA10_PINMUX_SHARED_IO_Q3_NAND	14
+#define ARRIA10_PINMUX_SHARED_IO_Q3_GPIO	15
+
+#define ARRIA10_PINMUX_SHARED_IO_Q4_I2C		0
+#define ARRIA10_PINMUX_SHARED_IO_Q4_EMAC0	1
+#define ARRIA10_PINMUX_SHARED_IO_Q4_SPIS	2
+#define ARRIA10_PINMUX_SHARED_IO_Q4_SPIM	3
+#define ARRIA10_PINMUX_SHARED_IO_Q4_SDMMC	4
+#define ARRIA10_PINMUX_SHARED_IO_Q4_EMAC1	8
+#define ARRIA10_PINMUX_SHARED_IO_Q4_QSPI	12
+#define ARRIA10_PINMUX_SHARED_IO_Q4_UART	13
+#define ARRIA10_PINMUX_SHARED_IO_Q4_NAND	14
+#define ARRIA10_PINMUX_SHARED_IO_Q4_GPIO	15
+
+#define ARRIA10_PINMUX_DEDICATED_IO_1_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x00
+#define ARRIA10_PINMUX_DEDICATED_IO_2_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x04
+#define ARRIA10_PINMUX_DEDICATED_IO_3_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x08
+#define ARRIA10_PINMUX_DEDICATED_IO_4_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x0c
+#define ARRIA10_PINMUX_DEDICATED_IO_5_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x10
+#define ARRIA10_PINMUX_DEDICATED_IO_6_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x14
+#define ARRIA10_PINMUX_DEDICATED_IO_7_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x18
+#define ARRIA10_PINMUX_DEDICATED_IO_8_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x1c
+#define ARRIA10_PINMUX_DEDICATED_IO_9_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x20
+#define ARRIA10_PINMUX_DEDICATED_IO_10_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x24
+#define ARRIA10_PINMUX_DEDICATED_IO_11_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x28
+#define ARRIA10_PINMUX_DEDICATED_IO_12_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x2c
+#define ARRIA10_PINMUX_DEDICATED_IO_13_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x30
+#define ARRIA10_PINMUX_DEDICATED_IO_14_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x34
+#define ARRIA10_PINMUX_DEDICATED_IO_15_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x38
+#define ARRIA10_PINMUX_DEDICATED_IO_16_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x3c
+#define ARRIA10_PINMUX_DEDICATED_IO_17_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x40
+
+#define ARRIA10_PINCFG_DEDICATED_IO_BANK_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x00
+#define ARRIA10_PINCFG_DEDICATED_IO_1_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x04
+#define ARRIA10_PINCFG_DEDICATED_IO_2_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x08
+#define ARRIA10_PINCFG_DEDICATED_IO_3_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x0c
+#define ARRIA10_PINCFG_DEDICATED_IO_4_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x10
+#define ARRIA10_PINCFG_DEDICATED_IO_5_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x14
+#define ARRIA10_PINCFG_DEDICATED_IO_6_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x18
+#define ARRIA10_PINCFG_DEDICATED_IO_7_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x1c
+#define ARRIA10_PINCFG_DEDICATED_IO_8_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x20
+#define ARRIA10_PINCFG_DEDICATED_IO_9_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x24
+#define ARRIA10_PINCFG_DEDICATED_IO_10_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x28
+#define ARRIA10_PINCFG_DEDICATED_IO_11_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x2c
+#define ARRIA10_PINCFG_DEDICATED_IO_12_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x30
+#define ARRIA10_PINCFG_DEDICATED_IO_13_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x34
+#define ARRIA10_PINCFG_DEDICATED_IO_14_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x38
+#define ARRIA10_PINCFG_DEDICATED_IO_15_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x3c
+#define ARRIA10_PINCFG_DEDICATED_IO_16_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x40
+#define ARRIA10_PINCFG_DEDICATED_IO_17_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x44
+
+enum arria10_pinmux_io_addr {
+	arria10_pinmux_shared_io_q1_1,
+	arria10_pinmux_shared_io_q1_2,
+	arria10_pinmux_shared_io_q1_3,
+	arria10_pinmux_shared_io_q1_4,
+	arria10_pinmux_shared_io_q1_5,
+	arria10_pinmux_shared_io_q1_6,
+	arria10_pinmux_shared_io_q1_7,
+	arria10_pinmux_shared_io_q1_8,
+	arria10_pinmux_shared_io_q1_9,
+	arria10_pinmux_shared_io_q1_10,
+	arria10_pinmux_shared_io_q1_11,
+	arria10_pinmux_shared_io_q1_12,
+	arria10_pinmux_shared_io_q2_1,
+	arria10_pinmux_shared_io_q2_2,
+	arria10_pinmux_shared_io_q2_3,
+	arria10_pinmux_shared_io_q2_4,
+	arria10_pinmux_shared_io_q2_5,
+	arria10_pinmux_shared_io_q2_6,
+	arria10_pinmux_shared_io_q2_7,
+	arria10_pinmux_shared_io_q2_8,
+	arria10_pinmux_shared_io_q2_9,
+	arria10_pinmux_shared_io_q2_10,
+	arria10_pinmux_shared_io_q2_11,
+	arria10_pinmux_shared_io_q2_12,
+	arria10_pinmux_shared_io_q3_1,
+	arria10_pinmux_shared_io_q3_2,
+	arria10_pinmux_shared_io_q3_3,
+	arria10_pinmux_shared_io_q3_4,
+	arria10_pinmux_shared_io_q3_5,
+	arria10_pinmux_shared_io_q3_6,
+	arria10_pinmux_shared_io_q3_7,
+	arria10_pinmux_shared_io_q3_8,
+	arria10_pinmux_shared_io_q3_9,
+	arria10_pinmux_shared_io_q3_10,
+	arria10_pinmux_shared_io_q3_11,
+	arria10_pinmux_shared_io_q3_12,
+	arria10_pinmux_shared_io_q4_1,
+	arria10_pinmux_shared_io_q4_2,
+	arria10_pinmux_shared_io_q4_3,
+	arria10_pinmux_shared_io_q4_4,
+	arria10_pinmux_shared_io_q4_5,
+	arria10_pinmux_shared_io_q4_6,
+	arria10_pinmux_shared_io_q4_7,
+	arria10_pinmux_shared_io_q4_8,
+	arria10_pinmux_shared_io_q4_9,
+	arria10_pinmux_shared_io_q4_10,
+	arria10_pinmux_shared_io_q4_11,
+	arria10_pinmux_shared_io_q4_12,
+	arria10_pinmux_dedicated_io_1,
+	arria10_pinmux_dedicated_io_2,
+	arria10_pinmux_dedicated_io_3,
+	arria10_pinmux_dedicated_io_4,
+	arria10_pinmux_dedicated_io_5,
+	arria10_pinmux_dedicated_io_6,
+	arria10_pinmux_dedicated_io_7,
+	arria10_pinmux_dedicated_io_8,
+	arria10_pinmux_dedicated_io_9,
+	arria10_pinmux_dedicated_io_10,
+	arria10_pinmux_dedicated_io_11,
+	arria10_pinmux_dedicated_io_12,
+	arria10_pinmux_dedicated_io_13,
+	arria10_pinmux_dedicated_io_14,
+	arria10_pinmux_dedicated_io_15,
+	arria10_pinmux_dedicated_io_16,
+	arria10_pinmux_dedicated_io_17,
+	arria10_pincfg_dedicated_io_bank,
+	arria10_pincfg_dedicated_io_1,
+	arria10_pincfg_dedicated_io_2,
+	arria10_pincfg_dedicated_io_3,
+	arria10_pincfg_dedicated_io_4,
+	arria10_pincfg_dedicated_io_5,
+	arria10_pincfg_dedicated_io_6,
+	arria10_pincfg_dedicated_io_7,
+	arria10_pincfg_dedicated_io_8,
+	arria10_pincfg_dedicated_io_9,
+	arria10_pincfg_dedicated_io_10,
+	arria10_pincfg_dedicated_io_11,
+	arria10_pincfg_dedicated_io_12,
+	arria10_pincfg_dedicated_io_13,
+	arria10_pincfg_dedicated_io_14,
+	arria10_pincfg_dedicated_io_15,
+	arria10_pincfg_dedicated_io_16,
+	arria10_pincfg_dedicated_io_17,
+	arria10_pinmux_rgmii0_usefpga,
+	arria10_pinmux_rgmii1_usefpga,
+	arria10_pinmux_rgmii2_usefpga,
+	arria10_pinmux_i2c0_usefpga,
+	arria10_pinmux_i2c1_usefpga,
+	arria10_pinmux_i2cemac0_usefpga,
+	arria10_pinmux_i2cemac1_usefpga,
+	arria10_pinmux_i2cemac2_usefpga,
+	arria10_pinmux_nand_usefpga,
+	arria10_pinmux_qspi_usefpga,
+	arria10_pinmux_sdmmc_usefpga,
+	arria10_pinmux_spim0_usefpga,
+	arria10_pinmux_spim1_usefpga,
+	arria10_pinmux_spis0_usefpga,
+	arria10_pinmux_spis1_usefpga,
+	arria10_pinmux_uart0_usefpga,
+	arria10_pinmux_uart1_usefpga,
+	arria10_pinmux_max
+};
+#endif
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-regs.h b/arch/arm/mach-socfpga/include/mach/arria10-regs.h
new file mode 100644
index 0000000000..5569574e15
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/arria10-regs.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ARRIA10_HARDWARE_H_
+#define _ARRIA10_HARDWARE_H_
+
+#define ARRIA10_EMAC0_ADDR				(0xff800000)
+#define ARRIA10_EMAC1_ADDR				(0xff802000)
+#define ARRIA10_EMAC2_ADDR				(0xff804000)
+#define ARRIA10_SDMMC_ADDR				(0xff808000)
+#define ARRIA10_QSPIREGS_ADDR				(0xff809000)
+#define ARRIA10_ECC_OCRAM_ADDR				(0xff8c3000)
+#define ARRIA10_QSPIDATA_ADDR				(0xffa00000)
+#define ARRIA10_UART0_ADDR				(0xffc02000)
+#define ARRIA10_UART1_ADDR				(0xffc02100)
+#define ARRIA10_I2C0_ADDR				(0xffc02200)
+#define ARRIA10_I2C1_ADDR				(0xffc02300)
+#define ARRIA10_GPIO0_ADDR				(0xffc02900)
+#define ARRIA10_GPIO1_ADDR				(0xffc02a00)
+#define ARRIA10_GPIO2_ADDR				(0xffc02b00)
+#define ARRIA10_HMC_MMR_IO48_ADDR			(0xffcfa000)
+#define ARRIA10_SDR_ADDR				(0xffcfb000)
+#define ARRIA10_FPGAMGRDATA_ADDR			(0xffcfe400)
+#define ARRIA10_OSC1TIMER0_ADDR				(0xffd00000)
+#define ARRIA10_L4WD0_ADDR				(0xffd00200)
+#define ARRIA10_FPGAMGRREGS_ADDR			(0xffd03000)
+#define ARRIA10_CLKMGR_ADDR				(0xffd04000)
+#define ARRIA10_RSTMGR_ADDR				(0xffd05000)
+#define ARRIA10_SYSMGR_ADDR				(0xffd06000)
+#define ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR		(0xffd07000)
+#define ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR		(0xffd07200)
+#define ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR	(0xffd07300)
+#define ARRIA10_PINMUX_FPGA_INTERFACE_ADDR		(0xffd07400)
+#define ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR		(0xffd11000)
+#define ARRIA10_SDR_SCHEDULER_ADDR			(0xffd12400)
+#define ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR		(0xffd13000)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR		(0xffd13200)
+#define ARRIA10_SDR_FW_MPU_FPGA_ADDR			(0xffd13300)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR		(0xffd13400)
+#define ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_ADDR	(0xffd13500)
+#define ARRIA10_DMANONSECURE_ADDR			(0xffda0000)
+#define ARRIA10_DMASECURE_ADDR				(0xffda1000)
+#define ARRIA10_MPUSCU_ADDR				(0xffffc000)
+#define ARRIA10_MPUL2_ADDR				(0xfffff000)
+
+/* L2 cache controller */
+#define ARRIA10_MPUL2_ADRFLTR_START			(ARRIA10_MPUL2_ADDR + 0xC00)
+
+/* NOC L4 Priv */
+#define ARRIA10_NOC_L4_PRIV_L4_PRIV_L4_PRIV		(ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR + 0x00)
+#define ARRIA10_NOC_L4_PRIV_L4_PRIV_L4_PRIV_SET		(ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR + 0x04)
+#define ARRIA10_NOC_L4_PRIV_L4_PRIV_L4_PRIV_CLR		(ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR + 0x08)
+
+/* NOC L4 Permissions */
+#define ARRIA10_NOC_FW_L4_PER_SCR_NAND_REG		(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x00)
+#define ARRIA10_NOC_FW_L4_PER_SCR_NAND_DATA		(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x04)
+#define ARRIA10_NOC_FW_L4_PER_SCR_QSPI_DATA		(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x08)
+#define ARRIA10_NOC_FW_L4_PER_SCR_USB0_REG		(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x0c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_USB1_REG		(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x10)
+#define ARRIA10_NOC_FW_L4_PER_SCR_DMA_NONSECURE		(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x14)
+#define ARRIA10_NOC_FW_L4_PER_SCR_DMA_SECURE		(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x18)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SPIM0			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x1c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SPIM1			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x20)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SPIS0			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x24)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SPIS1			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x28)
+#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC0			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x2c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC1			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x30)
+#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC2			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x34)
+#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC3			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x38)
+#define ARRIA10_NOC_FW_L4_PER_SCR_QSPI			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x3c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SDMMC			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x40)
+#define ARRIA10_NOC_FW_L4_PER_SCR_GPIO0			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x44)
+#define ARRIA10_NOC_FW_L4_PER_SCR_GPIO1			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x48)
+#define ARRIA10_NOC_FW_L4_PER_SCR_GPIO2			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x4c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_I2C0			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x50)
+#define ARRIA10_NOC_FW_L4_PER_SCR_I2C1			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x54)
+#define ARRIA10_NOC_FW_L4_PER_SCR_I2C2			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x58)
+#define ARRIA10_NOC_FW_L4_PER_SCR_I2C3			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x5c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_I2C4			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x60)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SPTIMER0		(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x64)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SPTIMER1		(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x68)
+#define ARRIA10_NOC_FW_L4_PER_SCR_UART0			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x6c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_UART1			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x70)
+
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN		(ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x00)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN_SET		(ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x04)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN_CLR		(ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x08)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION0		(ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x0c)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION1		(ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x10)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION2		(ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x14)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION3		(ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x18)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION4		(ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x1c)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION5		(ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x20)
+
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_EN		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x00)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_EN_SET		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x04)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_EN_CLR		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x08)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION0		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x0c)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION1		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x10)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION2		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x14)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION3		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x18)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION4		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x1c)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION5		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x20)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION6		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x24)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION7		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x28)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_GLOBAL		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x2c)
+
+#define ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_LWSOC2FPGA	(ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_ADDR + 0x00)
+#define ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_SOC2FPGA	(ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_ADDR + 0x04)
+
+#endif
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h b/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h
new file mode 100644
index 0000000000..ebd2043426
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef	_ARRIA10_RESET_MANAGER_H_
+#define	_ARRIA10_RESET_MANAGER_H_
+
+#define ARRIA10_RSTMGR_STATUS		0x0
+#define ARRIA10_RSTMGR_RAMSTAT		0x4
+#define ARRIA10_RSTMGR_MISCSTAT		0x8
+#define ARRIA10_RSTMGR_CTRL		0xc
+#define ARRIA10_RSTMGR_HDSKEN		0x10
+#define ARRIA10_RSTMGR_HDSKREQ		0x14
+#define ARRIA10_RSTMGR_HDSKACK		0x18
+#define ARRIA10_RSTMGR_COUNTS		0x1c
+#define ARRIA10_RSTMGR_MPUMODRST	0x20
+#define ARRIA10_RSTMGR_PER0MODRST	0x24
+#define ARRIA10_RSTMGR_PER1MODRST	0x28
+#define ARRIA10_RSTMGR_BRGMODRST	0x2c
+#define ARRIA10_RSTMGR_SYSMODRST	0x30
+#define ARRIA10_RSTMGR_COLDMODRST	0x34
+#define ARRIA10_RSTMGR_NRSTMODRST	0x38
+#define ARRIA10_RSTMGR_DBGMODRST	0x3c
+#define ARRIA10_RSTMGR_MPUWARMMASK	0x40
+#define ARRIA10_RSTMGR_PER0WARMMASK	0x44
+#define ARRIA10_RSTMGR_PER1WARMMASK	0x48
+#define ARRIA10_RSTMGR_BRGWARMMASK	0x4c
+#define ARRIA10_RSTMGR_SYSWARMMASK	0x50
+#define ARRIA10_RSTMGR_NRSTWARMMASK	0x54
+#define ARRIA10_RSTMGR_L3WARMMASK	0x58
+#define ARRIA10_RSTMGR_TSTSTA		0x5c
+#define ARRIA10_RSTMGR_TSTSCRATCH	0x60
+#define ARRIA10_RSTMGR_HDSKTIMEOUT	0x64
+#define ARRIA10_RSTMGR_HMCINTR		0x68
+#define ARRIA10_RSTMGR_HMCINTREN	0x6c
+#define ARRIA10_RSTMGR_HMCINTRENS	0x70
+#define ARRIA10_RSTMGR_HMCINTRENR	0x74
+#define ARRIA10_RSTMGR_HMCGPOUT		0x78
+#define ARRIA10_RSTMGR_HMCGPIN		0x7c
+
+#define ARRIA10_RSTMGR_CTL_SWWARMRSTREQ		BIT(1)
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC0		BIT(0)
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC1		BIT(1)
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC2		BIT(2)
+#define ARRIA10_RSTMGR_PER0MODRST_USB0		BIT(3)
+#define ARRIA10_RSTMGR_PER0MODRST_USB1		BIT(4)
+#define ARRIA10_RSTMGR_PER0MODRST_NAND		BIT(5)
+#define ARRIA10_RSTMGR_PER0MODRST_QSPI		BIT(6)
+#define ARRIA10_RSTMGR_PER0MODRST_SDMMC		BIT(7)
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP	BIT(8)
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP	BIT(9)
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP	BIT(10)
+#define ARRIA10_RSTMGR_PER0MODRST_USB0OCP	BIT(11)
+#define ARRIA10_RSTMGR_PER0MODRST_USB1OCP	BIT(12)
+#define ARRIA10_RSTMGR_PER0MODRST_NANDOCP	BIT(13)
+#define ARRIA10_RSTMGR_PER0MODRST_QSPIOCP	BIT(14)
+#define ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP	BIT(15)
+#define ARRIA10_RSTMGR_PER0MODRST_DMA		BIT(16)
+#define ARRIA10_RSTMGR_PER0MODRST_SPIM0		BIT(17)
+#define ARRIA10_RSTMGR_PER0MODRST_SPIM1		BIT(18)
+#define ARRIA10_RSTMGR_PER0MODRST_SPIS0		BIT(19)
+#define ARRIA10_RSTMGR_PER0MODRST_SPIS1		BIT(20)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAOCP	BIT(21)
+#define ARRIA10_RSTMGR_PER0MODRST_EMACPTP	BIT(22)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF0	BIT(24)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF1	BIT(25)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF2	BIT(26)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF3	BIT(27)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF4	BIT(28)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF5	BIT(29)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF6	BIT(30)
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF7	BIT(31)
+
+#define ARRIA10_RSTMGR_PER1MODRST_WATCHDOG0	BIT(0)
+#define ARRIA10_RSTMGR_PER1MODRST_WATCHDOG1	BIT(1)
+#define ARRIA10_RSTMGR_PER1MODRST_L4SYSTIMER0	BIT(2)
+#define ARRIA10_RSTMGR_PER1MODRST_L4SYSTIMER1	BIT(3)
+#define ARRIA10_RSTMGR_PER1MODRST_SPTIMER0	BIT(4)
+#define ARRIA10_RSTMGR_PER1MODRST_SPTIMER1	BIT(5)
+#define ARRIA10_RSTMGR_PER1MODRST_I2C0		BIT(8)
+#define ARRIA10_RSTMGR_PER1MODRST_I2C1		BIT(9)
+#define ARRIA10_RSTMGR_PER1MODRST_I2C2		BIT(10)
+#define ARRIA10_RSTMGR_PER1MODRST_I2C3		BIT(11)
+#define ARRIA10_RSTMGR_PER1MODRST_I2C4		BIT(12)
+#define ARRIA10_RSTMGR_PER1MODRST_UART0		BIT(16)
+#define ARRIA10_RSTMGR_PER1MODRST_UART1		BIT(17)
+#define ARRIA10_RSTMGR_PER1MODRST_GPIO0		BIT(24)
+#define ARRIA10_RSTMGR_PER1MODRST_GPIO1		BIT(25)
+#define ARRIA10_RSTMGR_PER1MODRST_GPIO2		BIT(26)
+
+#define ARRIA10_RSTMGR_BRGMODRST_HPS2FPGA	BIT(0)
+#define ARRIA10_RSTMGR_BRGMODRST_LWHPS2FPGA	BIT(1)
+#define ARRIA10_RSTMGR_BRGMODRST_FPGA2HPS	BIT(2)
+#define ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM0	BIT(3)
+#define ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM1	BIT(4)
+#define ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM2	BIT(5)
+#define ARRIA10_RSTMGR_BRGMODRST_DDRSCH		BIT(6)
+
+#define ARRIA10_RSTMGR_OCP_MASK (ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP |	\
+				 ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP |	\
+				 ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP |	\
+				 ARRIA10_RSTMGR_PER0MODRST_NANDOCP  |	\
+				 ARRIA10_RSTMGR_PER0MODRST_QSPIOCP  |	\
+				 ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP)
+
+void arria10_reset_peripherals(void);
+void arria10_reset_deassert_dedicated_peripherals(void);
+void arria10_reset_deassert_shared_peripherals(void);
+void arria10_reset_deassert_fpga_peripherals(void);
+
+#endif
+
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-sdram.h b/arch/arm/mach-socfpga/include/mach/arria10-sdram.h
new file mode 100644
index 0000000000..07e4dd0130
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/arria10-sdram.h
@@ -0,0 +1,353 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <mach/arria10-system-manager.h>
+
+#ifndef	_ARRIA10_SDRAM_H_
+#define	_ARRIA10_SDRAM_H_
+
+#define ARRIA10_ECC_HMC_OCP_IP_REV_ID			(ARRIA10_SDR_ADDR + 0x00)
+#define ARRIA10_ECC_HMC_OCP_DDRIOCTRL			(ARRIA10_SDR_ADDR + 0x08)
+#define ARRIA10_ECC_HMC_OCP_DDRCALSTAT			(ARRIA10_SDR_ADDR + 0x0c)
+#define ARRIA10_ECC_HMC_OCP_MPR_OBEAT1			(ARRIA10_SDR_ADDR + 0x10)
+#define ARRIA10_ECC_HMC_OCP_MPR_1BEAT1			(ARRIA10_SDR_ADDR + 0x14)
+#define ARRIA10_ECC_HMC_OCP_MPR_2BEAT1			(ARRIA10_SDR_ADDR + 0x18)
+#define ARRIA10_ECC_HMC_OCP_MPR_3BEAT1			(ARRIA10_SDR_ADDR + 0x1c)
+#define ARRIA10_ECC_HMC_OCP_MPR_4BEAT1			(ARRIA10_SDR_ADDR + 0x20)
+#define ARRIA10_ECC_HMC_OCP_MPR_5BEAT1			(ARRIA10_SDR_ADDR + 0x24)
+#define ARRIA10_ECC_HMC_OCP_MPR_6BEAT1			(ARRIA10_SDR_ADDR + 0x28)
+#define ARRIA10_ECC_HMC_OCP_MPR_7BEAT1			(ARRIA10_SDR_ADDR + 0x2c)
+#define ARRIA10_ECC_HMC_OCP_MPR_8BEAT1			(ARRIA10_SDR_ADDR + 0x30)
+#define ARRIA10_ECC_HMC_OCP_MPR_OBEAT2			(ARRIA10_SDR_ADDR + 0x34)
+#define ARRIA10_ECC_HMC_OCP_MPR_1BEAT2			(ARRIA10_SDR_ADDR + 0x38)
+#define ARRIA10_ECC_HMC_OCP_MPR_2BEAT2			(ARRIA10_SDR_ADDR + 0x3c)
+#define ARRIA10_ECC_HMC_OCP_MPR_3BEAT2			(ARRIA10_SDR_ADDR + 0x40)
+#define ARRIA10_ECC_HMC_OCP_MPR_4BEAT2			(ARRIA10_SDR_ADDR + 0x44)
+#define ARRIA10_ECC_HMC_OCP_MPR_5BEAT2			(ARRIA10_SDR_ADDR + 0x48)
+#define ARRIA10_ECC_HMC_OCP_MPR_6BEAT2			(ARRIA10_SDR_ADDR + 0x4c)
+#define ARRIA10_ECC_HMC_OCP_MPR_7BEAT2			(ARRIA10_SDR_ADDR + 0x50)
+#define ARRIA10_ECC_HMC_OCP_MPR_8BEAT2			(ARRIA10_SDR_ADDR + 0x54)
+#define ARRIA10_ECC_HMC_OCP_MPR_AUTO_PRECHARGE		(ARRIA10_SDR_ADDR + 0x60)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL1		(ARRIA10_SDR_ADDR + 0x100)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL2		(ARRIA10_SDR_ADDR + 0x104)
+#define ARRIA10_ECC_HMC_OCP_MPR_ERRINTEN		(ARRIA10_SDR_ADDR + 0x110)
+#define ARRIA10_ECC_HMC_OCP_MPR_ERRINTENS		(ARRIA10_SDR_ADDR + 0x114)
+#define ARRIA10_ECC_HMC_OCP_MPR_ERRINTENR		(ARRIA10_SDR_ADDR + 0x118)
+#define ARRIA10_ECC_HMC_OCP_MPR_INTMODE			(ARRIA10_SDR_ADDR + 0x11c)
+#define ARRIA10_ECC_HMC_OCP_MPR_INTSTAT			(ARRIA10_SDR_ADDR + 0x120)
+#define ARRIA10_ECC_HMC_OCP_MPR_DIAGINTTEST		(ARRIA10_SDR_ADDR + 0x124)
+#define ARRIA10_ECC_HMC_OCP_MPR_MODSTAT			(ARRIA10_SDR_ADDR + 0x128)
+#define ARRIA10_ECC_HMC_OCP_MPR_DERRADDRA		(ARRIA10_SDR_ADDR + 0x12c)
+#define ARRIA10_ECC_HMC_OCP_MPR_SERRADDRA		(ARRIA10_SDR_ADDR + 0x130)
+#define ARRIA10_ECC_HMC_OCP_MPR_AUTOWB_CORRADDR		(ARRIA10_SDR_ADDR + 0x138)
+#define ARRIA10_ECC_HMC_OCP_MPR_SERRCNTREG		(ARRIA10_SDR_ADDR + 0x13c)
+#define ARRIA10_ECC_HMC_OCP_MPR_AUTOWB_DROP_CNTREG	(ARRIA10_SDR_ADDR + 0x140)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2WRECCDATABUS	(ARRIA10_SDR_ADDR + 0x144)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_RDECCDATA2REGBUS	(ARRIA10_SDR_ADDR + 0x148)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDECCDATABUS	(ARRIA10_SDR_ADDR + 0x14c)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_DIAGON		(ARRIA10_SDR_ADDR + 0x150)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_DECSTAT		(ARRIA10_SDR_ADDR + 0x154)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_0	(ARRIA10_SDR_ADDR + 0x160)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_1	(ARRIA10_SDR_ADDR + 0x164)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_2	(ARRIA10_SDR_ADDR + 0x168)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_3	(ARRIA10_SDR_ADDR + 0x16c)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT0	(ARRIA10_SDR_ADDR + 0x170)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT1	(ARRIA10_SDR_ADDR + 0x174)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT2	(ARRIA10_SDR_ADDR + 0x178)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT3	(ARRIA10_SDR_ADDR + 0x17c)
+
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_ID_COREID		(ARRIA10_SDR_SCHEDULER_ADDR + 0x00)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_ID_REVISIONID		(ARRIA10_SDR_SCHEDULER_ADDR + 0x04)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRCONF		(ARRIA10_SDR_SCHEDULER_ADDR + 0x08)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRTIMING		(ARRIA10_SDR_SCHEDULER_ADDR + 0x0c)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRMODE		(ARRIA10_SDR_SCHEDULER_ADDR + 0x10)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_READLATENCY		(ARRIA10_SDR_SCHEDULER_ADDR + 0x14)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_ACTIVATE		(ARRIA10_SDR_SCHEDULER_ADDR + 0x38)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DEVTODEV		(ARRIA10_SDR_SCHEDULER_ADDR + 0x3c)
+
+#define ARRIA10_IO48_HMC_MMR_DBGCFG0		(ARRIA10_HMC_MMR_IO48_ADDR + 0x00)
+#define ARRIA10_IO48_HMC_MMR_DBGCFG1		(ARRIA10_HMC_MMR_IO48_ADDR + 0x04)
+#define ARRIA10_IO48_HMC_MMR_DBGCFG2		(ARRIA10_HMC_MMR_IO48_ADDR + 0x08)
+#define ARRIA10_IO48_HMC_MMR_DBGCFG3		(ARRIA10_HMC_MMR_IO48_ADDR + 0x0c)
+#define ARRIA10_IO48_HMC_MMR_DBGCFG4		(ARRIA10_HMC_MMR_IO48_ADDR + 0x10)
+#define ARRIA10_IO48_HMC_MMR_DBGCFG5		(ARRIA10_HMC_MMR_IO48_ADDR + 0x14)
+#define ARRIA10_IO48_HMC_MMR_DBGCFG6		(ARRIA10_HMC_MMR_IO48_ADDR + 0x18)
+#define ARRIA10_IO48_HMC_MMR_RESERVE0		(ARRIA10_HMC_MMR_IO48_ADDR + 0x1c)
+#define ARRIA10_IO48_HMC_MMR_RESERVE1		(ARRIA10_HMC_MMR_IO48_ADDR + 0x20)
+#define ARRIA10_IO48_HMC_MMR_RESERVE2		(ARRIA10_HMC_MMR_IO48_ADDR + 0x24)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG0		(ARRIA10_HMC_MMR_IO48_ADDR + 0x28)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG1		(ARRIA10_HMC_MMR_IO48_ADDR + 0x2c)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG2		(ARRIA10_HMC_MMR_IO48_ADDR + 0x30)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG3		(ARRIA10_HMC_MMR_IO48_ADDR + 0x34)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG4		(ARRIA10_HMC_MMR_IO48_ADDR + 0x38)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG5		(ARRIA10_HMC_MMR_IO48_ADDR + 0x3c)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG6		(ARRIA10_HMC_MMR_IO48_ADDR + 0x40)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG7		(ARRIA10_HMC_MMR_IO48_ADDR + 0x44)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG8		(ARRIA10_HMC_MMR_IO48_ADDR + 0x48)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG9		(ARRIA10_HMC_MMR_IO48_ADDR + 0x4c)
+#define ARRIA10_IO48_HMC_MMR_DRAMTIMING0	(ARRIA10_HMC_MMR_IO48_ADDR + 0x50)
+#define ARRIA10_IO48_HMC_MMR_DRAMODT0		(ARRIA10_HMC_MMR_IO48_ADDR + 0x54)
+#define ARRIA10_IO48_HMC_MMR_DRAMODT1		(ARRIA10_HMC_MMR_IO48_ADDR + 0x58)
+#define ARRIA10_IO48_HMC_MMR_SBCFG0		(ARRIA10_HMC_MMR_IO48_ADDR + 0x5c)
+#define ARRIA10_IO48_HMC_MMR_SBCFG1		(ARRIA10_HMC_MMR_IO48_ADDR + 0x60)
+#define ARRIA10_IO48_HMC_MMR_SBCFG2		(ARRIA10_HMC_MMR_IO48_ADDR + 0x64)
+#define ARRIA10_IO48_HMC_MMR_SBCFG3		(ARRIA10_HMC_MMR_IO48_ADDR + 0x68)
+#define ARRIA10_IO48_HMC_MMR_SBCFG4		(ARRIA10_HMC_MMR_IO48_ADDR + 0x6c)
+#define ARRIA10_IO48_HMC_MMR_SBCFG5		(ARRIA10_HMC_MMR_IO48_ADDR + 0x70)
+#define ARRIA10_IO48_HMC_MMR_SBCFG6		(ARRIA10_HMC_MMR_IO48_ADDR + 0x74)
+#define ARRIA10_IO48_HMC_MMR_SBCFG7		(ARRIA10_HMC_MMR_IO48_ADDR + 0x78)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING0		(ARRIA10_HMC_MMR_IO48_ADDR + 0x7c)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING1		(ARRIA10_HMC_MMR_IO48_ADDR + 0x80)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING2		(ARRIA10_HMC_MMR_IO48_ADDR + 0x84)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING3		(ARRIA10_HMC_MMR_IO48_ADDR + 0x88)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING4		(ARRIA10_HMC_MMR_IO48_ADDR + 0x8c)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING5		(ARRIA10_HMC_MMR_IO48_ADDR + 0x90)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING6		(ARRIA10_HMC_MMR_IO48_ADDR + 0x94)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING7		(ARRIA10_HMC_MMR_IO48_ADDR + 0x98)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING8		(ARRIA10_HMC_MMR_IO48_ADDR + 0x9c)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING9		(ARRIA10_HMC_MMR_IO48_ADDR + 0xa0)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING10	(ARRIA10_HMC_MMR_IO48_ADDR + 0xa4)
+#define ARRIA10_IO48_HMC_MMR_DRAMADDRW		(ARRIA10_HMC_MMR_IO48_ADDR + 0xa8)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND0		(ARRIA10_HMC_MMR_IO48_ADDR + 0xac)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND1		(ARRIA10_HMC_MMR_IO48_ADDR + 0xb0)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND2		(ARRIA10_HMC_MMR_IO48_ADDR + 0xb4)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND3		(ARRIA10_HMC_MMR_IO48_ADDR + 0xb8)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND4		(ARRIA10_HMC_MMR_IO48_ADDR + 0xbc)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND5		(ARRIA10_HMC_MMR_IO48_ADDR + 0xc0)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND6		(ARRIA10_HMC_MMR_IO48_ADDR + 0xc4)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND7		(ARRIA10_HMC_MMR_IO48_ADDR + 0xc8)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND8		(ARRIA10_HMC_MMR_IO48_ADDR + 0xcc)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND9		(ARRIA10_HMC_MMR_IO48_ADDR + 0xd0)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND10		(ARRIA10_HMC_MMR_IO48_ADDR + 0xd4)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND11		(ARRIA10_HMC_MMR_IO48_ADDR + 0xd8)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND12		(ARRIA10_HMC_MMR_IO48_ADDR + 0xdc)
+#define ARRIA10_IO48_HMC_MMR_SIDEBANB13		(ARRIA10_HMC_MMR_IO48_ADDR + 0xe0)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND14		(ARRIA10_HMC_MMR_IO48_ADDR + 0xe4)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND15		(ARRIA10_HMC_MMR_IO48_ADDR + 0xe8)
+#define ARRIA10_IO48_HMC_MMR_DRAMSTS		(ARRIA10_HMC_MMR_IO48_ADDR + 0xec)
+#define ARRIA10_IO48_HMC_MMR_DBGDONE		(ARRIA10_HMC_MMR_IO48_ADDR + 0xf0)
+#define ARRIA10_IO48_HMC_MMR_DBGSIGNALS		(ARRIA10_HMC_MMR_IO48_ADDR + 0xf4)
+#define ARRIA10_IO48_HMC_MMR_DBGRESET		(ARRIA10_HMC_MMR_IO48_ADDR + 0xf8)
+#define ARRIA10_IO48_HMC_MMR_DBGMATCH		(ARRIA10_HMC_MMR_IO48_ADDR + 0xfc)
+#define ARRIA10_IO48_HMC_MMR_COUNTER0MASK	(ARRIA10_HMC_MMR_IO48_ADDR + 0x100)
+#define ARRIA10_IO48_HMC_MMR_COUNTER1MASK	(ARRIA10_HMC_MMR_IO48_ADDR + 0x104)
+#define ARRIA10_IO48_HMC_MMR_COUNTER0MATCH	(ARRIA10_HMC_MMR_IO48_ADDR + 0x108)
+#define ARRIA10_IO48_HMC_MMR_COUNTER1MATCH	(ARRIA10_HMC_MMR_IO48_ADDR + 0x10c)
+#define ARRIA10_IO48_HMC_MMR_NIOSRESERVE0	(ARRIA10_HMC_MMR_IO48_ADDR + 0x110)
+#define ARRIA10_IO48_HMC_MMR_NIOSRESERVE1	(ARRIA10_HMC_MMR_IO48_ADDR + 0x114)
+#define ARRIA10_IO48_HMC_MMR_NIOSRESERVE2	(ARRIA10_HMC_MMR_IO48_ADDR + 0x118)
+
+union dramaddrw_reg {
+	struct {
+		u32 cfg_col_addr_width:5;
+		u32 cfg_row_addr_width:5;
+		u32 cfg_bank_addr_width:4;
+		u32 cfg_bank_group_addr_width:2;
+		u32 cfg_cs_addr_width:3;
+		u32 reserved:13;
+	};
+	u32 word;
+};
+
+union ctrlcfg0_reg {
+	struct {
+		u32 cfg_mem_type:4;
+		u32 cfg_dimm_type:3;
+		u32 cfg_ac_pos:2;
+		u32 cfg_ctrl_burst_len:5;
+		u32 reserved:18;  /* Other fields unused */
+	};
+	u32 word;
+};
+
+union ctrlcfg1_reg {
+	struct {
+		u32 cfg_dbc3_burst_len:5;
+		u32 cfg_addr_order:2;
+		u32 cfg_ctrl_enable_ecc:1;
+		u32 reserved:24;  /* Other fields unused */
+	};
+	u32 word;
+};
+
+union caltiming0_reg {
+	struct {
+		u32 cfg_act_to_rdwr:6;
+		u32 cfg_act_to_pch:6;
+		u32 cfg_act_to_act:6;
+		u32 cfg_act_to_act_db:6;
+		u32 reserved:8;  /* Other fields unused */
+	};
+	u32 word;
+};
+
+union caltiming1_reg {
+	struct {
+		u32 cfg_rd_to_rd:6;
+		u32 cfg_rd_to_rd_dc:6;
+		u32 cfg_rd_to_rd_db:6;
+		u32 cfg_rd_to_wr:6;
+		u32 cfg_rd_to_wr_dc:6;
+		u32 reserved:2;
+	};
+	u32 word;
+};
+
+union caltiming2_reg {
+	struct {
+		u32 cfg_rd_to_wr_db:6;
+		u32 cfg_rd_to_pch:6;
+		u32 cfg_rd_ap_to_valid:6;
+		u32 cfg_wr_to_wr:6;
+		u32 cfg_wr_to_wr_dc:6;
+		u32 reserved:2;
+	};
+	u32 word;
+};
+
+union caltiming3_reg {
+	struct {
+		u32 cfg_wr_to_wr_db:6;
+		u32 cfg_wr_to_rd:6;
+		u32 cfg_wr_to_rd_dc:6;
+		u32 cfg_wr_to_rd_db:6;
+		u32 cfg_wr_to_pch:6;
+		u32 reserved:2;
+	};
+	u32 word;
+};
+
+union caltiming4_reg {
+	struct {
+		u32 cfg_wr_ap_to_valid:6;
+		u32 cfg_pch_to_valid:6;
+		u32 cfg_pch_all_to_valid:6;
+		u32 cfg_arf_to_valid:8;
+		u32 cfg_pdn_to_valid:6;
+	};
+	u32 word;
+};
+
+union caltiming9_reg {
+	struct {
+		u32 cfg_4_act_to_act:8;
+		u32 reserved:24;
+	};
+	u32 word;
+};
+
+#define IRQ_ECC_SERR						34
+#define IRQ_ECC_DERR						32
+
+#define ARRIA10_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE			0x00000001
+
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_SERRPENA			0x00000001
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_DERRPENA			0x00000002
+#define ARRIA10_ECC_HMC_OCP_ERRINTEN_SERRINTEN			0x00000001
+#define ARRIA10_ECC_HMC_OCP_ERRINTEN_DERRINTEN			0x00000002
+#define ARRIA10_ECC_HMC_OCP_INTMOD_INTONCMP			0x00010000
+#define ARRIA10_ECC_HMC_OCP_INTMOD_SERR				0x00000001
+#define ARRIA10_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY		0x00000100
+#define ARRIA10_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST			0x00010000
+#define ARRIA10_ECC_HMC_OCP_ECCCTL_CNT_RST			0x00000100
+#define ARRIA10_ECC_HMC_OCP_ECCCTL_ECC_EN			0x00000000
+#define ARRIA10_ECC_HMC_OCP_ECCCTL2_RMW_EN			0x00000100
+#define ARRIA10_ECC_HMC_OCP_ECCCTL2_AWB_EN			0x00000001
+#define ARRIA10_ECC_HMC_OCP_ERRINTEN_SERR			0x00000001
+#define ARRIA10_ECC_HMC_OCP_ERRINTEN_DERR			0x00000002
+#define ARRIA10_ECC_HMC_OCP_ERRINTEN_HMI			0x00000004
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_SERR			0x00000001
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_DERR			0x00000002
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_HMI				0x00000004
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG			0x00010000
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_ADDRPARFLG			0x00020000
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_DERRBUSFLG			0x00040000
+
+#define ARRIA10_ECC_HMC_OCP_SERRCNTREG_VALUE			8
+
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB	22
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB	0
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB	0
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB	2
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB	6
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB	15
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB	0
+
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_LSB	0
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB	0
+
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB		4
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB		13
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB	4
+
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB	4
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB	6
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB	6
+
+#define ARRIA10_SDR_FW_MPU_FPGA_EN			(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x00)
+#define ARRIA10_SDR_FW_MPU_FPGA_EN_SET			(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x04)
+#define ARRIA10_SDR_FW_MPU_FPGA_EN_CLR			(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x08)
+#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION0ADDR		(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x10)
+#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION1ADDR		(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x14)
+#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION2ADDR		(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x18)
+#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION3ADDR		(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x1c)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION0ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x20)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION1ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x24)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION2ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x28)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION3ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x2c)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION0ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x30)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION1ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x34)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION2ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x38)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION3ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x3c)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION0ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x40)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION1ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x44)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION2ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x48)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION3ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x4c)
+
+#define ARRIA10_NOC_FW_DDR_MPU_MPUREG0EN		BIT(0)
+#define ARRIA10_NOC_FW_DDR_MPU_MPUREG1EN		BIT(1)
+#define ARRIA10_NOC_FW_DDR_MPU_MPUREG2EN		BIT(2)
+#define ARRIA10_NOC_FW_DDR_MPU_MPUREG3EN		BIT(3)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG0EN		BIT(4)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG1EN		BIT(5)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG2EN		BIT(6)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG3EN		BIT(7)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG0EN		BIT(8)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG1EN		BIT(9)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG2EN		BIT(10)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG3EN		BIT(11)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG0EN		BIT(12)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG1EN		BIT(13)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG2EN		BIT(14)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG3EN		BIT(15)
+
+#define ARRIA10_NOC_FW_DDR_L3_EN			(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x00)
+#define ARRIA10_NOC_FW_DDR_L3_EN_SET			(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x04)
+#define ARRIA10_NOC_FW_DDR_L3_EN_CLR			(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x08)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION0ADDR		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x0c)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION1ADDR		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x10)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION2ADDR		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x14)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION3ADDR		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x18)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION4ADDR		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x1c)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION5ADDR		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x20)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION6ADDR		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x24)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION7ADDR		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x28)
+#define ARRIA10_NOC_FW_DDR_L3_GLOBAL			(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x2c)
+
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG0EN			BIT(0)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG1EN			BIT(1)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG2EN			BIT(2)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG3EN			BIT(3)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG4EN			BIT(4)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG5EN			BIT(5)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG6EN			BIT(6)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG7EN			BIT(7)
+
+#define ARRIA10_IO48_DRAMTIME_MEM_READ_LATENCY		0x0000003f
+
+int arria10_ddr_calibration_sequence(void);
+
+#endif
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-system-manager.h b/arch/arm/mach-socfpga/include/mach/arria10-system-manager.h
new file mode 100644
index 0000000000..f98cc36c76
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/arria10-system-manager.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef	_ARRIA10_SYSTEM_MANAGER_H_
+#define	_ARRIA10_SYSTEM_MANAGER_H_
+
+#include <mach/arria10-regs.h>
+
+#define ARRIA10_SYSMGR_SILICONID1		(ARRIA10_SYSMGR_ADDR + 0x00)
+#define ARRIA10_SYSMGR_SILICONID2		(ARRIA10_SYSMGR_ADDR + 0x04)
+#define ARRIA10_SYSMGR_WDDBG			(ARRIA10_SYSMGR_ADDR + 0x08)
+#define ARRIA10_SYSMGR_BOOTINFO			(ARRIA10_SYSMGR_ADDR + 0x0c)
+#define ARRIA10_SYSMGR_MPU_CTRL_L2_ECC		(ARRIA10_SYSMGR_ADDR + 0x10)
+#define ARRIA10_SYSMGR_DMA			(ARRIA10_SYSMGR_ADDR + 0x20)
+#define ARRIA10_SYSMGR_DMA_PERIPH		(ARRIA10_SYSMGR_ADDR + 0x24)
+#define ARRIA10_SYSMGR_SDMMC			(ARRIA10_SYSMGR_ADDR + 0x28)
+#define ARRIA10_SYSMGR_SDMMC_L3MASTER		(ARRIA10_SYSMGR_ADDR + 0x2c)
+#define ARRIA10_SYSMGR_NAND_BOOTSTRAP		(ARRIA10_SYSMGR_ADDR + 0x30)
+#define ARRIA10_SYSMGR_NAND_L3MASTER		(ARRIA10_SYSMGR_ADDR + 0x34)
+#define ARRIA10_SYSMGR_USB0_L3MASTER		(ARRIA10_SYSMGR_ADDR + 0x38)
+#define ARRIA10_SYSMGR_USB1_L3MASTER		(ARRIA10_SYSMGR_ADDR + 0x3c)
+#define ARRIA10_SYSMGR_EMAC_GLOBAL		(ARRIA10_SYSMGR_ADDR + 0x40)
+#define ARRIA10_SYSMGR_EMAC0			(ARRIA10_SYSMGR_ADDR + 0x44)
+#define ARRIA10_SYSMGR_EMAC1			(ARRIA10_SYSMGR_ADDR + 0x48)
+#define ARRIA10_SYSMGR_EMAC2			(ARRIA10_SYSMGR_ADDR + 0x4c)
+#define ARRIA10_SYSMGR_FPGAINTF_GLOBAL		(ARRIA10_SYSMGR_ADDR + 0x60)
+#define ARRIA10_SYSMGR_FPGAINTF_EN_0		(ARRIA10_SYSMGR_ADDR + 0x64)
+#define ARRIA10_SYSMGR_FPGAINTF_EN_1		(ARRIA10_SYSMGR_ADDR + 0x68)
+#define ARRIA10_SYSMGR_FPGAINTF_EN_2		(ARRIA10_SYSMGR_ADDR + 0x6c)
+#define ARRIA10_SYSMGR_FPGAINTF_EN_3		(ARRIA10_SYSMGR_ADDR + 0x70)
+#define ARRIA10_SYSMGR_NOC_ADDR_REMAP_VALUE 	(ARRIA10_SYSMGR_ADDR + 0x80)
+#define ARRIA10_SYSMGR_NOC_ADDR_REMAP_SET 	(ARRIA10_SYSMGR_ADDR + 0x84)
+#define ARRIA10_SYSMGR_NOC_ADDR_REMAP_CLEAR 	(ARRIA10_SYSMGR_ADDR + 0x88)
+#define ARRIA10_SYSMGR_ECC_INTMASK_VALUE 	(ARRIA10_SYSMGR_ADDR + 0x90)
+#define ARRIA10_SYSMGR_ECC_INTMASK_SET 		(ARRIA10_SYSMGR_ADDR + 0x94)
+#define ARRIA10_SYSMGR_ECC_INTMASK_CLR 		(ARRIA10_SYSMGR_ADDR + 0x98)
+#define ARRIA10_SYSMGR_ECC_INTSTATUS_SERR 	(ARRIA10_SYSMGR_ADDR + 0x9c)
+#define ARRIA10_SYSMGR_ECC_INTSTATUS_DERR 	(ARRIA10_SYSMGR_ADDR + 0xa0)
+#define ARRIA10_SYSMGR_MPU_STATUS_L2_ECC 	(ARRIA10_SYSMGR_ADDR + 0xa4)
+#define ARRIA10_SYSMGR_MPU_CLEAR_L2_ECC 	(ARRIA10_SYSMGR_ADDR + 0xa8)
+#define ARRIA10_SYSMGR_MPU_STATUS_L1_PARITY 	(ARRIA10_SYSMGR_ADDR + 0xac)
+#define ARRIA10_SYSMGR_MPU_CLEAR_L1_PARITY 	(ARRIA10_SYSMGR_ADDR + 0xb0)
+#define ARRIA10_SYSMGR_MPU_SET_L1_PARITY 	(ARRIA10_SYSMGR_ADDR + 0xb4)
+#define ARRIA10_SYSMGR_NOC_TIMEOUT 		(ARRIA10_SYSMGR_ADDR + 0xc0)
+#define ARRIA10_SYSMGR_NOC_IDLEREQ_SET		(ARRIA10_SYSMGR_ADDR + 0xc4)
+#define ARRIA10_SYSMGR_NOC_IDLEREQ_CLR		(ARRIA10_SYSMGR_ADDR + 0xc8)
+#define ARRIA10_SYSMGR_NOC_IDLEREQ_VALUE	(ARRIA10_SYSMGR_ADDR + 0xcc)
+#define ARRIA10_SYSMGR_NOC_IDLEACK		(ARRIA10_SYSMGR_ADDR + 0xd0)
+#define ARRIA10_SYSMGR_NOC_IDLESTATUS		(ARRIA10_SYSMGR_ADDR + 0xd4)
+#define ARRIA10_SYSMGR_FPGA2SOC_CTRL		(ARRIA10_SYSMGR_ADDR + 0xd8)
+
+/* pin mux */
+#define ARRIA10_SYSMGR_PINMUXGRP		(ARRIA10_SYSMGR_ADDR + 0x400)
+#define ARRIA10_SYSMGR_PINMUXGRP_NANDUSEFPGA	(ARRIA10_SYSMGR_PINMUXGRP + 0x2F0)
+#define ARRIA10_SYSMGR_PINMUXGRP_EMAC1USEFPGA	(ARRIA10_SYSMGR_PINMUXGRP + 0x2F8)
+#define ARRIA10_SYSMGR_PINMUXGRP_SDMMCUSEFPGA	(ARRIA10_SYSMGR_PINMUXGRP + 0x308)
+#define ARRIA10_SYSMGR_PINMUXGRP_EMAC0USEFPGA	(ARRIA10_SYSMGR_PINMUXGRP + 0x314)
+#define ARRIA10_SYSMGR_PINMUXGRP_SPIM1USEFPGA	(ARRIA10_SYSMGR_PINMUXGRP + 0x330)
+#define ARRIA10_SYSMGR_PINMUXGRP_SPIM0USEFPGA	(ARRIA10_SYSMGR_PINMUXGRP + 0x338)
+
+/* bit fields */
+#define ARRIA10_SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX		BIT(0)
+#define ARRIA10_SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO		BIT(1)
+#define ARRIA10_SYSMGR_ECC_OCRAM_EN				BIT(0)
+#define ARRIA10_SYSMGR_ECC_OCRAM_SERR				BIT(3)
+#define ARRIA10_SYSMGR_ECC_OCRAM_DERR				BIT(4)
+#define ARRIA10_SYSMGR_FPGAINTF_USEFPGA				BIT(1)
+#define ARRIA10_SYSMGR_FPGAINTF_SPIM0				BIT(0)
+#define ARRIA10_SYSMGR_FPGAINTF_SPIM1				BIT(1)
+#define ARRIA10_SYSMGR_FPGAINTF_EMAC0				BIT(2)
+#define ARRIA10_SYSMGR_FPGAINTF_EMAC1				BIT(3)
+#define ARRIA10_SYSMGR_FPGAINTF_NAND				BIT(4)
+#define ARRIA10_SYSMGR_FPGAINTF_SDMMC				BIT(5)
+
+#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	0x0
+#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII		0x1
+#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII		0x2
+#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_LSB			0
+#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_MASK			0x00000003
+
+#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC0	BIT(0)
+#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC0_SW	BIT(4)
+#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC1	BIT(8)
+#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC1_SW	BIT(12)
+#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC2	BIT(16)
+#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC2_SW	BIT(20)
+
+#define ARRIA10_SYSMGR_SDMMC_SMPLSEL(smplsel)	(((smplsel) & 0x7) << 4)
+#define ARRIA10_SYSMGR_SDMMC_DRVSEL(drvsel)	((drvsel) & 0x7)
+
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)	\
+	((drvsel << 0) & 0x7) | ((smplsel << 4) & 0x70)
+
+#endif
diff --git a/arch/arm/mach-socfpga/include/mach/barebox-arm-head.h b/arch/arm/mach-socfpga/include/mach/barebox-arm-head.h
new file mode 100644
index 0000000000..28fb1c92fc
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/barebox-arm-head.h
@@ -0,0 +1,42 @@
+static inline void __barebox_arm_head(void)
+{
+	__asm__ __volatile__ (
+#ifdef CONFIG_THUMB2_BAREBOX
+		".arm\n"
+		"adr r9, 1f + 1\n"
+		"bx r9\n"
+		".thumb\n"
+		"1:\n"
+		"bl 2f\n"
+		".rept 10\n"
+		"1: b 1b\n"
+		".endr\n"
+#else
+		"b 2f\n"
+		"1: b 1b\n"
+		"1: b 1b\n"
+		"1: b 1b\n"
+		"1: b 1b\n"
+		"1: b 1b\n"
+		"1: b 1b\n"
+		"1: b 1b\n"
+#endif
+		".asciz \"barebox\"\n"
+		".word _text\n"				/* text base. If copied there,
+							 * barebox can skip relocation
+							 */
+		".word _barebox_image_size\n"		/* image size to copy */
+
+		".rept 10\n"
+		".word 0x55555555\n"
+		".endr\n"
+		"2:\n"
+	);
+}
+static inline void barebox_arm_head(void)
+{
+	__barebox_arm_head();
+	__asm__ __volatile__ (
+		"b barebox_arm_reset_vector\n"
+	);
+}
diff --git a/arch/arm/mach-socfpga/include/mach/debug_ll.h b/arch/arm/mach-socfpga/include/mach/debug_ll.h
index 4e906ea66e..f41258c504 100644
--- a/arch/arm/mach-socfpga/include/mach/debug_ll.h
+++ b/arch/arm/mach-socfpga/include/mach/debug_ll.h
@@ -53,6 +53,17 @@ static inline void INIT_LL(void)
 	writel(FCRVAL, UART_BASE + FCR);
 }
 
+#ifdef CONFIG_ARCH_SOCFPGA_ARRIA10
+static inline void PUTC_LL(char c)
+{
+	/* Wait until there is space in the FIFO */
+	while ((readl(UART_BASE + LSR) & LSR_THRE) == 0);
+	/* Send the character */
+	writel(c, UART_BASE + THR);
+	/* Wait to make sure it hits the line, in case we die too soon. */
+	while ((readl(UART_BASE + LSR) & LSR_THRE) == 0);
+}
+#else
 static inline void PUTC_LL(char c)
 {
 	/* Wait until there is space in the FIFO */
@@ -62,6 +73,7 @@ static inline void PUTC_LL(char c)
 	/* Wait to make sure it hits the line, in case we die too soon. */
 	while ((readb(UART_BASE + LSR) & LSR_THRE) == 0);
 }
+#endif
 
 #else
 static inline unsigned int ns16550_calc_divisor(unsigned int clk,
diff --git a/arch/arm/mach-socfpga/include/mach/generic.h b/arch/arm/mach-socfpga/include/mach/generic.h
index 2a7e0ea499..9d6dd1f26c 100644
--- a/arch/arm/mach-socfpga/include/mach/generic.h
+++ b/arch/arm/mach-socfpga/include/mach/generic.h
@@ -1,13 +1,49 @@
 #ifndef __MACH_SOCFPGA_GENERIC_H
 #define __MACH_SOCFPGA_GENERIC_H
 
+#include <linux/types.h>
+
 struct socfpga_cm_config;
 
 struct socfpga_io_config;
 
+struct arria10_mainpll_cfg;
+struct arria10_perpll_cfg;
+struct arria10_pinmux_cfg;
+
+void arria10_init(struct arria10_mainpll_cfg *mainpll,
+		  struct arria10_perpll_cfg *perpll, uint32_t *pinmux);
+
 void socfpga_lowlevel_init(struct socfpga_cm_config *cm_config,
 			   struct socfpga_io_config *io_config);
 
+#if defined(CONFIG_ARCH_SOCFPGA_CYCLONE5)
+void socfpga_cyclone5_mmc_init(void);
+void socfpga_cyclone5_uart_init(void);
+void socfpga_cyclone5_timer_init(void);
+void socfpga_cyclone5_qspi_init(void);
+#else
+static inline void socfpga_cyclone5_mmc_init(void)
+{
+	return;
+}
+
+static inline void socfpga_cyclone5_uart_init(void)
+{
+	return;
+}
+
+static inline void socfpga_cyclone5_timer_init(void)
+{
+	return;
+}
+
+static inline void socfpga_cyclone5_qspi_init(void)
+{
+	return;
+}
+#endif
+
 static inline void __udelay(unsigned us)
 {
 	volatile unsigned int i;
diff --git a/arch/arm/mach-socfpga/xload.c b/arch/arm/mach-socfpga/xload.c
index 5d47bb9d3e..ee7d194427 100644
--- a/arch/arm/mach-socfpga/xload.c
+++ b/arch/arm/mach-socfpga/xload.c
@@ -1,8 +1,5 @@
-#include <platform_data/cadence_qspi.h>
-#include <platform_data/dw_mmc.h>
 #include <bootsource.h>
 #include <bootstrap.h>
-#include <platform_data/serial-ns16550.h>
 #include <common.h>
 #include <malloc.h>
 #include <init.h>
@@ -10,7 +7,6 @@
 #include <linux/sizes.h>
 #include <fs.h>
 #include <io.h>
-#include <mci.h>
 
 #include <linux/clkdev.h>
 #include <linux/stat.h>
@@ -30,84 +26,6 @@ static struct socfpga_barebox_part default_parts[] = {
 };
 const struct socfpga_barebox_part *barebox_parts = default_parts;
 
-enum socfpga_clks {
-	timer, mmc, qspi_clk, uart, clk_max
-};
-
-static struct clk *clks[clk_max];
-
-static struct dw_mmc_platform_data mmc_pdata = {
-	.bus_width_caps = MMC_CAP_4_BIT_DATA,
-	.ciu_div = 3,
-};
-
-static void socfpga_mmc_init(void)
-{
-	clks[mmc] = clk_fixed("mmc", 400000000);
-	clkdev_add_physbase(clks[mmc], CYCLONE5_SDMMC_ADDRESS, NULL);
-	add_generic_device("dw_mmc", 0, NULL, CYCLONE5_SDMMC_ADDRESS, SZ_4K,
-			IORESOURCE_MEM, &mmc_pdata);
-}
-
-#if defined(CONFIG_SPI_CADENCE_QUADSPI)
-static struct cadence_qspi_platform_data qspi_pdata = {
-	.ext_decoder = 0,
-	.fifo_depth = 128,
-};
-
-static __maybe_unused void add_cadence_qspi_device(int id, resource_size_t ctrl,
-				    resource_size_t data, void *pdata)
-{
-	struct resource *res;
-
-	res = xzalloc(sizeof(struct resource) * 2);
-	res[0].start = ctrl;
-	res[0].end = ctrl + 0x100 - 1;
-	res[0].flags = IORESOURCE_MEM;
-	res[1].start = data;
-	res[1].end = data + 0x100 - 1;
-	res[1].flags = IORESOURCE_MEM;
-
-	add_generic_device_res("cadence_qspi", id, res, 2, pdata);
-}
-
-static __maybe_unused void socfpga_qspi_init(void)
-{
-	clks[qspi_clk] = clk_fixed("qspi_clk", 370000000);
-	clkdev_add_physbase(clks[qspi_clk], CYCLONE5_QSPI_CTRL_ADDRESS, NULL);
-	clkdev_add_physbase(clks[qspi_clk], CYCLONE5_QSPI_DATA_ADDRESS, NULL);
-	add_cadence_qspi_device(0, CYCLONE5_QSPI_CTRL_ADDRESS,
-				CYCLONE5_QSPI_DATA_ADDRESS, &qspi_pdata);
-}
-#else
-static void socfpga_qspi_init(void)
-{
-	return;
-}
-#endif
-
-static struct NS16550_plat uart_pdata = {
-	.clock = 100000000,
-	.shift = 2,
-};
-
-static void socfpga_uart_init(void)
-{
-	clks[uart] = clk_fixed("uart", 100000000);
-	clkdev_add_physbase(clks[uart], CYCLONE5_UART0_ADDRESS, NULL);
-	clkdev_add_physbase(clks[uart], CYCLONE5_UART1_ADDRESS, NULL);
-	add_ns16550_device(0, 0xffc02000, 1024, IORESOURCE_MEM |
-			IORESOURCE_MEM_8BIT, &uart_pdata);
-}
-
-static void socfpga_timer_init(void)
-{
-	clks[timer] = clk_fixed("timer", 200000000);
-	clkdev_add_physbase(clks[timer], CYCLONE5_SMP_TWD_ADDRESS, NULL);
-	add_generic_device("smp_twd", 0, NULL, CYCLONE5_SMP_TWD_ADDRESS, 0x100,
-			IORESOURCE_MEM, NULL);
-}
-
 static __noreturn int socfpga_xload(void)
 {
 	enum bootsource bootsource = bootsource_get();
@@ -116,7 +34,7 @@ static __noreturn int socfpga_xload(void)
 
 	switch (bootsource) {
 	case BOOTSOURCE_MMC:
-		socfpga_mmc_init();
+		socfpga_cyclone5_mmc_init();
 
 		for (part = barebox_parts; part->mmc_disk; part++) {
 			buf = bootstrap_read_disk(barebox_parts->mmc_disk, "fat");
@@ -132,8 +50,7 @@ static __noreturn int socfpga_xload(void)
 		}
 		break;
 	case BOOTSOURCE_SPI:
-		socfpga_qspi_init();
-
+		socfpga_cyclone5_qspi_init();
 		for (part = barebox_parts; part->nor_size; part++) {
 			buf = bootstrap_read_devfs("mtd0", false,
 					part->nor_offset, part->nor_size, SZ_1M);
@@ -142,7 +59,6 @@ static __noreturn int socfpga_xload(void)
 					part->nor_offset);
 				continue;
 			}
-
 			break;
 		}
 
@@ -167,8 +83,8 @@ static __noreturn int socfpga_xload(void)
 static int socfpga_devices_init(void)
 {
 	barebox_set_model("SoCFPGA");
-	socfpga_timer_init();
-	socfpga_uart_init();
+	socfpga_cyclone5_timer_init();
+	socfpga_cyclone5_uart_init();
 
 	barebox_main = socfpga_xload;