ARM: socfpga: make debug_ll configurable

Allow configuring the serial port and clock rate
instead of hardcoding it.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 44 insertions, 25 deletions

diff --git a/arch/arm/mach-socfpga/include/mach/debug_ll.h b/arch/arm/mach-socfpga/include/mach/debug_ll.h
index f378435970..4e906ea66e 100644
--- a/arch/arm/mach-socfpga/include/mach/debug_ll.h
+++ b/arch/arm/mach-socfpga/include/mach/debug_ll.h
@@ -2,24 +2,33 @@
 #define   __MACH_DEBUG_LL_H__
 
 #include <io.h>
+#include <errno.h>
 
-#define UART_BASE	0xffc02000
+#ifdef CONFIG_DEBUG_LL
+#define UART_BASE	CONFIG_DEBUG_SOCFPGA_UART_PHYS_ADDR
+#endif
 
 #define LSR_THRE	0x20	/* Xmit holding register empty */
-#define LSR		(5 << 2)
-#define THR		(0 << 2)
+#define LSR_TEMT	0x40
 
 #define LCR_BKSE	0x80	/* Bank select enable */
-#define LSR		(5 << 2)
-#define THR		(0 << 2)
-#define DLL		(0 << 2)
-#define IER		(1 << 2)
-#define DLM		(1 << 2)
-#define FCR		(2 << 2)
-#define LCR		(3 << 2)
-#define MCR		(4 << 2)
-#define MDR		(8 << 2)
+#define LCRVAL		0x3
+#define MCRVAL		0x3
+#define FCRVAL		0xc1
+
+#define RBR		0x0
+#define DLL		0x0
+#define IER		0x4
+#define DLM		0x4
+#define FCR		0x8
+#define LCR		0xc
+#define MCR		0x10
+#define LSR		0x14
+#define MSR		0x18
+#define SCR		0x1c
+#define THR		0x30
 
+#ifdef CONFIG_DEBUG_LL
 static inline unsigned int ns16550_calc_divisor(unsigned int clk,
 					 unsigned int baudrate)
 {
@@ -28,19 +37,20 @@ static inline unsigned int ns16550_calc_divisor(unsigned int clk,
 
 static inline void INIT_LL(void)
 {
-	unsigned int clk = 100000000;
-	unsigned int divisor = clk / 16 / 115200;
-
-	writeb(0x00, UART_BASE + LCR);
-	writeb(0x00, UART_BASE + IER);
-	writeb(0x07, UART_BASE + MDR);
-	writeb(LCR_BKSE, UART_BASE + LCR);
-	writeb(divisor & 0xff, UART_BASE + DLL);
-	writeb(divisor >> 8, UART_BASE + DLM);
-	writeb(0x03, UART_BASE + LCR);
-	writeb(0x03, UART_BASE + MCR);
-	writeb(0x07, UART_BASE + FCR);
-	writeb(0x00, UART_BASE + MDR);
+	unsigned int div = ns16550_calc_divisor(CONFIG_DEBUG_SOCFPGA_UART_CLOCK,
+						115200);
+
+	while ((readl(UART_BASE + LSR) & LSR_TEMT) == 0);
+
+	writel(0x00, UART_BASE + IER);
+
+	writel(LCR_BKSE, UART_BASE + LCR);
+	writel(div & 0xff, UART_BASE + DLL);
+	writel((div >> 8) & 0xff, UART_BASE + DLM);
+	writel(LCRVAL, UART_BASE + LCR);
+
+	writel(MCRVAL, UART_BASE + MCR);
+	writel(FCRVAL, UART_BASE + FCR);
 }
 
 static inline void PUTC_LL(char c)
@@ -52,4 +62,13 @@ static inline void PUTC_LL(char c)
 	/* Wait to make sure it hits the line, in case we die too soon. */
 	while ((readb(UART_BASE + LSR) & LSR_THRE) == 0);
 }
+
+#else
+static inline unsigned int ns16550_calc_divisor(unsigned int clk,
+					 unsigned int baudrate) {
+	return -ENOSYS;
+}
+static inline void INIT_LL(void) {}
+static inline void PUTC_LL(char c) {}
+#endif
 #endif