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author | Steffen Trumtrar <s.trumtrar@pengutronix.de> | 2018-01-10 09:14:19 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-01-11 09:34:33 +0100 |
commit | dc3f2c4e0d25b0fa48e9a1a6cda1a485ae41dfd6 (patch) | |
tree | 1d26dc92cd2c824cc303a063f569ce3f0b452f3e /arch/arm/mach-socfpga | |
parent | 3b6f631bfd2d5d80a4be338ee8947863e6f4e445 (diff) | |
download | barebox-dc3f2c4e0d25b0fa48e9a1a6cda1a485ae41dfd6.tar.gz barebox-dc3f2c4e0d25b0fa48e9a1a6cda1a485ae41dfd6.tar.xz |
ARM: SoCFPGA: remove emac init code
There is a proper driver now that handles the PHY setup for SoCFPGA.
Get rid of the code from mach-socfpga.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-socfpga')
-rw-r--r-- | arch/arm/mach-socfpga/cyclone5-generic.c | 35 |
1 files changed, 0 insertions, 35 deletions
diff --git a/arch/arm/mach-socfpga/cyclone5-generic.c b/arch/arm/mach-socfpga/cyclone5-generic.c index 73a8ad03b7..dfb1f49e4d 100644 --- a/arch/arm/mach-socfpga/cyclone5-generic.c +++ b/arch/arm/mach-socfpga/cyclone5-generic.c @@ -161,43 +161,8 @@ static int socfpga_detect_sdram(void) return 0; } -/* Some initialization for the EMAC */ -static void socfpga_init_emac(void) -{ - uint32_t rst, val; - - /* No need for this without network support, e.g. xloader build */ - if (!IS_ENABLED(CONFIG_NET)) - return; - - /* According to Cyclone V datasheet, 17-60 "EMAC HPS Interface - * Initialization", changing PHYSEL should be done with EMAC in reset - * via permodrst. */ - - /* Everything, except L4WD0/1, is out of reset via socfpga_lowlevel_init() */ - rst = readl(CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS); - rst |= RSTMGR_PERMODRST_EMAC0 | RSTMGR_PERMODRST_EMAC1; - writel(rst, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS); - - /* Set emac0/1 PHY interface select to RGMII. We could read phy-mode - * from the device tree, if it was desired to support interfaces other - * than RGMII. */ - val = readl(CONFIG_SYSMGR_EMAC_CTRL); - val &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB); - val &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB); - val |= SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; - val |= SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; - writel(val, CONFIG_SYSMGR_EMAC_CTRL); - - /* Take emac0 and emac1 out of reset */ - rst &= ~(RSTMGR_PERMODRST_EMAC0 | RSTMGR_PERMODRST_EMAC1); - writel(rst, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS); -} - static int socfpga_init(void) { - socfpga_init_emac(); - writel(SYSMGR_SDMMC_CTRL_DRVSEL(3) | SYSMGR_SDMMC_CTRL_SMPLSEL(0), SYSMGR_SDMMCGRP_CTRL_REG); |