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| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2020-10-01 11:48:20 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-10-02 06:33:11 +0200 |
| commit | 0387f4f9172126b40a82d2cf640b6bdf968efa01 (patch) | |
| tree | 72b861ca0718cdf3a59b320f2dec631bacc89dfd /arch/arm/mach-stm32mp/include/mach | |
| parent | d2cd3238c21c54afbb1b3b79b7061458649dbd17 (diff) | |
| download | barebox-0387f4f9172126b40a82d2cf640b6bdf968efa01.tar.gz barebox-0387f4f9172126b40a82d2cf640b6bdf968efa01.tar.xz | |
ARM: stm32mp: revision: make CPU type accessible to PBL
There is nothing holding holding us back from reading SoC type in
the PBL. Migrate the necessary definitions to the header to allow
for this.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-stm32mp/include/mach')
| -rw-r--r-- | arch/arm/mach-stm32mp/include/mach/revision.h | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/arch/arm/mach-stm32mp/include/mach/revision.h b/arch/arm/mach-stm32mp/include/mach/revision.h index 2eb4d44b33..2ef8ef30c3 100644 --- a/arch/arm/mach-stm32mp/include/mach/revision.h +++ b/arch/arm/mach-stm32mp/include/mach/revision.h @@ -6,6 +6,9 @@ #ifndef __MACH_CPUTYPE_H__ #define __MACH_CPUTYPE_H__ +#include <mach/bsec.h> +#include <asm/io.h> +#include <mach/stm32.h> /* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit7:0) * 157X: 2x Cortex-A7, Cortex-M4, CAN FD, GPU, DSI @@ -45,4 +48,52 @@ int stm32mp_package(void); #define cpu_is_stm32mp151c() (stm32mp_cputype() == CPU_STM32MP151Cxx) #define cpu_is_stm32mp151a() (stm32mp_cputype() == CPU_STM32MP151Axx) +/* DBGMCU register */ +#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) +#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) +#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) +#define DBGMCU_IDC_DEV_ID_SHIFT 0 +#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) +#define DBGMCU_IDC_REV_ID_SHIFT 16 + +#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) +#define RCC_DBGCFGR_DBGCKEN BIT(8) + +/* BSEC OTP index */ +#define BSEC_OTP_RPN 1 +#define BSEC_OTP_PKG 16 + +/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */ +#define RPN_SHIFT 0 +#define RPN_MASK GENMASK(7, 0) + +static inline u32 stm32mp_read_idc(void) +{ + setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); + return readl(IOMEM(DBGMCU_IDC)); +} + +/* Get Device Part Number (RPN) from OTP */ +static inline int __stm32mp_get_cpu_rpn(u32 *rpn) +{ + int ret = bsec_read_field(BSEC_OTP_RPN, rpn); + if (ret) + return ret; + + *rpn = (*rpn >> RPN_SHIFT) & RPN_MASK; + return 0; +} + +static inline int __stm32mp_get_cpu_type(u32 *type) +{ + u32 id; + int ret = __stm32mp_get_cpu_rpn(type); + if (ret) + return ret; + + id = (stm32mp_read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; + *type |= id << 16; + return 0; +} + #endif /* __MACH_CPUTYPE_H__ */ |