Merge branch 'for-next/misc' into master

4 files changed, 60 insertions, 57 deletions

diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index f064a38088..b8ccbaab67 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -8,9 +8,12 @@ config ARCH_STM32MP157
 	select ARM_PSCI_CLIENT
 	bool
 
-config MACH_STM32MP157C_DK2
+config MACH_STM32MP15XX_DKX
 	select ARCH_STM32MP157
-	bool "STM32MP157C-DK2 board"
+	bool "STM32MP157 DK1 and DK2 boards"
+	help
+	  builds a single barebox-stm32mp15xx-dkx.img that can be deployed
+	  as SSBL on both the stm32mp157a-dk1 and stm32mp157c-dk2
 
 config MACH_LXA_MC1
 	select ARCH_STM32MP157
diff --git a/arch/arm/mach-stm32mp/include/mach/revision.h b/arch/arm/mach-stm32mp/include/mach/revision.h
index 2eb4d44b33..2ef8ef30c3 100644
--- a/arch/arm/mach-stm32mp/include/mach/revision.h
+++ b/arch/arm/mach-stm32mp/include/mach/revision.h
@@ -6,6 +6,9 @@
 #ifndef __MACH_CPUTYPE_H__
 #define __MACH_CPUTYPE_H__
 
+#include <mach/bsec.h>
+#include <asm/io.h>
+#include <mach/stm32.h>
 
 /* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit7:0)
  * 157X: 2x Cortex-A7, Cortex-M4, CAN FD, GPU, DSI
@@ -45,4 +48,52 @@ int stm32mp_package(void);
 #define cpu_is_stm32mp151c() (stm32mp_cputype() == CPU_STM32MP151Cxx)
 #define cpu_is_stm32mp151a() (stm32mp_cputype() == CPU_STM32MP151Axx)
 
+/* DBGMCU register */
+#define DBGMCU_APB4FZ1		(STM32_DBGMCU_BASE + 0x2C)
+#define DBGMCU_IDC		(STM32_DBGMCU_BASE + 0x00)
+#define DBGMCU_IDC_DEV_ID_MASK	GENMASK(11, 0)
+#define DBGMCU_IDC_DEV_ID_SHIFT	0
+#define DBGMCU_IDC_REV_ID_MASK	GENMASK(31, 16)
+#define DBGMCU_IDC_REV_ID_SHIFT	16
+
+#define RCC_DBGCFGR		(STM32_RCC_BASE + 0x080C)
+#define RCC_DBGCFGR_DBGCKEN	BIT(8)
+
+/* BSEC OTP index */
+#define BSEC_OTP_RPN	1
+#define BSEC_OTP_PKG	16
+
+/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
+#define RPN_SHIFT	0
+#define RPN_MASK	GENMASK(7, 0)
+
+static inline u32 stm32mp_read_idc(void)
+{
+	setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
+	return readl(IOMEM(DBGMCU_IDC));
+}
+
+/* Get Device Part Number (RPN) from OTP */
+static inline int __stm32mp_get_cpu_rpn(u32 *rpn)
+{
+	int ret = bsec_read_field(BSEC_OTP_RPN, rpn);
+	if (ret)
+		return ret;
+
+	*rpn = (*rpn >> RPN_SHIFT) & RPN_MASK;
+	return 0;
+}
+
+static inline int __stm32mp_get_cpu_type(u32 *type)
+{
+	u32 id;
+	int ret = __stm32mp_get_cpu_rpn(type);
+	if (ret)
+		return ret;
+
+	id = (stm32mp_read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
+	*type |= id << 16;
+	return 0;
+}
+
 #endif /* __MACH_CPUTYPE_H__ */
diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c
index 7f687fa4f2..e77e99f8fa 100644
--- a/arch/arm/mach-stm32mp/init.c
+++ b/arch/arm/mach-stm32mp/init.c
@@ -15,26 +15,6 @@
 #include <bootsource.h>
 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
 
-/* DBGMCU register */
-#define DBGMCU_IDC		(STM32_DBGMCU_BASE + 0x00)
-#define DBGMCU_APB4FZ1		(STM32_DBGMCU_BASE + 0x2C)
-#define DBGMCU_APB4FZ1_IWDG2	BIT(2)
-#define DBGMCU_IDC_DEV_ID_MASK	GENMASK(11, 0)
-#define DBGMCU_IDC_DEV_ID_SHIFT	0
-#define DBGMCU_IDC_REV_ID_MASK	GENMASK(31, 16)
-#define DBGMCU_IDC_REV_ID_SHIFT	16
-
-#define RCC_DBGCFGR		(STM32_RCC_BASE + 0x080C)
-#define RCC_DBGCFGR_DBGCKEN	BIT(8)
-
-/* BSEC OTP index */
-#define BSEC_OTP_RPN	1
-#define BSEC_OTP_PKG	16
-
-/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
-#define RPN_SHIFT	0
-#define RPN_MASK	GENMASK(7, 0)
-
 /* Package = bit 27:29 of OTP16
  * - 100: LBGA448  (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
  * - 011: LBGA354  (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
@@ -152,38 +132,9 @@ int stm32mp_package(void)
 	return __stm32mp_package;
 }
 
-static inline u32 read_idc(void)
-{
-	setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
-	return readl(IOMEM(DBGMCU_IDC));
-}
-
-/* Get Device Part Number (RPN) from OTP */
-static int get_cpu_rpn(u32 *rpn)
-{
-	int ret = bsec_read_field(BSEC_OTP_RPN, rpn);
-	if (ret)
-		return ret;
-
-	*rpn = (*rpn >> RPN_SHIFT) & RPN_MASK;
-	return 0;
-}
-
 static u32 get_cpu_revision(void)
 {
-	return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
-}
-
-static int get_cpu_type(u32 *type)
-{
-	u32 id;
-	int ret = get_cpu_rpn(type);
-	if (ret)
-		return ret;
-
-	id = (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
-	*type |= id << 16;
-	return 0;
+	return (stm32mp_read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
 }
 
 static int get_cpu_package(u32 *pkg)
@@ -250,7 +201,7 @@ static int setup_cpu_type(void)
 	u32 pkg;
 	int ret;
 
-	get_cpu_type(&__stm32mp_cputype);
+	__stm32mp_get_cpu_type(&__stm32mp_cputype);
 	switch (__stm32mp_cputype) {
 	case CPU_STM32MP157Fxx:
 		cputypestr = "157F";
@@ -366,4 +317,4 @@ static int stm32mp_init(void)
 
 	return 0;
 }
-postcore_initcall(stm32mp_init);
+core_initcall(stm32mp_init);
diff --git a/arch/arm/mach-stm32mp/stm32image.c b/arch/arm/mach-stm32mp/stm32image.c
index 84975c5c3b..207df6894d 100644
--- a/arch/arm/mach-stm32mp/stm32image.c
+++ b/arch/arm/mach-stm32mp/stm32image.c
@@ -43,8 +43,6 @@ static struct image_handler image_handler_stm32_image_v1_handler = {
 
 static int stm32mp_register_stm32image_image_handler(void)
 {
-	register_image_handler(&image_handler_stm32_image_v1_handler);
-
-	return 0;
+	return register_image_handler(&image_handler_stm32_image_v1_handler);
 }
 late_initcall(stm32mp_register_stm32image_image_handler);