diff options
author | Lucas Stach <dev@lynxeye.de> | 2015-03-02 22:47:20 +0100 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-03-03 08:38:20 +0100 |
commit | 09c4b63aa20e97011eb109794c7c23faf7ebdce4 (patch) | |
tree | f4bad7f9c52ceef6287e1b4907ea080068d66f9d /arch/arm/mach-tegra | |
parent | 0b6ddeecb52feb3da17585c5d076da0f67dde2a0 (diff) | |
download | barebox-09c4b63aa20e97011eb109794c7c23faf7ebdce4.tar.gz barebox-09c4b63aa20e97011eb109794c7c23faf7ebdce4.tar.xz |
tegra: avp_init: write DT address register earlier
Otherwise the write would be skipped if we are already running on the main CPU
cluster. In practice this means that a second stage barebox will reuse the DT
of the first stage, instead of using it's own.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r-- | arch/arm/mach-tegra/tegra_avp_init.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c index 619fecf4c3..91fd894dca 100644 --- a/arch/arm/mach-tegra/tegra_avp_init.c +++ b/arch/arm/mach-tegra/tegra_avp_init.c @@ -262,6 +262,9 @@ void tegra_avp_reset_vector(uint32_t boarddata) int num_cores; unsigned int entry_address = 0; + /* put boarddata in scratch reg, for main CPU to fetch after startup */ + writel(boarddata, TEGRA_PMC_BASE + PMC_SCRATCH(10)); + if (tegra_cpu_is_maincomplex()) tegra_maincomplex_entry(); @@ -291,9 +294,6 @@ void tegra_avp_reset_vector(uint32_t boarddata) } writel(entry_address, TEGRA_EXCEPTION_VECTORS_BASE + 0x100); - /* put boarddata in scratch reg, for main CPU to fetch after startup */ - writel(boarddata, TEGRA_PMC_BASE + PMC_SCRATCH(10)); - /* bring up main CPU complex */ start_cpu0_clocks(); maincomplex_powerup(); |