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| author | Lucas Stach <dev@lynxeye.de> | 2014-06-03 22:35:01 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-06-05 08:01:14 +0200 |
| commit | 983f39f6cafd7a38ba19a52c822fd3f850803e54 (patch) | |
| tree | 79f1b8e3bdf14abe7d5d502eab7770dcf80fa9a3 /arch/arm/mach-tegra | |
| parent | 3d6fcedfeb418c0c12fe2424b1a4a65a4d3fc362 (diff) | |
| download | barebox-983f39f6cafd7a38ba19a52c822fd3f850803e54.tar.gz barebox-983f39f6cafd7a38ba19a52c822fd3f850803e54.tar.xz | |
tegra: change cpu internal reset layout for Tegra124
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-tegra')
| -rw-r--r-- | arch/arm/mach-tegra/tegra_avp_init.c | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c index d25c1dd4d4..61cfa05ce8 100644 --- a/arch/arm/mach-tegra/tegra_avp_init.c +++ b/arch/arm/mach-tegra/tegra_avp_init.c @@ -43,8 +43,12 @@ static void assert_maincomplex_reset(int num_cores) u32 mask = 0; int i; - for (i = 0; i < num_cores; i++) - mask |= 0x1111 << i; + for (i = 0; i < num_cores; i++) { + if (tegra_get_chiptype() >= TEGRA114) + mask |= 0x111001 << i; + else + mask |= 0x1111 << i; + } writel(mask, TEGRA_CLK_RESET_BASE + CRC_RST_CPU_CMPLX_SET); writel(CRC_RST_DEV_L_CPU, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_L_SET); @@ -53,7 +57,14 @@ static void assert_maincomplex_reset(int num_cores) /* release reset state of the first core of the main CPU complex */ static void deassert_cpu0_reset(void) { - writel(0x1111, TEGRA_CLK_RESET_BASE + CRC_RST_CPU_CMPLX_CLR); + u32 reg; + + if (tegra_get_chiptype() >= TEGRA114) + reg = 0x21fff00f; + else + reg = 0x1111; + + writel(reg, TEGRA_CLK_RESET_BASE + CRC_RST_CPU_CMPLX_CLR); writel(CRC_RST_DEV_L_CPU, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_L_CLR); } @@ -185,7 +196,7 @@ static void start_cpu0_clocks(void) /* deassert clock stop for cpu 0 */ reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_CPU_CMPLX); - reg &= ~CRC_CLK_CPU_CMPLX_CPU0_CLK_STP; + reg &= ~(0xf << 8); writel(reg, TEGRA_CLK_RESET_BASE + CRC_CLK_CPU_CMPLX); /* enable main CPU complex clock */ |