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| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2013-02-11 13:03:26 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-02-12 08:49:27 +0100 |
| commit | 2738f723521e299b38ab882a85e11f246b38dad2 (patch) | |
| tree | e92bb278f985478922a9f16dff1422b2a0085990 /arch/arm/mach-vexpress/devices.c | |
| parent | 19905efac5ebb268530e43282134f672bc618764 (diff) | |
| download | barebox-2738f723521e299b38ab882a85e11f246b38dad2.tar.gz barebox-2738f723521e299b38ab882a85e11f246b38dad2.tar.xz | |
arm: add vexpress board support
detect the cpu model to dynamise the periphs mapping
currently only tested on qemu but should work on real hardware
Cortex-A9
if you use 1GiB of ram you can run the same barebox on Cortex-A15 or Cortex-A9
otherwise use vexpress_ca9_defconfig where the TEXT_BASE is at 0x63f00000
when we will add the relocation support this defconfig will be drop
qemu/arm-softmmu/qemu-system-arm -M vexpress-a9 -m 1024 -smp 1 -kernel build/vexpress/barebox -pflash build/vexpress/flash0 -nographic
Cortex-A15
qemu/arm-softmmu/qemu-system-arm -M vexpress-a15 -m 1024 -smp 1 -kernel build/vexpress/barebox -pflash build/vexpress/flash0 -nographic
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-vexpress/devices.c')
| -rw-r--r-- | arch/arm/mach-vexpress/devices.c | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/arch/arm/mach-vexpress/devices.c b/arch/arm/mach-vexpress/devices.c new file mode 100644 index 0000000000..69c93efbcd --- /dev/null +++ b/arch/arm/mach-vexpress/devices.c @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> + * + * GPLv2 only + */ + +#include <common.h> + +#include <linux/amba/bus.h> + +#include <asm/memory.h> + +#include <mach/devices.h> + +void vexpress_a9_add_ddram(u32 ddr0_size, u32 ddr1_size) +{ + arm_add_mem_device("ram0", 0x60000000, ddr0_size); + + if (ddr1_size) + arm_add_mem_device("ram1", 0x80000000, ddr1_size); +} + + +void vexpress_a9_register_uart(unsigned id) +{ + resource_size_t start; + + switch (id) { + case 0: + start = 0x10009000; + break; + case 1: + start = 0x1000a000; + break; + case 2: + start = 0x1000b000; + break; + case 3: + start = 0x1000c000; + break; + default: + return; + } + amba_apb_device_add(NULL, "uart-pl011", id, start, 4096, NULL, 0); +} + +void vexpress_add_ddram(u32 size) +{ + arm_add_mem_device("ram1", 0x80000000, size); +} + +void vexpress_register_uart(unsigned id) +{ + resource_size_t start; + + switch (id) { + case 0: + start = 0x1c090000; + break; + case 1: + start = 0x1c0a0000; + break; + case 2: + start = 0x1c0b0000; + break; + case 3: + start = 0x1c0c0000; + break; + default: + return; + } + amba_apb_device_add(NULL, "uart-pl011", id, start, 4096, NULL, 0); +} |