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author | Steffen Trumtrar <s.trumtrar@pengutronix.de> | 2013-03-26 10:11:23 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-03-27 09:23:48 +0100 |
commit | 1bb8460fc19dee2199a74f0fd2c2e8f841d22abe (patch) | |
tree | 4fb75c1d3fbd12445295949a0f74564c80069b5a /arch/arm/mach-zynq/zynq.c | |
parent | a89e378be07ca03f4d12b0dc871298211ce4ad31 (diff) | |
download | barebox-1bb8460fc19dee2199a74f0fd2c2e8f841d22abe.tar.gz barebox-1bb8460fc19dee2199a74f0fd2c2e8f841d22abe.tar.xz |
ARM: zynq: Add new architecture zynq
Add basic support for the Xilinx Zynq-7000 EPP architecture.
The Zynq-7000 is an embedded processing platform that combines a Cortex A9
dualcore MPSoC with an Artix-7 FPGA.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-zynq/zynq.c')
-rw-r--r-- | arch/arm/mach-zynq/zynq.c | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/arch/arm/mach-zynq/zynq.c b/arch/arm/mach-zynq/zynq.c new file mode 100644 index 0000000000..bd29e13377 --- /dev/null +++ b/arch/arm/mach-zynq/zynq.c @@ -0,0 +1,56 @@ +/* + * (c) 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <asm/system.h> +#include <asm-generic/io.h> +#include <common.h> +#include <init.h> +#include <mach/zynq7000-regs.h> + +static int zynq_init(void) +{ + u32 val; + + dsb(); + isb(); + writel(0xDF0D, ZYNQ_SLCR_UNLOCK); + /* remap ocm high */ + writel(0x0000000F, 0xf8000910); + /* mpcore.filtering_start_address */ + writel(0x00000000, 0xf8f00040); + /* mpcore.filtering_end_address */ + writel(0xffe00000, 0xf8f00044); + val = readl(0xf8f00000); + val |= 0x2; + writel(val, 0xf8f00000); + dmb(); + + add_generic_device("zynq-clock", 0, NULL, ZYNQ_SLCR_BASE, 0x4000, IORESOURCE_MEM, NULL); + add_generic_device("smp_twd", 0, NULL, CORTEXA9_SCU_TIMER_BASE_ADDR, + 0x4000, IORESOURCE_MEM, NULL); + return 0; +} +postcore_initcall(zynq_init); + +void __noreturn reset_cpu(unsigned long addr) +{ + /* write unlock key to slcr */ + writel(0xDF0D, ZYNQ_SLCR_UNLOCK); + /* reset */ + writel(0x1, ZYNQ_PSS_RST_CTRL); + + while (1) + ; +} |