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authorSascha Hauer <s.hauer@pengutronix.de>2015-08-26 09:04:45 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2015-08-27 21:37:03 +0200
commit83b0a5ae055bc084938dac96b3ea1c796d99d86c (patch)
treeba69e2015cbfeb1626f7ea3f6bf850556541095a /arch/arm/mach-zynq
parent167e93947e9b755b54900ae9870dbcc089f8d6c9 (diff)
downloadbarebox-83b0a5ae055bc084938dac96b3ea1c796d99d86c.tar.gz
barebox-83b0a5ae055bc084938dac96b3ea1c796d99d86c.tar.xz
restart: replace reset_cpu with registered restart handlers
This replaces the reset_cpu() function which every SoC or board must provide with registered handlers. This makes it possible to have multiple reset functions for boards which have multiple ways to reset the machine. Also boards which have no way at all to reset the machine no longer have to provide a dummy reset_cpu() function. The problem this solves is that some machines have external PMICs or similar to reset the system which have to be preferred over the internal SoC reset, because the PMIC can reset not only the SoC but also the external devices. To pick the right way to reset a machine each handler has a priority. The default priority is 100 and all currently existing restart handlers are registered with this priority. of_get_restart_priority() allows to retrieve the priority from the device tree which makes it possible for boards to give certain restart handlers a higher priority in order to use this one instead of the default one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-zynq')
-rw-r--r--arch/arm/mach-zynq/zynq.c24
1 files changed, 13 insertions, 11 deletions
diff --git a/arch/arm/mach-zynq/zynq.c b/arch/arm/mach-zynq/zynq.c
index bd29e13377..a0a8d0d249 100644
--- a/arch/arm/mach-zynq/zynq.c
+++ b/arch/arm/mach-zynq/zynq.c
@@ -17,8 +17,19 @@
#include <asm-generic/io.h>
#include <common.h>
#include <init.h>
+#include <restart.h>
#include <mach/zynq7000-regs.h>
+static void __noreturn zynq_restart_soc(struct restart_handler *rst)
+{
+ /* write unlock key to slcr */
+ writel(0xDF0D, ZYNQ_SLCR_UNLOCK);
+ /* reset */
+ writel(0x1, ZYNQ_PSS_RST_CTRL);
+
+ hang();
+}
+
static int zynq_init(void)
{
u32 val;
@@ -40,17 +51,8 @@ static int zynq_init(void)
add_generic_device("zynq-clock", 0, NULL, ZYNQ_SLCR_BASE, 0x4000, IORESOURCE_MEM, NULL);
add_generic_device("smp_twd", 0, NULL, CORTEXA9_SCU_TIMER_BASE_ADDR,
0x4000, IORESOURCE_MEM, NULL);
+ restart_handler_register_fn(zynq_restart_soc);
+
return 0;
}
postcore_initcall(zynq_init);
-
-void __noreturn reset_cpu(unsigned long addr)
-{
- /* write unlock key to slcr */
- writel(0xDF0D, ZYNQ_SLCR_UNLOCK);
- /* reset */
- writel(0x1, ZYNQ_PSS_RST_CTRL);
-
- while (1)
- ;
-}