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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2013-01-17 14:31:00 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-01-20 11:07:50 +0100 |
| commit | 59a22cb39275917c8455ee54ce71aafd5ecaefe0 (patch) | |
| tree | 6abfa0f113fdbdd4c294a7f47889416412389e85 /arch/arm | |
| parent | f051557a74512c864a350fd3f835e2dd5e7558a1 (diff) | |
| download | barebox-59a22cb39275917c8455ee54ce71aafd5ecaefe0.tar.gz barebox-59a22cb39275917c8455ee54ce71aafd5ecaefe0.tar.xz | |
ARM i.MX6: Fix usb phy base addresses
What we had as usb phy1 base address is really usb phy2. Fix the names
and add the missing base address definition for usb phy1.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-imx/include/mach/imx6-regs.h | 3 | ||||
| -rw-r--r-- | arch/arm/mach-imx/usb-imx6.c | 10 |
2 files changed, 7 insertions, 6 deletions
diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h index 7c72cba838..d947aa6c9d 100644 --- a/arch/arm/mach-imx/include/mach/imx6-regs.h +++ b/arch/arm/mach-imx/include/mach/imx6-regs.h @@ -49,7 +49,8 @@ #define MX6_WDOG2_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x40000) #define MX6_CCM_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x44000) #define MX6_ANATOP_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x48000) -#define MX6_USBPHY1_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x4a000) +#define MX6_USBPHY1_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x49000) +#define MX6_USBPHY2_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x4a000) #define MX6_SNVS_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x4C000) #define MX6_EPIT1_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x50000) #define MX6_EPIT2_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x54000) diff --git a/arch/arm/mach-imx/usb-imx6.c b/arch/arm/mach-imx/usb-imx6.c index a3c4304add..5e3df10e44 100644 --- a/arch/arm/mach-imx/usb-imx6.c +++ b/arch/arm/mach-imx/usb-imx6.c @@ -94,18 +94,18 @@ int imx6_usb_phy2_enable(void) while (readl(MX6_USBOH3_USB_BASE_ADDR + USB_UH1_USBCMD) & USB_CMD_RESET); /* reset usbphy */ - writel(USBPHY_CTRL_SFTRST, MX6_USBPHY1_BASE_ADDR + USBPHY_CTRL + SET); + writel(USBPHY_CTRL_SFTRST, MX6_USBPHY2_BASE_ADDR + USBPHY_CTRL + SET); udelay(10); /* clr reset and clkgate */ - writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE, MX6_USBPHY1_BASE_ADDR + USBPHY_CTRL + CLR); + writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE, MX6_USBPHY2_BASE_ADDR + USBPHY_CTRL + CLR); /* clr all pwd bits => power up phy */ - writel(0xffffffff, MX6_USBPHY1_BASE_ADDR + CLR); + writel(0xffffffff, MX6_USBPHY2_BASE_ADDR + CLR); /* set utmilvl2/3 */ - val = readl(MX6_USBPHY1_BASE_ADDR + USBPHY_CTRL); + val = readl(MX6_USBPHY2_BASE_ADDR + USBPHY_CTRL); val |= USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2; - writel(val, MX6_USBPHY1_BASE_ADDR + USBPHY_CTRL + SET); + writel(val, MX6_USBPHY2_BASE_ADDR + USBPHY_CTRL + SET); return 0; } |