path: root/arch/arm
diff options
authorSascha Hauer <>2017-02-01 08:19:43 +0100
committerSascha Hauer <>2017-02-06 11:51:20 +0100
commitad200f0dc31c1dc89e36e0d2f71707c51e2bc0a1 (patch)
tree96dbbbfc78a0e1085b6944518c9c90d82fe7ca7f /arch/arm
parentc82e1f90d2fa1ebfbeaf0f765ee974b31d273b1c (diff)
pinctrl: i.MX7: Fix LPSR sel_imput setting
The i.MX7 has two pinmux controllers, the regular and the LPSR controller. The LPSR pinmux controller doesn't have any sel_input registers, instead they can be found in the regular pinmux controller. This means whenever we want to apply the the sel_input setting for the LPSR controller, we have to apply them to the regular controller instead. In barebox take the easy way out and just add the difference of the two base addresses to the register offset. The same issue is present in the Kernel aswell, but when the bootloader already configured the pins correctly nobody notices when the Kernel sel_input setup effectively is a no-op. Signed-off-by: Sascha Hauer <>
Diffstat (limited to 'arch/arm')
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/include/mach/iomux-v3.h b/arch/arm/mach-imx/include/mach/iomux-v3.h
index f877aad89b..271fe94a00 100644
--- a/arch/arm/mach-imx/include/mach/iomux-v3.h
+++ b/arch/arm/mach-imx/include/mach/iomux-v3.h
@@ -116,6 +116,7 @@ typedef u64 iomux_v3_cfg_t;
#define SHARE_MUX_CONF_REG 0x1
+#define IMX7_PINMUX_LPSR 0x4
static inline void iomux_v3_setup_pad(void __iomem *iomux, unsigned int flags,
u32 mux_reg, u32 conf_reg, u32 input_reg,
@@ -125,6 +126,13 @@ static inline void iomux_v3_setup_pad(void __iomem *iomux, unsigned int flags,
const bool conf_ok = !!conf_reg;
const bool input_ok = !!input_reg;
+ /*
+ * The sel_input registers for the LPSR controller pins are in the regular pinmux
+ * controller, so bend the register offset over to the other controller.
+ */
+ if (flags & IMX7_PINMUX_LPSR)
+ input_reg += 0x70000;
if (flags & SHARE_MUX_CONF_REG) {
mux_val |= conf_val;
} else {