Merge branch 'next'

Conflicts:
	common/hush.c

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

150 files changed, 11668 insertions, 834 deletions

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 529948691d..d0bfd71cd6 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -104,6 +104,7 @@ board-$(CONFIG_MACH_PCM049)			:= pcm049
 board-$(CONFIG_MACH_PCA100)			:= phycard-i.MX27
 board-$(CONFIG_MACH_PCAAL1)			:= phycard-a-l1
 board-$(CONFIG_MACH_PCAAXL2)			:= phycard-a-xl2
+board-$(CONFIG_MACH_PCM027)			:= pcm027
 board-$(CONFIG_MACH_PCM037)			:= pcm037
 board-$(CONFIG_MACH_PCM038)			:= pcm038
 board-$(CONFIG_MACH_PCM043)			:= pcm043
@@ -130,6 +131,8 @@ board-$(CONFIG_MACH_USB_A9G20)			:= usb-a926x
 board-$(CONFIG_MACH_VERSATILEPB)		:= versatile
 board-$(CONFIG_MACH_TX25)			:= karo-tx25
 board-$(CONFIG_MACH_TQMA53)			:= tqma53
+board-$(CONFIG_MACH_TX51)			:= karo-tx51
+board-$(CONFIG_MACH_MX6Q_ARM2)			:= freescale-mx6-arm2
 
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 
diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
index adeaaccb39..1a3181ebfb 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -109,15 +109,15 @@ static int a9m2410_devices_init(void)
 	writel(reg, S3C_MISCCR);
 
 	/* ----------- the devices the boot loader should work with -------- */
-	add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
-			   IORESOURCE_MEM, &nand_info);
+	add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL, S3C24X0_NAND_BASE,
+			0, IORESOURCE_MEM, &nand_info);
 	/*
 	 * SMSC 91C111 network controller on the baseboard
 	 * connected to CS line 1 and interrupt line
 	 * GPIO3, data width is 32 bit
 	 */
-	add_generic_device("smc91c111", -1, NULL, S3C_CS1_BASE + 0x300, 16,
-			   IORESOURCE_MEM, NULL);
+	add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, S3C_CS1_BASE + 0x300,
+			16, IORESOURCE_MEM, NULL);
 
 #ifdef CONFIG_NAND
 	/* ----------- add some vital partitions -------- */
@@ -145,8 +145,8 @@ void __bare_init nand_boot(void)
 
 static int a9m2410_console_init(void)
 {
-	add_generic_device("s3c_serial", -1, NULL, S3C_UART1_BASE, S3C_UART1_SIZE,
-			   IORESOURCE_MEM, NULL);
+	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
+			S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
 	return 0;
 }
 
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
index 6c6ccdb5f5..4094e31cd7 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -129,15 +129,15 @@ static int a9m2440_devices_init(void)
 	writel(reg, S3C_MISCCR);
 
 	/* ----------- the devices the boot loader should work with -------- */
-	add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
+	add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL, S3C24X0_NAND_BASE, 0,
 			   IORESOURCE_MEM, &nand_info);
 	/*
 	 * cs8900 network controller onboard
 	 * Connected to CS line 5 + A24 and interrupt line EINT9,
 	 * data width is 16 bit
 	 */
-	add_generic_device("cs8900", -1, NULL, S3C_CS5_BASE + (1 << 24) + 0x300, 16,
-			   IORESOURCE_MEM, NULL);
+	add_generic_device("cs8900", DEVICE_ID_DYNAMIC, NULL,
+			S3C_CS5_BASE + (1 << 24) + 0x300, 16, IORESOURCE_MEM, NULL);
 
 #ifdef CONFIG_NAND
 	/* ----------- add some vital partitions -------- */
@@ -164,8 +164,8 @@ void __bare_init nand_boot(void)
 
 static int a9m2440_console_init(void)
 {
-	add_generic_device("s3c_serial", -1, NULL, S3C_UART1_BASE, S3C_UART1_SIZE,
-			   IORESOURCE_MEM, NULL);
+	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
+			S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
 	return 0;
 }
 
diff --git a/arch/arm/boards/at91sam9260ek/env/config b/arch/arm/boards/at91sam9260ek/env/config
index 2c0f075fa8..06b9fafb81 100644
--- a/arch/arm/boards/at91sam9260ek/env/config
+++ b/arch/arm/boards/at91sam9260ek/env/config
@@ -21,19 +21,21 @@ fi
 kernel_loc=nfs
 # can be either 'net', 'nor', 'nand' or 'initrd'
 rootfs_loc=net
+# can be either 'nfs', 'tftp', 'nor', 'nand' or empty
+oftree_loc=nfs
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
 rootfsimage=root.$rootfs_type
 
-#kernelimage=zImage
-kernelimage=uImage
+kernelimage=zImage
+#kernelimage=uImage
 #kernelimage=Image
 #kernelimage=Image.lzo
 
 nand_device=atmel_nand
-nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),4M(kernel),120M(rootfs),-(data)"
-rootfs_mtdblock_nand=5
+nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),4M(kernel),120M(rootfs),-(data)"
+rootfs_mtdblock_nand=6
 
 autoboot_timeout=3
 
diff --git a/arch/arm/boards/at91sam9261ek/env/config b/arch/arm/boards/at91sam9261ek/env/config
index be4d37ce4e..820485dea8 100644
--- a/arch/arm/boards/at91sam9261ek/env/config
+++ b/arch/arm/boards/at91sam9261ek/env/config
@@ -18,22 +18,24 @@ fi
 #eth0.serverip=a.b.c.d
 
 # can be either 'nfs', 'tftp' or 'nand'
-kernel_loc=tftp
+kernel_loc=nfs
 # can be either 'net', 'nand' or 'initrd'
 rootfs_loc=net
+# can be either 'nfs', 'tftp', 'nand' or empty
+oftree_loc=nfs
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
 rootfsimage=root.$rootfs_type
 
-#kernelimage=zImage
-kernelimage=uImage
+kernelimage=zImage
+#kernelimage=uImage
 #kernelimage=Image
 #kernelimage=Image.lzo
 
 nand_device=atmel_nand
-nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),4M(kernel),120M(rootfs),-(data)"
-rootfs_mtdblock_nand=5
+nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),4M(kernel),120M(rootfs),-(data)"
+rootfs_mtdblock_nand=6
 
 autoboot_timeout=3
 
diff --git a/arch/arm/boards/at91sam9263ek/env/config b/arch/arm/boards/at91sam9263ek/env/config
index 93eeb1e2ce..a09bc26080 100644
--- a/arch/arm/boards/at91sam9263ek/env/config
+++ b/arch/arm/boards/at91sam9263ek/env/config
@@ -12,24 +12,26 @@ dhcp_vendor_id=barebox-at91sam9263ek
 #eth0.serverip=a.b.c.d
 
 # can be either 'nfs', 'tftp', 'nor' or 'nand'
-kernel_loc=tftp
+kernel_loc=nfs
 # can be either 'net', 'nor', 'nand' or 'initrd'
 rootfs_loc=net
+# can be either 'nfs', 'tftp', 'nor', 'nand' or empty
+oftree_loc=nfs
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
 rootfsimage=root.$rootfs_type
 
-#kernelimage=zImage
-kernelimage=uImage
+kernelimage=zImage
+#kernelimage=uImage
 #kernelimage=Image
 #kernelimage=Image.lzo
 
 nand_device=atmel_nand
-nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),4M(kernel),120M(rootfs),-(data)"
-rootfs_mtdblock_nand=5
+nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),4M(kernel),120M(rootfs),-(data)"
+rootfs_mtdblock_nand=6
 
-nor_parts="256k(barebox),64k(bareboxenv),4M(kernel),-(root)"
+nor_parts="256k(barebox),64k(bareboxenv),64k(oftree)4M(kernel),-(root)"
 
 autoboot_timeout=3
 
diff --git a/arch/arm/boards/at91sam9m10g45ek/env/bin/boot_board b/arch/arm/boards/at91sam9m10g45ek/env/bin/boot_board
new file mode 100644
index 0000000000..3d7426f527
--- /dev/null
+++ b/arch/arm/boards/at91sam9m10g45ek/env/bin/boot_board
@@ -0,0 +1,51 @@
+#!/bin/sh
+
+PATH=/env/bin
+export PATH
+
+. /env/config
+
+menu -r -m boot
+menu -a -m boot -d "\e[1;36mWelcome on Barebox Boot Sequence\e[0m"
+menu -e -a -m boot -c 'menu_boot'			-d "boot (default)             "
+menu -e -a -m boot -c 'menu_boot -m nand'		-d "boot from nand             "
+menu -e -a -m boot -c 'menu_boot -k nfs -r net'		-d "boot from nfs (kernel nfs) "
+menu -e -a -m boot -c 'menu_boot -k tftp -r net'	-d "boot from nfs (kernel tftp)"
+menu -e -a -m boot -c 'clear'			-d "\e[2;33mshell                      \e[0m"
+menu -e -a -m boot -u update				-d "update                     "
+menu -e -a -m boot -c reset			-d "\e[1;31mreset                      \e[0m"
+
+# Submenu Update
+menu -r -m update
+menu -a -m update -d "\e[1;36mUpdate\e[0m"
+menu -e -a -m update -u update_barebox	-d "\e[2;33mbarebox\e[0m"
+menu -e -a -m update -u update_kernel		-d "kernel"
+menu -e -a -m update -u update_rootfs		-d "rootfs"
+menu -e -a -m update -c 'true'			-d "back  "
+
+# submenu update barebox
+menu -r -m update_barebox
+menu -a -m update_barebox -d "\e[2;33mBarebox Update Methode\e[0m"
+menu -e -a -m update_barebox -c 'update -t barebox -d nand -m tftp -c; echo ; timeout -a 3'	-d "tftp  "
+menu -e -a -m update_barebox -c 'update -t barebox -d nand -m xmodem -c; echo ; timeout -a 3'	-d "xmodem"
+menu -e -a -m update_barebox -c 'update -t barebox -d nand -m nfs -c; echo ; timeout -a 3'	-d "nfs   "
+menu -e -a -m update_barebox -c 'true'								-d "back  "
+
+# submenu update kernel
+menu -r -m update_kernel
+menu -a -m update_kernel -d "\e[1;36mKernel Update Methode\e[0m"
+menu -e -a -m update_kernel -c 'update -t kernel -d nand -m tftp -c; echo ; timeout -a 3'	-d "tftp  "
+menu -e -a -m update_kernel -c 'update -t kernel -d nand -m xmodem -c; echo ; timeout -a 3'	-d "xmodem"
+menu -e -a -m update_kernel -c 'update -t kernel -d nand -m nfs -c; echo ; timeout -a 3'	-d "nfs   "
+menu -e -a -m update_kernel -c 'true'								-d "back  "
+
+# submenu update barebox
+menu -r -m update_rootfs
+menu -a -m update_rootfs -d "\e[1;36mRootfs Update Methode\e[0m"
+menu -e -a -m update_rootfs -c 'update -t rootfs -d nand -m tftp -c; echo ; timeout -a 3'	-d "tftp  "
+menu -e -a -m update_rootfs -c 'update -t rootfs -d nand -m xmodem -c; echo ; timeout -a 3'	-d "xmodem"
+menu -e -a -m update_rootfs -c 'update -t rootfs -d nand -m nfs -c; echo ; timeout -a 3'	-d "nfs   "
+menu -e -a -m update_rootfs -c 'true'								-d "back  "
+
+menu -s -m boot -A $autoboot_timeout
+exit 1
diff --git a/arch/arm/boards/at91sam9m10g45ek/env/bin/menu_boot b/arch/arm/boards/at91sam9m10g45ek/env/bin/menu_boot
new file mode 100644
index 0000000000..d0b1396de9
--- /dev/null
+++ b/arch/arm/boards/at91sam9m10g45ek/env/bin/menu_boot
@@ -0,0 +1,37 @@
+#!/bin/sh
+
+. /env/config
+
+while getopt "k:r:i:m:" Option
+do
+if [ ${Option} = k ]; then
+	kernel_loc=${OPTARG}
+elif [ ${Option} = r ]; then
+	rootfs_loc=${OPTARG}
+elif [ ${Option} = i ]; then
+	ip=${OPTARG}
+elif [ ${Option} = m ]; then
+	mode=${OPTARG}
+else
+fi
+done
+
+boot_opt=
+
+if [ x$mode != x ]; then
+	boot_opt="-m ${mode}"
+else
+	if [ x$kernel_loc != x ]; then
+		boot_opt="-k ${kernel_loc}"
+	fi
+	if [ x$kernel_loc != x ]; then
+		boot_opt="-r ${rootfs_loc}"
+	fi
+fi
+
+boot ${boot_opt} -i ${ip}
+
+echo -n "boot error: Hit any key to return to the menu: "
+timeout -a 3
+menu -s -m boot
+exit 1
diff --git a/arch/arm/boards/at91sam9m10g45ek/env/config b/arch/arm/boards/at91sam9m10g45ek/env/config
index d1151323df..37a20e93f2 100644
--- a/arch/arm/boards/at91sam9m10g45ek/env/config
+++ b/arch/arm/boards/at91sam9m10g45ek/env/config
@@ -12,26 +12,28 @@ dhcp_vendor_id=barebox-at91sam9m10g45ek
 #eth0.serverip=a.b.c.d
 
 # can be either 'nfs', 'tftp' or 'nand'
-kernel_loc=tftp
+kernel_loc=nfs
 # can be either 'net', 'nand' or 'initrd'
 rootfs_loc=net
+# can be either 'nfs', 'tftp', 'nand' or empty
+oftree_loc=nfs
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
 rootfsimage=root.$rootfs_type
 
-#kernelimage=zImage
-kernelimage=uImage
+kernelimage=zImage
+#kernelimage=uImage
 #kernelimage=Image
 #kernelimage=Image.lzo
 
 nand_device=atmel_nand
-nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),4M(kernel),120M(rootfs),-(data)"
-rootfs_mtdblock_nand=5
+nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),4M(kernel),120M(rootfs),-(data)"
+rootfs_mtdblock_nand=6
 
 autoboot_timeout=3
 
-bootargs="console=ttyS0,115200"
+bootargs="console=ttyS0,115200 console=tty0"
 
 # set a fancy prompt (if support is compiled in)
 PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c b/arch/arm/boards/at91sam9m10g45ek/init.c
index 6011bad2f6..c4b1a97f8e 100644
--- a/arch/arm/boards/at91sam9m10g45ek/init.c
+++ b/arch/arm/boards/at91sam9m10g45ek/init.c
@@ -41,6 +41,8 @@
 #include <mach/io.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/sam9_smc.h>
+#include <gpio_keys.h>
+#include <readkey.h>
 
 /*
  * board revision encoding
@@ -164,6 +166,54 @@ static void ek_device_add_leds(void)
 static void ek_device_add_leds(void) {}
 #endif
 
+#ifdef CONFIG_KEYBOARD_GPIO
+struct gpio_keys_button keys[] = {
+	{
+		.code = KEY_HOME,
+		.gpio = AT91_PIN_PB6,
+	}, {
+		.code = KEY_RETURN,
+		.gpio = AT91_PIN_PB7,
+	}, {
+		.code = KEY_LEFT,
+		.gpio = AT91_PIN_PB14,
+	}, {
+		.code = KEY_RIGHT,
+		.gpio = AT91_PIN_PB15,
+	}, {
+		.code = KEY_UP,
+		.gpio = AT91_PIN_PB16,
+	}, {
+		.code = KEY_DOWN,
+		.gpio = AT91_PIN_PB17,
+	}, {
+		.code = KEY_RETURN,
+		.gpio = AT91_PIN_PB18,
+	},
+};
+
+struct gpio_keys_platform_data gk_pdata = {
+	.buttons = keys,
+	.nbuttons = ARRAY_SIZE(keys),
+};
+
+static void ek_device_add_keyboard(void)
+{
+	int i;
+
+	for (i = 0; i < gk_pdata.nbuttons; i++) {
+		/* user push button, pull up enabled */
+		keys[i].active_low = 1;
+		at91_set_GPIO_periph(keys[i].gpio, keys[i].active_low);
+		at91_set_deglitch(keys[i].gpio, 1);
+	}
+
+	add_gpio_keys_device(-1, &gk_pdata);
+}
+#else
+static void ek_device_add_keyboard(void) {}
+#endif
+
 static int at91sam9m10g45ek_mem_init(void)
 {
 	at91_add_device_sdram(128 * 1024 * 1024);
@@ -178,6 +228,7 @@ static int at91sam9m10g45ek_devices_init(void)
 	at91_add_device_eth(0, &macb_pdata);
 	ek_add_device_mci();
 	ek_device_add_leds();
+	ek_device_add_keyboard();
 
 	devfs_add_partition("nand0", 0x00000, SZ_128K, PARTITION_FIXED, "at91bootstrap_raw");
 	dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap");
diff --git a/arch/arm/boards/at91sam9x5ek/env/config b/arch/arm/boards/at91sam9x5ek/env/config
index cc7286796f..dafe875664 100644
--- a/arch/arm/boards/at91sam9x5ek/env/config
+++ b/arch/arm/boards/at91sam9x5ek/env/config
@@ -15,6 +15,8 @@ dhcp_vendor_id=barebox-at91sam9x5ek
 kernel_loc=nfs
 # can be either 'net', 'nor', 'nand' or 'initrd'
 rootfs_loc=net
+# can be either 'nfs', 'tftp', 'nand' or empty
+oftree_loc=nfs
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
@@ -27,8 +29,8 @@ kernelimage=zImage
 #kernelimage=Image.lzo
 
 nand_device=atmel_nand
-nand_parts="256k(at91bootstrap),384k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),1152k(free),6M(kernel),120M(rootfs),-(data)"
-rootfs_mtdblock_nand=5
+nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),1M(free),4M(kernel),120M(rootfs),-(data)"
+rootfs_mtdblock_nand=7
 
 autoboot_timeout=3
 
diff --git a/arch/arm/boards/beagle/board.c b/arch/arm/boards/beagle/board.c
index 90525d88c2..9ddf3172f2 100644
--- a/arch/arm/boards/beagle/board.c
+++ b/arch/arm/boards/beagle/board.c
@@ -294,12 +294,12 @@ mem_initcall(beagle_mem_init);
 static int beagle_devices_init(void)
 {
 	i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
-	add_generic_device("i2c-omap", -1, NULL, OMAP_I2C1_BASE, SZ_4K,
+	add_generic_device("i2c-omap", DEVICE_ID_DYNAMIC, NULL, OMAP_I2C1_BASE, SZ_4K,
 			   IORESOURCE_MEM, NULL);
 
 #ifdef CONFIG_USB_EHCI_OMAP
 	if (ehci_omap_init(&omap_ehci_pdata) >= 0)
-		add_usb_ehci_device(-1, OMAP_EHCI_BASE,
+		add_usb_ehci_device(DEVICE_ID_DYNAMIC, OMAP_EHCI_BASE,
 				    OMAP_EHCI_BASE + 0x10, &ehci_pdata);
 #endif /* CONFIG_USB_EHCI_OMAP */
 #ifdef CONFIG_OMAP_GPMC
@@ -309,7 +309,7 @@ static int beagle_devices_init(void)
 	gpmc_generic_nand_devices_init(0, 16,
 			OMAP_ECC_HAMMING_CODE_HW_ROMCODE, &omap3_nand_cfg);
 
-	add_generic_device("omap-hsmmc", -1, NULL, OMAP_MMC1_BASE, SZ_4K,
+	add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, OMAP_MMC1_BASE, SZ_4K,
 			   IORESOURCE_MEM, NULL);
 
 	armlinux_set_bootparams((void *)0x80000100);
diff --git a/arch/arm/boards/chumby_falconwing/env/config b/arch/arm/boards/chumby_falconwing/env/config
index 1419161253..bf48da614d 100644
--- a/arch/arm/boards/chumby_falconwing/env/config
+++ b/arch/arm/boards/chumby_falconwing/env/config
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-machine=falconwing
+hostname=falconwing
 
 # use 'dhcp' to do dhcp in barebox and in kernel
 # use 'none' if you want to skip kernel ip autoconfiguration
diff --git a/arch/arm/boards/edb93xx/edb93xx.c b/arch/arm/boards/edb93xx/edb93xx.c
index 70fd12c1bf..e1e8adcddb 100644
--- a/arch/arm/boards/edb93xx/edb93xx.c
+++ b/arch/arm/boards/edb93xx/edb93xx.c
@@ -72,7 +72,8 @@ static int ep93xx_devices_init(void)
 	 * Up to 32MiB NOR type flash, connected to
 	 * CS line 6, data width is 16 bit
 	 */
-	add_generic_device("ep93xx_eth", -1, NULL, 0, 0, IORESOURCE_MEM, NULL);
+	add_generic_device("ep93xx_eth", DEVICE_ID_DYNAMIC, NULL, 0, 0, IORESOURCE_MEM,
+			NULL);
 
 	armlinux_set_bootparams((void *)CONFIG_EP93XX_SDRAM_BANK0_BASE + 0x100);
 
@@ -101,7 +102,7 @@ static int edb93xx_console_init(void)
 	writel(0xAA, &syscon->sysswlock);
 	writel(value, &syscon->devicecfg);
 
-	add_generic_device("pl010_serial", -1, NULL, UART1_BASE, 4096,
+	add_generic_device("pl010_serial", DEVICE_ID_DYNAMIC, NULL, UART1_BASE, 4096,
 			   IORESOURCE_MEM, NULL);
 
 	return 0;
diff --git a/arch/arm/boards/eukrea_cpuimx25/env/config b/arch/arm/boards/eukrea_cpuimx25/env/config
index bc1cfd5060..9d9ff9aef1 100644
--- a/arch/arm/boards/eukrea_cpuimx25/env/config
+++ b/arch/arm/boards/eukrea_cpuimx25/env/config
@@ -3,7 +3,7 @@
 # otg port mode : can be 'host' or 'device'
 otg_mode="device"
 
-machine=eukrea-cpuimx25
+hostname=eukrea-cpuimx25
 
 # use 'dhcp' to do dhcp in barebox and in kernel
 # use 'none' if you want to skip kernel ip autoconfiguration
@@ -22,16 +22,16 @@ rootfs_loc=nand
 
 # rootfs
 rootfs_type=ubifs
-rootfsimage=$machine/rootfs.$rootfs_type
+rootfsimage=$hostname/rootfs.$rootfs_type
 
 # kernel
-kernelimage=$machine/uImage-${machine}.bin
+kernelimage=$hostname/uImage-${hostname}.bin
 
 # barebox and it's env
-bareboximage=$machine/barebox-${machine}.bin
-bareboxenvimage=$machine/bareboxenv-${machine}.bin
+bareboximage=$hostname/barebox-${hostname}.bin
+bareboxenvimage=$hostname/bareboxenv-${hostname}.bin
 
-nfsroot="$eth0.serverip:/srv/nfs/$machine"
+nfsroot="$eth0.serverip:/srv/nfs/$hostname"
 
 autoboot_timeout=1
 
@@ -40,7 +40,7 @@ bootargs="console=ttymxc0,115200 otg_mode=$otg_mode"
 nand_parts="256k(barebox)ro,128k(bareboxenv),3M(kernel),-(root)"
 rootfs_mtdblock_nand=3
 nand_device="mxc_nand"
-ubiroot="$machine-rootfs"
+ubiroot="$hostname-rootfs"
 device_type="nand"
 
 # set a fancy prompt (if support is compiled in)
diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
index 1e48650a9d..c717f0b0a2 100644
--- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
+++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
@@ -164,7 +164,7 @@ static int eukrea_cpuimx25_mem_init(void)
 }
 mem_initcall(eukrea_cpuimx25_mem_init);
 
-static struct pad_desc eukrea_cpuimx25_pads[] = {
+static iomux_v3_cfg_t eukrea_cpuimx25_pads[] = {
 	MX25_PAD_FEC_MDC__FEC_MDC,
 	MX25_PAD_FEC_MDIO__FEC_MDIO,
 	MX25_PAD_FEC_RDATA0__FEC_RDATA0,
@@ -253,9 +253,9 @@ static int eukrea_cpuimx25_devices_init(void)
 
 #ifdef CONFIG_USB
 	imx25_usb_init();
-	add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
+	add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL);
 #endif
-	add_generic_device("fsl-udc", -1, NULL, IMX_OTG_BASE, 0x200,
+	add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, IMX_OTG_BASE, 0x200,
 			   IORESOURCE_MEM, &usb_pdata);
 
 	armlinux_set_bootparams((void *)0x80000100);
diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
index 4d2b482c9a..45ba4f00d1 100644
--- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
+++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
@@ -32,7 +32,6 @@
 #include <asm/armlinux.h>
 #include <asm-generic/sections.h>
 #include <generated/mach-types.h>
-#include <mach/pmic.h>
 #include <partition.h>
 #include <fs.h>
 #include <fcntl.h>
diff --git a/arch/arm/boards/eukrea_cpuimx35/env/config b/arch/arm/boards/eukrea_cpuimx35/env/config
index 8f64ba05ca..1b19bd232e 100644
--- a/arch/arm/boards/eukrea_cpuimx35/env/config
+++ b/arch/arm/boards/eukrea_cpuimx35/env/config
@@ -3,7 +3,7 @@
 # otg port mode : can be 'host' or 'device'
 otg_mode="device"
 
-machine=eukrea-cpuimx35
+hostname=eukrea-cpuimx35
 
 # use 'dhcp' to do dhcp in barebox and in kernel
 # use 'none' if you want to skip kernel ip autoconfiguration
@@ -22,16 +22,16 @@ rootfs_loc=nand
 
 # rootfs
 rootfs_type=ubifs
-rootfsimage=$machine/rootfs.$rootfs_type
+rootfsimage=$hostname/rootfs.$rootfs_type
 
 # kernel
-kernelimage=$machine/uImage-${machine}.bin
+kernelimage=$hostname/uImage-${hostname}.bin
 
 # barebox and it's env
-bareboximage=$machine/barebox-${machine}.bin
-bareboxenvimage=$machine/bareboxenv-${machine}.bin
+bareboximage=$hostname/barebox-${hostname}.bin
+bareboxenvimage=$hostname/bareboxenv-${hostname}.bin
 
-nfsroot="$eth0.serverip:/srv/nfs/$machine"
+nfsroot="$eth0.serverip:/srv/nfs/$hostname"
 
 autoboot_timeout=1
 
@@ -40,7 +40,7 @@ bootargs="console=ttymxc0,115200 otg_mode=$otg_mode"
 nand_parts="256k(barebox)ro,128k(bareboxenv),3M(kernel),-(root)"
 rootfs_mtdblock_nand=3
 nand_device="mxc_nand"
-ubiroot="$machine-rootfs"
+ubiroot="$hostname-rootfs"
 device_type="nand"
 
 # set a fancy prompt (if support is compiled in)
diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
index 17da5699be..37c32ad0db 100644
--- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
+++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
@@ -48,7 +48,6 @@
 #include <mach/imx-regs.h>
 #include <mach/iomux-mx35.h>
 #include <mach/iomux-v3.h>
-#include <mach/pmic.h>
 #include <mach/imx-ipu-fb.h>
 #include <mach/imx-pll.h>
 #include <i2c/i2c.h>
@@ -163,13 +162,13 @@ static int eukrea_cpuimx35_devices_init(void)
 
 #ifdef CONFIG_USB
 	imx35_usb_init();
-	add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
+	add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL);
 #endif
 #ifdef CONFIG_USB_GADGET
 	/* Workaround ENGcm09152 */
 	tmp = readl(IMX_OTG_BASE + 0x608);
 	writel(tmp | (1 << 23), IMX_OTG_BASE + 0x608);
-	add_generic_device("fsl-udc", -1, NULL, IMX_OTG_BASE, 0x200,
+	add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, IMX_OTG_BASE, 0x200,
 			   IORESOURCE_MEM, &usb_pdata);
 #endif
 	armlinux_set_bootparams((void *)0x80000100);
@@ -180,7 +179,7 @@ static int eukrea_cpuimx35_devices_init(void)
 
 device_initcall(eukrea_cpuimx35_devices_init);
 
-static struct pad_desc eukrea_cpuimx35_pads[] = {
+static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = {
 	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
 	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
 	MX35_PAD_FEC_RX_DV__FEC_RX_DV,
diff --git a/arch/arm/boards/eukrea_cpuimx51/env/config b/arch/arm/boards/eukrea_cpuimx51/env/config
index 1b57b29039..531fa4329a 100644
--- a/arch/arm/boards/eukrea_cpuimx51/env/config
+++ b/arch/arm/boards/eukrea_cpuimx51/env/config
@@ -6,7 +6,7 @@ otg_mode="device"
 # ex : 640x480M-16@60 800x600M-24@60 1024x768M-16@60
 video="CMO-QVGA"
 
-machine=eukrea-cpuimx51
+hostname=eukrea-cpuimx51
 
 # use 'dhcp' to do dhcp in barebox and in kernel
 # use 'none' if you want to skip kernel ip autoconfiguration
@@ -25,16 +25,16 @@ rootfs_loc=nand
 
 # rootfs
 rootfs_type=ubifs
-rootfsimage=$machine/rootfs.$rootfs_type
+rootfsimage=$hostname/rootfs.$rootfs_type
 
 # kernel
-kernelimage=$machine/uImage-${machine}.bin
+kernelimage=$hostname/uImage-${hostname}.bin
 
 # barebox and it's env
-bareboximage=$machine/barebox-${machine}.bin
-bareboxenvimage=$machine/bareboxenv-${machine}.bin
+bareboximage=$hostname/barebox-${hostname}.bin
+bareboxenvimage=$hostname/bareboxenv-${hostname}.bin
 
-nfsroot="$eth0.serverip:/srv/nfs/$machine"
+nfsroot="$eth0.serverip:/srv/nfs/$hostname"
 
 autoboot_timeout=1
 
@@ -49,7 +49,7 @@ bootargs="console=ttymxc0,115200 otg_mode=$otg_mode video=$video screen_type=$sc
 nand_parts="256k(barebox)ro,128k(bareboxenv),3M(kernel),-(root)"
 rootfs_mtdblock_nand=3
 nand_device="mxc_nand"
-ubiroot="$machine-rootfs"
+ubiroot="$hostname-rootfs"
 device_type="nand"
 
 # set a fancy prompt (if support is compiled in)
diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
index 6de8f1f192..2bda9743df 100644
--- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
+++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
@@ -52,7 +52,7 @@ struct imx_nand_platform_data nand_info = {
 	.flash_bbt	= 1,
 };
 
-static struct pad_desc eukrea_cpuimx51_pads[] = {
+static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
 	/* FEC */
 	MX51_PAD_DISP2_DAT1__FEC_RX_ER,
 	MX51_PAD_DISP2_DAT15__FEC_TDATA0,
@@ -139,7 +139,7 @@ static int eukrea_cpuimx51_console_init(void)
 {
 	mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads, ARRAY_SIZE(eukrea_cpuimx51_pads));
 
-	imx51_init_lowlevel();
+	imx51_init_lowlevel(800);
 
 	writel(0, 0x73fa8228);
 	writel(0, 0x73fa822c);
diff --git a/arch/arm/boards/freescale-mx25-3-stack/3stack.c b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
index c63467a267..ac781fd134 100644
--- a/arch/arm/boards/freescale-mx25-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
@@ -243,7 +243,7 @@ static int imx25_devices_init(void)
 
 device_initcall(imx25_devices_init);
 
-static struct pad_desc imx25_pads[] = {
+static iomux_v3_cfg_t imx25_pads[] = {
 	MX25_PAD_FEC_MDC__FEC_MDC,
 	MX25_PAD_FEC_MDIO__FEC_MDIO,
 	MX25_PAD_FEC_RDATA0__FEC_RDATA0,
diff --git a/arch/arm/boards/freescale-mx28-evk/env/config b/arch/arm/boards/freescale-mx28-evk/env/config
index 509563388e..3951c5bd06 100644
--- a/arch/arm/boards/freescale-mx28-evk/env/config
+++ b/arch/arm/boards/freescale-mx28-evk/env/config
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-machine=mx28-evk
+hostname=mx28-evk
 #user=
 
 # use 'dhcp' to do dhcp in barebox and in kernel
@@ -24,21 +24,21 @@ rootfs_loc=net
 rootfs_type=ext2
 # where is the rootfs in case of 'rootfs_loc=disk' (linux name)
 rootfs_part_linux_dev=mmcblk0p4
-rootfsimage=rootfs-${machine}.$rootfs_type
+rootfsimage=rootfs-${hostname}.$rootfs_type
 
 # where is the kernel image in case of 'kernel_loc=disk'
 kernel_part=disk0.2
 
-kernelimage=zImage-$machine
-bareboximage=barebox-${machine}.bin
-bareboxenvimage=barebox-${machine}.bin
+kernelimage=zImage-$hostname
+bareboximage=barebox-${hostname}.bin
+bareboxenvimage=barebox-${hostname}.bin
 
 if [ -n $user ]; then
 	bareboximage="$user"-"$bareboximage"
 	bareboxenvimage="$user"-"$bareboxenvimage"
 	kernelimage="$user"-"$kernelimage"
 	rootfsimage="$user"-"$rootfsimage"
-	nfsroot="/home/$user/nfsroot/$machine"
+	nfsroot="/home/$user/nfsroot/$hostname"
 else
 	nfsroot="/path/to/nfs/root"
 fi
diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
index cb30e6ce67..ca8680a82c 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
@@ -46,13 +46,12 @@
 #include <mach/imx-regs.h>
 #include <mach/iomux-mx35.h>
 #include <mach/iomux-v3.h>
-#include <mach/pmic.h>
 #include <mach/imx-ipu-fb.h>
 #include <mach/generic.h>
 #include <mach/devices-imx35.h>
 
 #include <i2c/i2c.h>
-#include <mfd/mc13892.h>
+#include <mfd/mc13xxx.h>
 #include <mfd/mc9sdz60.h>
 
 
@@ -72,7 +71,7 @@ struct imx_nand_platform_data nand_info = {
 
 static struct i2c_board_info i2c_devices[] = {
 	{
-		I2C_BOARD_INFO("mc13892-i2c", 0x08),
+		I2C_BOARD_INFO("mc13xxx-i2c", 0x08),
 	}, {
 		I2C_BOARD_INFO("mc9sdz60", 0x69),
 	},
@@ -182,7 +181,7 @@ static int f3s_devices_init(void)
 	imx35_add_i2c0(NULL);
 
 	imx35_add_fec(&fec_info);
-	add_generic_device("smc911x", -1, NULL,	IMX_CS5_BASE, IMX_CS5_RANGE,
+	add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL,	IMX_CS5_BASE, IMX_CS5_RANGE,
 			IORESOURCE_MEM, NULL);
 
 	imx35_add_mmc0(NULL);
@@ -207,7 +206,7 @@ static int f3s_enable_display(void)
 
 late_initcall(f3s_enable_display);
 
-static struct pad_desc f3s_pads[] = {
+static iomux_v3_cfg_t f3s_pads[] = {
 	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
 	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
 	MX35_PAD_FEC_RX_DV__FEC_RX_DV,
@@ -353,33 +352,33 @@ static int f3s_core_init(void)
 
 core_initcall(f3s_core_init);
 
-static int f3s_get_rev(struct mc13892 *mc13892)
+static int f3s_get_rev(struct mc13xxx *mc13xxx)
 {
 	u32 rev;
 	int err;
 
-	err = mc13892_reg_read(mc13892, MC13892_REG_IDENTIFICATION, &rev);
+	err = mc13xxx_reg_read(mc13xxx, MC13XXX_REG_IDENTIFICATION, &rev);
 	if (err)
 		return err;
 
-	dev_info(&mc13892->client->dev, "revision: 0x%x\n", rev);
+	dev_info(&mc13xxx->client->dev, "revision: 0x%x\n", rev);
 	if (rev == 0x00ffffff)
 		return -ENODEV;
 
 	return ((rev >> 6) & 0x7) ? MX35PDK_BOARD_REV_2 : MX35PDK_BOARD_REV_1;
 }
 
-static int f3s_pmic_init_v2(struct mc13892 *mc13892)
+static int f3s_pmic_init_v2(struct mc13xxx *mc13xxx)
 {
 	int err = 0;
 
 	/* COMPARE pin (GPIO1_5) as output and set high */
 	gpio_direction_output( 32*0 + 5 , 1);
 
-	err |= mc13892_set_bits(mc13892, MC13892_REG_SETTING_0, 0x03, 0x03);
-	err |= mc13892_set_bits(mc13892, MC13892_REG_MODE_0, 0x01, 0x01);
+	err |= mc13xxx_set_bits(mc13xxx, MC13892_REG_SETTING_0, 0x03, 0x03);
+	err |= mc13xxx_set_bits(mc13xxx, MC13892_REG_MODE_0, 0x01, 0x01);
 	if (err)
-		dev_err(&mc13892->client->dev,
+		dev_err(&mc13xxx->client->dev,
 			"Init sequence failed, the system might not be working!\n");
 
 	return err;
@@ -404,22 +403,22 @@ static int f3s_pmic_init_all(struct mc9sdz60 *mc9sdz60)
 
 static int f3s_pmic_init(void)
 {
-	struct mc13892 *mc13892;
+	struct mc13xxx *mc13xxx;
 	struct mc9sdz60 *mc9sdz60;
 	int rev;
 
-	mc13892 = mc13892_get();
-	if (!mc13892) {
-		printf("FAILED to get mc13892 handle!\n");
+	mc13xxx = mc13xxx_get();
+	if (!mc13xxx) {
+		printf("FAILED to get PMIC handle!\n");
 		return 0;
 	}
 
-	rev = f3s_get_rev(mc13892);
+	rev = f3s_get_rev(mc13xxx);
 	switch (rev) {
 	case MX35PDK_BOARD_REV_1:
 		break;
 	case MX35PDK_BOARD_REV_2:
-		f3s_pmic_init_v2(mc13892);
+		f3s_pmic_init_v2(mc13xxx);
 		break;
 	default:
 		printf("FAILED to identify board revision!\n");
diff --git a/arch/arm/boards/freescale-mx35-3-stack/env/config b/arch/arm/boards/freescale-mx35-3-stack/env/config
index 9f37348bf6..171ae8c9bf 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/env/config
+++ b/arch/arm/boards/freescale-mx35-3-stack/env/config
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-machine=mx35-3stack
+hostname=mx35-3stack
 eth0.serverip=
 user=
 
@@ -21,16 +21,16 @@ rootfs_loc=net
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
-rootfsimage=root-$machine.$rootfs_type
+rootfsimage=root-$hostname.$rootfs_type
 
-kernelimage=zImage-$machine
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-$machine.lzo
+kernelimage=zImage-$hostname
+#kernelimage=uImage-$hostname
+#kernelimage=Image-$hostname
+#kernelimage=Image-$hostname.lzo
 
 if [ -n $user ]; then
 	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname"
 	rootfsimage="$user"-"$rootfsimage"
 else
 	nfsroot="$eth0.serverip:/path/to/nfs/root"
diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c
index 2ca4339272..3b1b5741db 100644
--- a/arch/arm/boards/freescale-mx51-pdk/board.c
+++ b/arch/arm/boards/freescale-mx51-pdk/board.c
@@ -32,7 +32,7 @@
 #include <nand.h>
 #include <notifier.h>
 #include <spi/spi.h>
-#include <mfd/mc13892.h>
+#include <mfd/mc13xxx.h>
 #include <io.h>
 #include <asm/mmu.h>
 #include <mach/imx5.h>
@@ -47,7 +47,7 @@ static struct fec_platform_data fec_info = {
 	.xcv_type = MII100,
 };
 
-static struct pad_desc f3s_pads[] = {
+static iomux_v3_cfg_t f3s_pads[] = {
 	MX51_PAD_EIM_EB2__FEC_MDIO,
 	MX51_PAD_EIM_EB3__FEC_RDATA1,
 	MX51_PAD_EIM_CS2__FEC_RDATA2,
@@ -56,7 +56,7 @@ static struct pad_desc f3s_pads[] = {
 	MX51_PAD_EIM_CS5__FEC_CRS,
 	MX51_PAD_NANDF_RB2__FEC_COL,
 	MX51_PAD_NANDF_RB3__FEC_RX_CLK,
-	MX51_PAD_NANDF_RB7__FEC_TX_ER,
+	MX51_PAD_NANDF_CS2__FEC_TX_ER,
 	MX51_PAD_NANDF_CS3__FEC_MDC,
 	MX51_PAD_NANDF_CS4__FEC_TDATA1,
 	MX51_PAD_NANDF_CS5__FEC_TDATA2,
@@ -64,13 +64,13 @@ static struct pad_desc f3s_pads[] = {
 	MX51_PAD_NANDF_CS7__FEC_TX_EN,
 	MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
 	MX51_PAD_NANDF_D11__FEC_RX_DV,
-	MX51_PAD_NANDF_RB6__FEC_RDATA0,
+	MX51_PAD_NANDF_D9__FEC_RDATA0,
 	MX51_PAD_NANDF_D8__FEC_TDATA0,
-	MX51_PAD_CSPI1_SS0__CSPI1_SS0,
-	MX51_PAD_CSPI1_MOSI__CSPI1_MOSI,
-	MX51_PAD_CSPI1_MISO__CSPI1_MISO,
-	MX51_PAD_CSPI1_RDY__CSPI1_RDY,
-	MX51_PAD_CSPI1_SCLK__CSPI1_SCLK,
+	MX51_PAD_CSPI1_SS0__GPIO4_24,
+	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
+	MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
+	MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
+	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
 	MX51_PAD_EIM_A20__GPIO2_14, /* LAN8700 reset pin */
 	IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, 0x85), /* FIXME: needed? */
 	/* SD 1 */
@@ -110,7 +110,7 @@ static struct spi_imx_master spi_0_data = {
 
 static const struct spi_board_info mx51_babbage_spi_board_info[] = {
 	{
-		.name = "mc13892-spi",
+		.name = "mc13xxx-spi",
 		.max_speed_hz = 300000,
 		.bus_num = 0,
 		.chip_select = 0,
@@ -121,101 +121,101 @@ static const struct spi_board_info mx51_babbage_spi_board_info[] = {
 
 static void babbage_power_init(void)
 {
-	struct mc13892 *mc13892;
+	struct mc13xxx *mc13xxx;
 	u32 val;
 
-	mc13892 = mc13892_get();
-	if (!mc13892) {
-		printf("could not get mc13892\n");
+	mc13xxx = mc13xxx_get();
+	if (!mc13xxx) {
+		printf("could not get PMIC\n");
 		return;
 	}
 
 	/* Write needed to Power Gate 2 register */
-	mc13892_reg_read(mc13892, MC13892_REG_POWER_MISC, &val);
+	mc13xxx_reg_read(mc13xxx, MC13892_REG_POWER_MISC, &val);
 	val &= ~0x10000;
-	mc13892_reg_write(mc13892, MC13892_REG_POWER_MISC, val);
+	mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, val);
 
 	/* Write needed to update Charger 0 */
-	mc13892_reg_write(mc13892, MC13892_REG_CHARGE, 0x0023807F);
+	mc13xxx_reg_write(mc13xxx, MC13892_REG_CHARGE, 0x0023807F);
 
 	/* power up the system first */
-	mc13892_reg_write(mc13892, MC13892_REG_POWER_MISC, 0x00200000);
+	mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, 0x00200000);
 
-	if (imx_silicon_revision() < MX51_CHIP_REV_3_0) {
+	if (imx_silicon_revision() < IMX_CHIP_REV_3_0) {
 		/* Set core voltage to 1.1V */
-		mc13892_reg_read(mc13892, MC13892_REG_SW_0, &val);
+		mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_0, &val);
 		val &= ~0x1f;
 		val |= 0x14;
-		mc13892_reg_write(mc13892, MC13892_REG_SW_0, val);
+		mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_0, val);
 
 		/* Setup VCC (SW2) to 1.25 */
-		mc13892_reg_read(mc13892, MC13892_REG_SW_1, &val);
+		mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val);
 		val &= ~0x1f;
 		val |= 0x1a;
-		mc13892_reg_write(mc13892, MC13892_REG_SW_1, val);
+		mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val);
 
 		/* Setup 1V2_DIG1 (SW3) to 1.25 */
-		mc13892_reg_read(mc13892, MC13892_REG_SW_2, &val);
+		mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val);
 		val &= ~0x1f;
 		val |= 0x1a;
-		mc13892_reg_write(mc13892, MC13892_REG_SW_2, val);
+		mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val);
 	} else {
 		/* Setup VCC (SW2) to 1.225 */
-		mc13892_reg_read(mc13892, MC13892_REG_SW_1, &val);
+		mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val);
 		val &= ~0x1f;
 		val |= 0x19;
-		mc13892_reg_write(mc13892, MC13892_REG_SW_1, val);
+		mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val);
 
 		/* Setup 1V2_DIG1 (SW3) to 1.2 */
-		mc13892_reg_read(mc13892, MC13892_REG_SW_2, &val);
+		mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val);
 		val &= ~0x1f;
 		val |= 0x18;
-		mc13892_reg_write(mc13892, MC13892_REG_SW_2, val);
+		mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val);
 	}
 
-	if (mc13892_get_revision(mc13892) < MC13892_REVISION_2_0) {
+	if (mc13xxx->revision < MC13892_REVISION_2_0) {
 		/* Set switchers in PWM mode for Atlas 2.0 and lower */
 		/* Setup the switcher mode for SW1 & SW2*/
-		mc13892_reg_read(mc13892, MC13892_REG_SW_4, &val);
+		mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val);
 		val &= ~0x3c0f;
 		val |= 0x1405;
-		mc13892_reg_write(mc13892, MC13892_REG_SW_4, val);
+		mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val);
 
 		/* Setup the switcher mode for SW3 & SW4 */
-		mc13892_reg_read(mc13892, MC13892_REG_SW_5, &val);
+		mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val);
 		val &= ~0xf0f;
 		val |= 0x505;
-		mc13892_reg_write(mc13892, MC13892_REG_SW_5, val);
+		mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val);
 	} else {
 		/* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
 		/* Setup the switcher mode for SW1 & SW2*/
-		mc13892_reg_read(mc13892, MC13892_REG_SW_4, &val);
+		mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val);
 		val &= ~0x3c0f;
 		val |= 0x2008;
-		mc13892_reg_write(mc13892, MC13892_REG_SW_4, val);
+		mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val);
 
 		/* Setup the switcher mode for SW3 & SW4 */
-		mc13892_reg_read(mc13892, MC13892_REG_SW_5, &val);
+		mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val);
 		val &= ~0xf0f;
 		val |= 0x808;
-		mc13892_reg_write(mc13892, MC13892_REG_SW_5, val);
+		mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val);
 	}
 
 	/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */
-	mc13892_reg_read(mc13892, MC13892_REG_SETTING_0, &val);
+	mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_0, &val);
 	val &= ~0x34030;
 	val |= 0x10020;
-	mc13892_reg_write(mc13892, MC13892_REG_SETTING_0, val);
+	mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_0, val);
 
 	/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
-	mc13892_reg_read(mc13892, MC13892_REG_SETTING_1, &val);
+	mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_1, &val);
 	val &= ~0x1FC;
 	val |= 0x1F4;
-	mc13892_reg_write(mc13892, MC13892_REG_SETTING_1, val);
+	mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_1, val);
 
 	/* Configure VGEN3 and VCAM regulators to use external PNP */
 	val = 0x208;
-	mc13892_reg_write(mc13892, MC13892_REG_MODE_1, val);
+	mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val);
 	udelay(200);
 #define GPIO_LAN8700_RESET	(1 * 32 + 14)
 
@@ -224,7 +224,7 @@ static void babbage_power_init(void)
 
 	/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 	val = 0x49249;
-	mc13892_reg_write(mc13892, MC13892_REG_MODE_1, val);
+	mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val);
 
 	udelay(500);
 
@@ -244,7 +244,7 @@ static int f3s_devices_init(void)
 	babbage_power_init();
 
 	console_flush();
-	imx51_init_lowlevel();
+	imx51_init_lowlevel(800);
 	clock_notifier_call_chain();
 
 	armlinux_set_bootparams((void *)0x90000100);
diff --git a/arch/arm/boards/freescale-mx51-pdk/env/config b/arch/arm/boards/freescale-mx51-pdk/env/config
index 10690c9c50..7a2841e606 100644
--- a/arch/arm/boards/freescale-mx51-pdk/env/config
+++ b/arch/arm/boards/freescale-mx51-pdk/env/config
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-machine=babbage
+hostname=babbage
 eth0.serverip=
 user=
 
@@ -21,16 +21,16 @@ rootfs_loc=net
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
-rootfsimage=root-$machine.$rootfs_type
+rootfsimage=root-$hostname.$rootfs_type
 
-kernelimage=zImage-$machine
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-$machine.lzo
+kernelimage=zImage-$hostname
+#kernelimage=uImage-$hostname
+#kernelimage=Image-$hostname
+#kernelimage=Image-$hostname.lzo
 
 if [ -n $user ]; then
 	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname"
 	rootfsimage="$user"-"$rootfsimage"
 else
 	nfsroot="$eth0.serverip:/path/to/nfs/root"
diff --git a/arch/arm/boards/freescale-mx53-loco/board.c b/arch/arm/boards/freescale-mx53-loco/board.c
index 6ae597adad..ac3323b4ed 100644
--- a/arch/arm/boards/freescale-mx53-loco/board.c
+++ b/arch/arm/boards/freescale-mx53-loco/board.c
@@ -47,7 +47,7 @@ static struct fec_platform_data fec_info = {
 	.xcv_type = RMII,
 };
 
-static struct pad_desc loco_pads[] = {
+static iomux_v3_cfg_t loco_pads[] = {
 	/* UART1 */
 	MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
 	MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
@@ -95,6 +95,8 @@ static struct pad_desc loco_pads[] = {
 	/* I2C0 */
 	MX53_PAD_CSI0_DAT8__I2C1_SDA,
 	MX53_PAD_CSI0_DAT9__I2C1_SCL,
+
+	MX53_PAD_PATA_DA_2__GPIO7_8,
 };
 
 static struct i2c_board_info i2c_devices[] = {
@@ -149,6 +151,7 @@ static void loco_fec_reset(void)
 #define LOCO_SD3_CD			IMX_GPIO_NR(3, 11)
 #define LOCO_SD3_WP			IMX_GPIO_NR(3, 12)
 #define LOCO_SD1_CD			IMX_GPIO_NR(3, 13)
+#define MX53_LOCO_USB_PWREN		IMX_GPIO_NR(7, 8)
 
 static struct esdhc_platform_data loco_sd1_data = {
 	.cd_gpio = LOCO_SD1_CD,
@@ -163,8 +166,19 @@ static struct esdhc_platform_data loco_sd3_data = {
 	.wp_type = ESDHC_WP_GPIO,
 };
 
+static void loco_ehci_init(void)
+{
+	/* USB PWR enable */
+	gpio_direction_output(MX53_LOCO_USB_PWREN, 0);
+	gpio_set_value(MX53_LOCO_USB_PWREN, 1);
+
+	writel(0, MX53_OTG_BASE_ADDR + 0x384); /* setup portsc */
+	add_generic_usb_ehci_device(1, MX53_OTG_BASE_ADDR + 0x200, NULL);
+}
+
 static int loco_devices_init(void)
 {
+
 	imx53_iim_register_fec_ethaddr();
 	imx53_add_fec(&fec_info);
 	imx53_add_mmc0(&loco_sd1_data);
@@ -172,6 +186,9 @@ static int loco_devices_init(void)
 	i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
 	imx53_add_i2c0(NULL);
 
+	if (IS_ENABLED(CONFIG_USB_EHCI))
+		loco_ehci_init();
+
 	loco_fec_reset();
 
 	set_silicon_rev(imx_silicon_revision());
diff --git a/arch/arm/boards/freescale-mx53-loco/env/config b/arch/arm/boards/freescale-mx53-loco/env/config
index fd238a6ac2..bceddafa97 100644
--- a/arch/arm/boards/freescale-mx53-loco/env/config
+++ b/arch/arm/boards/freescale-mx53-loco/env/config
@@ -1,12 +1,13 @@
 #!/bin/sh
 
-machine=loco
+hostname=loco
 eth0.serverip=
 user=
 
 # use 'dhcp' to do dhcp in barebox and in kernel
 # use 'none' if you want to skip kernel ip autoconfiguration
 ip=dhcp
+dhcp_vendor_id=barebox-mx53-loco
 
 # or set your networking parameters here
 #eth0.ipaddr=a.b.c.d
@@ -21,16 +22,16 @@ rootfs_loc=net
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
-rootfsimage=root-$machine.$rootfs_type
+rootfsimage=root-$hostname.$rootfs_type
 
-kernelimage=zImage-$machine
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-$machine.lzo
+kernelimage=zImage-$hostname
+#kernelimage=uImage-$hostname
+#kernelimage=Image-$hostname
+#kernelimage=Image-$hostname.lzo
 
 if [ -n $user ]; then
 	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname"
 	rootfsimage="$user"-"$rootfsimage"
 else
 	nfsroot="$eth0.serverip:/path/to/nfs/root"
diff --git a/arch/arm/boards/freescale-mx53-smd/board.c b/arch/arm/boards/freescale-mx53-smd/board.c
index 72302456eb..b6632555af 100644
--- a/arch/arm/boards/freescale-mx53-smd/board.c
+++ b/arch/arm/boards/freescale-mx53-smd/board.c
@@ -44,7 +44,7 @@ static struct fec_platform_data fec_info = {
 	.xcv_type = RMII,
 };
 
-static struct pad_desc smd_pads[] = {
+static iomux_v3_cfg_t smd_pads[] = {
 	/* UART1 */
 	MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
 	MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
diff --git a/arch/arm/boards/freescale-mx53-smd/env/config b/arch/arm/boards/freescale-mx53-smd/env/config
index fd238a6ac2..d2afb291e8 100644
--- a/arch/arm/boards/freescale-mx53-smd/env/config
+++ b/arch/arm/boards/freescale-mx53-smd/env/config
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-machine=loco
+hostname=loco
 eth0.serverip=
 user=
 
@@ -21,16 +21,16 @@ rootfs_loc=net
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
-rootfsimage=root-$machine.$rootfs_type
+rootfsimage=root-$hostname.$rootfs_type
 
-kernelimage=zImage-$machine
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-$machine.lzo
+kernelimage=zImage-$hostname
+#kernelimage=uImage-$hostname
+#kernelimage=Image-$hostname
+#kernelimage=Image-$hostname.lzo
 
 if [ -n $user ]; then
 	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname"
 	rootfsimage="$user"-"$rootfsimage"
 else
 	nfsroot="$eth0.serverip:/path/to/nfs/root"
diff --git a/arch/arm/boards/freescale-mx6-arm2/Makefile b/arch/arm/boards/freescale-mx6-arm2/Makefile
new file mode 100644
index 0000000000..ad2e1beb99
--- /dev/null
+++ b/arch/arm/boards/freescale-mx6-arm2/Makefile
@@ -0,0 +1 @@
+obj-y += board.o flash_header.o
diff --git a/arch/arm/boards/freescale-mx6-arm2/board.c b/arch/arm/boards/freescale-mx6-arm2/board.c
new file mode 100644
index 0000000000..14224727a2
--- /dev/null
+++ b/arch/arm/boards/freescale-mx6-arm2/board.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) 2012 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <environment.h>
+#include <mach/imx-regs.h>
+#include <fec.h>
+#include <mach/gpio.h>
+#include <asm/armlinux.h>
+#include <generated/mach-types.h>
+#include <partition.h>
+#include <miidev.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <mach/generic.h>
+#include <sizes.h>
+#include <mach/imx6.h>
+#include <mach/devices-imx6.h>
+#include <mach/iomux-mx6.h>
+
+static iomux_v3_cfg_t arm2_pads[] = {
+	/* UART1 */
+	MX6Q_PAD_KEY_COL0__UART4_TXD,
+	MX6Q_PAD_KEY_ROW0__UART4_RXD,
+
+	MX6Q_PAD_SD1_CLK__USDHC1_CLK,
+	MX6Q_PAD_SD1_CMD__USDHC1_CMD,
+	MX6Q_PAD_SD1_DAT0__USDHC1_DAT0,
+	MX6Q_PAD_SD1_DAT1__USDHC1_DAT1,
+	MX6Q_PAD_SD1_DAT2__USDHC1_DAT2,
+	MX6Q_PAD_SD1_DAT3__USDHC1_DAT3,
+
+	MX6Q_PAD_SD2_CLK__USDHC2_CLK,
+	MX6Q_PAD_SD2_CMD__USDHC2_CMD,
+	MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
+	MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
+	MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
+	MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
+
+	MX6Q_PAD_SD3_CLK__USDHC3_CLK,
+	MX6Q_PAD_SD3_CMD__USDHC3_CMD,
+	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0,
+	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1,
+	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2,
+	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3,
+	MX6Q_PAD_SD3_DAT4__USDHC3_DAT4,
+	MX6Q_PAD_SD3_DAT5__USDHC3_DAT5,
+	MX6Q_PAD_SD3_DAT6__USDHC3_DAT6,
+	MX6Q_PAD_SD3_DAT7__USDHC3_DAT7,
+	MX6Q_PAD_GPIO_18__USDHC3_VSELECT,
+
+	MX6Q_PAD_SD4_CLK__USDHC4_CLK,
+	MX6Q_PAD_SD4_CMD__USDHC4_CMD,
+	MX6Q_PAD_SD4_DAT0__USDHC4_DAT0,
+	MX6Q_PAD_SD4_DAT1__USDHC4_DAT1,
+	MX6Q_PAD_SD4_DAT2__USDHC4_DAT2,
+	MX6Q_PAD_SD4_DAT3__USDHC4_DAT3,
+	MX6Q_PAD_SD4_DAT4__USDHC4_DAT4,
+	MX6Q_PAD_SD4_DAT5__USDHC4_DAT5,
+	MX6Q_PAD_SD4_DAT6__USDHC4_DAT6,
+	MX6Q_PAD_SD4_DAT7__USDHC4_DAT7,
+
+	MX6Q_PAD_KEY_COL1__ENET_MDIO,
+	MX6Q_PAD_KEY_COL2__ENET_MDC,
+	MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
+	MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
+	MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
+	MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
+	MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
+	MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
+	MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
+	MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
+	MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
+	MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
+	MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
+	MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
+	MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
+	MX6Q_PAD_GPIO_0__CCM_CLKO,
+	MX6Q_PAD_GPIO_3__CCM_CLKO2,
+};
+
+static int arm2_mem_init(void)
+{
+	arm_add_mem_device("ram0", 0x10000000, SZ_2G);
+
+	return 0;
+}
+mem_initcall(arm2_mem_init);
+
+static struct fec_platform_data fec_info = {
+	.xcv_type = RGMII,
+	.phy_addr = 0,
+};
+
+static int mx6_rgmii_rework(void)
+{
+	struct mii_device *mdev;
+	u16 val;
+
+	mdev = mii_open("phy0");
+	if (!mdev) {
+		printf("unable to open phy0\n");
+		return -ENODEV;
+	}
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	mii_write(mdev, mdev->address, 0xd, 0x7);
+	mii_write(mdev, mdev->address, 0xe, 0x8016);
+	mii_write(mdev, mdev->address, 0xd, 0x4007);
+
+	val = mii_read(mdev, mdev->address, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	mii_write(mdev, mdev->address, 0xe, val);
+
+	/* introduce tx clock delay */
+	mii_write(mdev, mdev->address, 0x1d, 0x5);
+
+	val = mii_read(mdev, mdev->address, 0x1e);
+	val |= 0x0100;
+	mii_write(mdev, mdev->address, 0x1e, val);
+
+	mii_close(mdev);
+
+	return 0;
+}
+
+static int arm2_devices_init(void)
+{
+	imx6_add_mmc3(NULL);
+
+	imx6_add_fec(&fec_info);
+	mx6_rgmii_rework();
+
+	armlinux_set_bootparams((void *)0x10000100);
+	armlinux_set_architecture(3837);
+
+	devfs_add_partition("disk0", 0, SZ_1M, PARTITION_FIXED, "self0");
+	devfs_add_partition("disk0", SZ_1M + SZ_1M, SZ_512K, PARTITION_FIXED, "env0");
+
+	return 0;
+}
+
+device_initcall(arm2_devices_init);
+
+static int arm2_console_init(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(arm2_pads, ARRAY_SIZE(arm2_pads));
+
+	imx6_init_lowlevel();
+
+	imx6_add_uart3();
+
+	return 0;
+}
+console_initcall(arm2_console_init);
diff --git a/arch/arm/boards/freescale-mx6-arm2/config.h b/arch/arm/boards/freescale-mx6-arm2/config.h
new file mode 100644
index 0000000000..ca15136817
--- /dev/null
+++ b/arch/arm/boards/freescale-mx6-arm2/config.h
@@ -0,0 +1,4 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#endif	/* __CONFIG_H */
diff --git a/arch/arm/boards/freescale-mx6-arm2/env/config b/arch/arm/boards/freescale-mx6-arm2/env/config
new file mode 100644
index 0000000000..0ab5bdf0e0
--- /dev/null
+++ b/arch/arm/boards/freescale-mx6-arm2/env/config
@@ -0,0 +1,47 @@
+#!/bin/sh
+
+machine=armadillo2
+serverip=
+user=
+
+# use 'dhcp' to do dhcp in barebox and in kernel
+# use 'none' if you want to skip kernel ip autoconfiguration
+ip=dhcp
+
+# or set your networking parameters here
+#eth0.ipaddr=a.b.c.d
+#eth0.netmask=a.b.c.d
+#eth0.gateway=a.b.c.d
+#eth0.serverip=a.b.c.d
+
+# can be either 'nfs', 'tftp', 'nor' or 'nand'
+kernel_loc=tftp
+# can be either 'net', 'nor', 'nand' or 'initrd'
+rootfs_loc=disk
+
+# can be either 'jffs2' or 'ubifs'
+rootfs_type=ubifs
+rootfsimage=root-$machine.$rootfs_type
+
+# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
+kernelimage=zImage-$machine
+
+if [ -n $user ]; then
+	kernelimage="$user"-"$kernelimage"
+	nfsroot="$serverip:/home/$user/nfsroot/$machine"
+	rootfsimage="$user"-"$rootfsimage"
+else
+	nfsroot="$serverip:/path/to/nfs/root"
+fi
+
+autoboot_timeout=3
+
+bootargs="console=ttymxc2,115200"
+
+disk_parts="1M(barebox)ro,3M(bareboxenv),4M(kernel),-(root)"
+
+rootfs_part_linux_dev=sda1
+rootfs_type=ext2
+
+# set a fancy prompt (if support is compiled in)
+PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
diff --git a/arch/arm/boards/freescale-mx6-arm2/flash_header.c b/arch/arm/boards/freescale-mx6-arm2/flash_header.c
new file mode 100644
index 0000000000..79f3113359
--- /dev/null
+++ b/arch/arm/boards/freescale-mx6-arm2/flash_header.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <asm/byteorder.h>
+#include <mach/imx-flash-header.h>
+#include <mach/imx6-regs.h>
+
+void __naked __flash_header_start go(void)
+{
+	__asm__ __volatile__("b exception_vectors\n");
+}
+
+#define DCD(a, v) { .addr = cpu_to_be32(a), .val = cpu_to_be32(v), }
+
+struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x5a8, 0x00000030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x5b0, 0x00000030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x524, 0x00000030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x51c, 0x00000030),
+
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x518, 0x00000030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x50c, 0x00000030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x5b8, 0x00000030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x5c0, 0x00000030),
+
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x5ac, 0x00020030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x5b4, 0x00020030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x528, 0x00020030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x520, 0x00020030),
+
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x514, 0x00020030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x510, 0x00020030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x5bc, 0x00020030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x5c4, 0x00020030),
+
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x56c, 0x00020030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x578, 0x00020030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x588, 0x00020030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x594, 0x00020030),
+
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x57c, 0x00020030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x590, 0x00003000),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x598, 0x00003000),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x58c, 0x00000000),
+
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x59c, 0x00003030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x5a0, 0x00003030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x784, 0x00000030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x788, 0x00000030),
+
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x794, 0x00000030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x79c, 0x00000030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x7a0, 0x00000030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x7a4, 0x00000030),
+
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x7a8, 0x00000030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x748, 0x00000030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x74c, 0x00000030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x750, 0x00020000),
+
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x758, 0x00000000),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x774, 0x00020000),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x78c, 0x00000030),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x798, 0x000C0000),
+
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x81c, 0x33333333),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x820, 0x33333333),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x824, 0x33333333),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x828, 0x33333333),
+
+	DCD(MX6_MMDC_P1_BASE_ADDR + 0x81c, 0x33333333),
+	DCD(MX6_MMDC_P1_BASE_ADDR + 0x820, 0x33333333),
+	DCD(MX6_MMDC_P1_BASE_ADDR + 0x824, 0x33333333),
+	DCD(MX6_MMDC_P1_BASE_ADDR + 0x828, 0x33333333),
+
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x018, 0x00081740),
+
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00008000),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x00c, 0x555A7975),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2),
+
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x030, 0x005B0E21),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x008, 0x09444040),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x004, 0x00025576),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x040, 0x00000027),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x000, 0xC31A0000),
+
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04088032),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x0408803A),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00008033),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00428031),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00428039),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x09408030),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x09408038),
+
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04008040),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04008048),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x800, 0xA1380003),
+	DCD(MX6_MMDC_P1_BASE_ADDR + 0x800, 0xA1380003),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x020, 0x00005800),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x818, 0x00022227),
+	DCD(MX6_MMDC_P1_BASE_ADDR + 0x818, 0x00022227),
+
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x83c, 0x434B0350),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x840, 0x034C0359),
+	DCD(MX6_MMDC_P1_BASE_ADDR + 0x83c, 0x434B0350),
+	DCD(MX6_MMDC_P1_BASE_ADDR + 0x840, 0x03650348),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x848, 0x4436383B),
+	DCD(MX6_MMDC_P1_BASE_ADDR + 0x848, 0x39393341),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x850, 0x35373933),
+	DCD(MX6_MMDC_P1_BASE_ADDR + 0x850, 0x48254A36),
+
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x810, 0x001F001F),
+
+	DCD(MX6_MMDC_P1_BASE_ADDR + 0x80c, 0x00440044),
+	DCD(MX6_MMDC_P1_BASE_ADDR + 0x810, 0x00440044),
+
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800),
+	DCD(MX6_MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800),
+
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00000000),
+	DCD(MX6_MMDC_P0_BASE_ADDR + 0x404, 0x00011006),
+
+	/* enable AXI cache for VDOA/VPU/IPU */
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x010, 0xf00000ff),
+	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x018, 0x007f007f),
+	DCD(MX6_IOMUXC_BASE_ADDR + 0x01c, 0x007f007f),
+};
+
+#define APP_DEST	CONFIG_TEXT_BASE
+
+struct imx_flash_header_v2 __flash_header_section flash_header = {
+	.header.tag		= IVT_HEADER_TAG,
+	.header.length		= cpu_to_be16(32),
+	.header.version		= IVT_VERSION,
+
+	.entry			= APP_DEST + 0x1000,
+	.dcd_ptr		= APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, dcd),
+	.boot_data_ptr		= APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, boot_data),
+	.self			= APP_DEST + 0x400,
+
+	.boot_data.start	= APP_DEST,
+	.boot_data.size		= 0x40000,
+
+	.dcd.header.tag		= DCD_HEADER_TAG,
+	.dcd.header.length	= cpu_to_be16(sizeof(struct imx_dcd) + sizeof(dcd_entry)),
+	.dcd.header.version	= DCD_VERSION,
+
+	.dcd.command.tag	= DCD_COMMAND_WRITE_TAG,
+	.dcd.command.length	= cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)),
+	.dcd.command.param	= DCD_COMMAND_WRITE_PARAM,
+};
diff --git a/arch/arm/boards/guf-cupid/board.c b/arch/arm/boards/guf-cupid/board.c
index 577d80e5e3..653d4408f9 100644
--- a/arch/arm/boards/guf-cupid/board.c
+++ b/arch/arm/boards/guf-cupid/board.c
@@ -146,7 +146,7 @@ static int cupid_devices_init(void)
 
 device_initcall(cupid_devices_init);
 
-static struct pad_desc cupid_pads[] = {
+static iomux_v3_cfg_t cupid_pads[] = {
 	/* UART1 */
 	MX35_PAD_CTS1__UART1_CTS,
 	MX35_PAD_RTS1__UART1_RTS,
diff --git a/arch/arm/boards/guf-cupid/env/config b/arch/arm/boards/guf-cupid/env/config
index 930a97d1e6..1be875d048 100644
--- a/arch/arm/boards/guf-cupid/env/config
+++ b/arch/arm/boards/guf-cupid/env/config
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-machine=cupid
+hostname=cupid
 eth0.serverip=
 user=
 
@@ -21,16 +21,16 @@ rootfs_loc=net
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
-rootfsimage=root-$machine.$rootfs_type
+rootfsimage=root-$hostname.$rootfs_type
 
-kernelimage=zImage-$machine
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-$machine.lzo
+kernelimage=zImage-$hostname
+#kernelimage=uImage-$hostname
+#kernelimage=Image-$hostname
+#kernelimage=Image-$hostname.lzo
 
 if [ -n $user ]; then
 	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname"
 	rootfsimage="$user"-"$rootfsimage"
 else
 	nfsroot="$eth0.serverip:/path/to/nfs/root"
diff --git a/arch/arm/boards/guf-neso/env/config b/arch/arm/boards/guf-neso/env/config
index 9b675b5920..3013728263 100644
--- a/arch/arm/boards/guf-neso/env/config
+++ b/arch/arm/boards/guf-neso/env/config
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-machine=guf-neso
+hostname=guf-neso
 eth0.serverip=
 user=
 
@@ -21,16 +21,16 @@ rootfs_loc=net
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
-rootfsimage=root-$machine.$rootfs_type
+rootfsimage=root-$hostname.$rootfs_type
 
-kernelimage=zImage-$machine
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-$machine.lzo
+kernelimage=zImage-$hostname
+#kernelimage=uImage-$hostname
+#kernelimage=Image-$hostname
+#kernelimage=Image-$hostname.lzo
 
 if [ -n $user ]; then
 	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname"
 	rootfsimage="$user"-"$rootfsimage"
 else
 	nfsroot="$eth0.serverip:/path/to/nfs/root"
diff --git a/arch/arm/boards/imx21ads/imx21ads.c b/arch/arm/boards/imx21ads/imx21ads.c
index a0c9fb6722..e39441789e 100644
--- a/arch/arm/boards/imx21ads/imx21ads.c
+++ b/arch/arm/boards/imx21ads/imx21ads.c
@@ -168,7 +168,7 @@ static int mx21ads_devices_init(void)
 
 	add_cfi_flash_device(-1, 0xC8000000, 32 * 1024 * 1024, 0);
 	imx21_add_nand(&nand_info);
-	add_generic_device("cs8900", -1, NULL,	IMX_CS1_BASE, 0x1000,
+	add_generic_device("cs8900", DEVICE_ID_DYNAMIC, NULL, IMX_CS1_BASE, 0x1000,
 			IORESOURCE_MEM, NULL);
 	imx21_add_fb(&imx_fb_data);
 
diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c
index 451d91df75..7df2e4c6ec 100644
--- a/arch/arm/boards/karo-tx25/board.c
+++ b/arch/arm/boards/karo-tx25/board.c
@@ -64,7 +64,7 @@ static int tx25_mem_init(void)
 }
 mem_initcall(tx25_mem_init);
 
-static struct pad_desc karo_tx25_padsd_fec[] = {
+static iomux_v3_cfg_t karo_tx25_padsd_fec[] = {
 	MX25_PAD_D11__GPIO_4_9,		/* FEC PHY power on pin */
 	MX25_PAD_D13__GPIO_4_7,		/* FEC reset */
 	MX25_PAD_FEC_MDC__FEC_MDC,
@@ -131,7 +131,7 @@ static int tx25_devices_init(void)
 
 device_initcall(tx25_devices_init);
 
-static struct pad_desc tx25_pads[] = {
+static iomux_v3_cfg_t tx25_pads[] = {
 	MX25_PAD_D12__GPIO_4_8,
 	MX25_PAD_D10__GPIO_4_10,
 	MX25_PAD_NF_CE0__NF_CE0,
@@ -172,7 +172,7 @@ void __bare_init nand_boot(void)
 }
 #endif
 
-static struct pad_desc tx25_lcdc_gpios[] = {
+static iomux_v3_cfg_t tx25_lcdc_gpios[] = {
 	MX25_PAD_A18__GPIO_2_4,		/* LCD Reset (active LOW) */
 	MX25_PAD_PWM__GPIO_1_26,	/* LCD Backlight brightness 0: full 1: off */
 	MX25_PAD_A19__GPIO_2_5,		/* LCD Power Enable 0: off 1: on */
diff --git a/arch/arm/boards/karo-tx25/env/config b/arch/arm/boards/karo-tx25/env/config
index 69f2c26c3d..28a5e7f27c 100644
--- a/arch/arm/boards/karo-tx25/env/config
+++ b/arch/arm/boards/karo-tx25/env/config
@@ -1,5 +1,5 @@
 
-machine=tx25
+hostname=tx25
 baseboard=tx28stk5
 user=
 
@@ -21,16 +21,16 @@ rootfs_loc=net
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
-rootfsimage=root-$machine.$rootfs_type
+rootfsimage=root-$hostname.$rootfs_type
 
-kernelimage=zImage-$machine
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-$machine.lzo
+kernelimage=zImage-$hostname
+#kernelimage=uImage-$hostname
+#kernelimage=Image-$hostname
+#kernelimage=Image-$hostname.lzo
 
 if [ -n $user ]; then
 	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname"
 	rootfsimage="$user"-"$rootfsimage"
 else
 	nfsroot="$eth0.serverip:/path/to/nfs/root"
diff --git a/arch/arm/boards/karo-tx28/env/config b/arch/arm/boards/karo-tx28/env/config
index ed361ebd26..b5222e99dc 100644
--- a/arch/arm/boards/karo-tx28/env/config
+++ b/arch/arm/boards/karo-tx28/env/config
@@ -1,7 +1,7 @@
 #
 #
 
-machine=tx28
+hostname=tx28
 baseboard=tx28stk5
 
 # use 'dhcp' to do dhcp in barebox and in kernel
@@ -22,16 +22,16 @@ rootfs_loc=net
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
-rootfsimage=root-$machine.$rootfs_type
+rootfsimage=root-$hostname.$rootfs_type
 
-kernelimage=zImage-$machine
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-$machine.lzo
+kernelimage=zImage-$hostname
+#kernelimage=uImage-$hostname
+#kernelimage=Image-$hostname
+#kernelimage=Image-$hostname.lzo
 
 if [ -n $user ]; then
 	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname"
 	rootfsimage="$user"-"$rootfsimage"
 else
 	nfsroot="$eth0.serverip:/path/to/nfs/root"
diff --git a/arch/arm/boards/karo-tx28/tx28-stk5.c b/arch/arm/boards/karo-tx28/tx28-stk5.c
index b36d8226e5..04fdbc37b9 100644
--- a/arch/arm/boards/karo-tx28/tx28-stk5.c
+++ b/arch/arm/boards/karo-tx28/tx28-stk5.c
@@ -21,11 +21,13 @@
 #include <fec.h>
 #include <sizes.h>
 #include <io.h>
+#include <net.h>
 #include <asm/sections.h>
 #include <mach/imx-regs.h>
 #include <mach/clock.h>
 #include <mach/mci.h>
 #include <mach/fb.h>
+#include <mach/ocotp.h>
 
 static struct mxs_mci_platform_data mci_pdata = {
 	.caps = MMC_MODE_4BIT,
@@ -345,6 +347,22 @@ static int register_persistent_environment(void)
 					DEVFS_PARTITION_FIXED, "env0");
 }
 
+void tx28_get_ethaddr(void)
+{
+	u32 buf[2];	/* to make use of cpu_to_be32 */
+	u32 ethaddr[2];
+	int ret;
+
+	ret = mxs_ocotp_read(buf, 8, 0);
+	if (ret != 8)
+		return;
+
+	ethaddr[0] = cpu_to_be32(buf[0]);
+	ethaddr[1] = cpu_to_be32(buf[1]);
+
+	eth_register_ethaddr(0, (char *)ethaddr);
+}
+
 void base_board_init(void)
 {
 	int i, ret;
@@ -369,6 +387,11 @@ void base_board_init(void)
 	add_generic_device("stmfb", 0, NULL, IMX_FB_BASE, 4096,
 			   IORESOURCE_MEM, &tx28_fb_pdata);
 
+	add_generic_device("ocotp", 0, NULL, IMX_OCOTP_BASE, 0,
+			   IORESOURCE_MEM, NULL);
+
+	tx28_get_ethaddr();
+
 	imx_enable_enetclk();
 	add_generic_device("fec_imx", 0, NULL, IMX_FEC0_BASE, 0,
 			   IORESOURCE_MEM, &fec_info);
diff --git a/arch/arm/boards/karo-tx51/Makefile b/arch/arm/boards/karo-tx51/Makefile
new file mode 100644
index 0000000000..e8f710e1ac
--- /dev/null
+++ b/arch/arm/boards/karo-tx51/Makefile
@@ -0,0 +1,2 @@
+obj-y += tx51.o
+obj-y += flash_header.o
diff --git a/arch/arm/boards/karo-tx51/config.h b/arch/arm/boards/karo-tx51/config.h
new file mode 100644
index 0000000000..b908fc09af
--- /dev/null
+++ b/arch/arm/boards/karo-tx51/config.h
@@ -0,0 +1,21 @@
+/**
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#endif	/* __CONFIG_H */
diff --git a/arch/arm/boards/karo-tx51/env/config b/arch/arm/boards/karo-tx51/env/config
new file mode 100644
index 0000000000..755eaec2c1
--- /dev/null
+++ b/arch/arm/boards/karo-tx51/env/config
@@ -0,0 +1,42 @@
+#!/bin/sh
+
+machine=tx51
+
+# use 'dhcp' to do dhcp in barebox and in kernel
+# use 'none' if you want to skip kernel ip autoconfiguration
+ip=dhcp
+
+
+# or set your networking parameters here
+#eth0.ipaddr=a.b.c.d
+#eth0.ethaddr=de:ad:be:ef:00:00
+#eth0.netmask=a.b.c.d
+#eth0.serverip=a.b.c.d
+#eth0.gateway=a.b.c.d
+
+# can be either 'nfs', 'tftp', 'nor' or 'nand'
+kernel_loc=tftp
+# can be either 'net', 'nor', 'nand' or 'initrd'
+rootfs_loc=net
+
+# can be either 'jffs2' or 'ubifs'
+rootfs_type=ubifs
+rootfsimage=root-$machine.$rootfs_type
+
+kernelimage=zImage_$machine
+#kernelimage=uImage-$machine
+#kernelimage=Image-$machine
+#kernelimage=Image-$machine.lzo
+kernel_part=nand0.kernel
+
+#nfsroot="$serverip:/srv/root"
+
+autoboot_timeout=3
+
+bootargs="console=ttymxc0,115200"
+
+nand_device=mxc_nand
+nand_parts="256k(barebox)ro,256k(bareboxenv),4M@0xc00000(kernel),64M(rootfs),-(rootfs_data)"
+
+# set a fancy prompt (if support is compiled in)
+PS1="\e[1;32mbarebox@\e[1;31mtx51:\w\e[0m "
diff --git a/arch/arm/boards/karo-tx51/flash_header.c b/arch/arm/boards/karo-tx51/flash_header.c
new file mode 100644
index 0000000000..7d2f97e347
--- /dev/null
+++ b/arch/arm/boards/karo-tx51/flash_header.c
@@ -0,0 +1,56 @@
+/**
+ * Copyright (C) 2012 Christian Kapeller, <christian.kapeller@cmotion.eu>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/barebox-arm-head.h>
+#include <mach/imx-flash-header.h>
+
+void __naked __flash_header_start go(void)
+{
+	barebox_arm_head();
+}
+
+struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
+    { .ptr_type = 4, .addr = 0x83fd9000, .val = 0x80000000, },
+    { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, },
+    { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, },
+    { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, },
+    { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00338018, },
+    { .ptr_type = 4, .addr = 0x83fd9000, .val = 0xb2220000, },
+    { .ptr_type = 4, .addr = 0x83fd9004, .val = 0xb08564a9, },
+    { .ptr_type = 4, .addr = 0x83fd9034, .val = 0x20020000, },
+    { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000a0080, },
+    { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00000000, },
+};
+
+#define APP_DEST	CONFIG_ARCH_TEXT_BASE
+
+struct imx_flash_header __flash_header_section flash_header = {
+	.app_code_jump_vector	= APP_DEST + 0x1000,
+	.app_code_barker	= APP_CODE_BARKER,
+	.app_code_csf		= 0,
+	.dcd_ptr_ptr		= APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd),
+	.super_root_key		= 0,
+	.dcd			= APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd_barker),
+	.app_dest		= APP_DEST,
+	.dcd_barker		= DCD_BARKER,
+	.dcd_block_len		= sizeof (dcd_entry),
+};
+
+unsigned long __image_len_section barebox_len = DCD_BAREBOX_SIZE;
diff --git a/arch/arm/boards/karo-tx51/tx51.c b/arch/arm/boards/karo-tx51/tx51.c
new file mode 100644
index 0000000000..b0b4278dd3
--- /dev/null
+++ b/arch/arm/boards/karo-tx51/tx51.c
@@ -0,0 +1,291 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
+ * Copyright (C) 2012 Christian Kapeller, <christian.kapeller@cmotion.eu>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <environment.h>
+#include <mach/imx-regs.h>
+#include <fec.h>
+#include <mach/gpio.h>
+#include <asm/armlinux.h>
+#include <generated/mach-types.h>
+#include <partition.h>
+#include <fs.h>
+#include <fcntl.h>
+#include <nand.h>
+#include <spi/spi.h>
+#include <mfd/mc13xxx.h>
+#include <io.h>
+#include <asm/mmu.h>
+#include <mach/imx5.h>
+#include <mach/imx-nand.h>
+#include <mach/spi.h>
+#include <mach/generic.h>
+#include <mach/iomux-mx51.h>
+#include <mach/devices-imx51.h>
+#include <mach/iim.h>
+
+
+#define STK5_MX51_PAD_DISPB2_SER_RS__GPIO3_8 \
+    IOMUX_PAD(0x6C8, 0x2C8, 4, 0x994, 1, PAD_CTL_PKE | PAD_CTL_PUE)
+
+#define STK5_MX51_PAD_DISPB2_SER_DIO__GPIO3_6 \
+    IOMUX_PAD(0x6c0, 0x2c0, 4, 0x098c, 1, 0)
+
+static struct fec_platform_data fec_info = {
+	.xcv_type = MII100,
+};
+
+struct imx_nand_platform_data nand_info = {
+	.width	= 1,
+	.hw_ecc	= 1,
+	.flash_bbt = 1,
+};
+
+struct gpio_led tx51_leds[] = {
+	{
+		.led = { .name = "GPIO-LED", },
+		.gpio = IMX_GPIO_NR(4,10),
+		.active_low = 0,
+	},
+};
+
+static iomux_v3_cfg_t tx51_pads[] = {
+	/*UART1*/
+	MX51_PAD_UART1_RXD__UART1_RXD,
+	MX51_PAD_UART1_TXD__UART1_TXD,
+	MX51_PAD_UART1_CTS__UART1_CTS,
+	MX51_PAD_UART1_RTS__UART1_RTS,
+
+	/* (e)CSPI */
+	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
+	MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
+	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
+	MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
+
+	/* (e)CSPI chip select lines */
+	MX51_PAD_CSPI1_SS0__GPIO4_24,
+	MX51_PAD_CSPI1_SS1__GPIO4_25,
+
+#ifdef CONFIG_MCI_IMX_ESDHC
+	/* eSDHC 1 */
+	MX51_PAD_SD1_CMD__SD1_CMD,
+	MX51_PAD_SD1_CLK__SD1_CLK,
+	MX51_PAD_SD1_DATA0__SD1_DATA0,
+	MX51_PAD_SD1_DATA1__SD1_DATA1,
+	MX51_PAD_SD1_DATA2__SD1_DATA2,
+	MX51_PAD_SD1_DATA3__SD1_DATA3,
+
+	/* SD1 card detect */
+	STK5_MX51_PAD_DISPB2_SER_RS__GPIO3_8,
+
+	/* eSDHC 2 */
+	MX51_PAD_SD2_CMD__SD2_CMD,
+	MX51_PAD_SD2_CLK__SD2_CLK,
+	MX51_PAD_SD2_DATA0__SD2_DATA0,
+	MX51_PAD_SD2_DATA1__SD2_DATA1,
+	MX51_PAD_SD2_DATA2__SD2_DATA2,
+	MX51_PAD_SD2_DATA3__SD2_DATA3,
+
+	/* SD2 card detect */
+	STK5_MX51_PAD_DISPB2_SER_DIO__GPIO3_6,
+#endif
+
+	/* SW controlled LED on STK5 baseboard */
+	MX51_PAD_CSI2_D13__GPIO4_10,
+
+	/* unuseable pads configured as GPIO */
+	MX51_PAD_GPIO1_1__GPIO1_1,
+	MX51_PAD_GPIO1_0__GPIO1_0,
+};
+
+static int tx51_mem_init(void)
+{
+	arm_add_mem_device("ram0", MX51_CSD0_BASE_ADDR, 128 * 1024 * 1024);
+
+	return 0;
+}
+mem_initcall(tx51_mem_init);
+
+static int spi_0_cs[] = {
+	IMX_GPIO_NR(4, 24),
+	IMX_GPIO_NR(4, 25),
+};
+
+static struct spi_imx_master tx51_spi_0_data = {
+	.chipselect = spi_0_cs,
+	.num_chipselect = ARRAY_SIZE(spi_0_cs),
+};
+
+static const struct spi_board_info mx51_tx51_spi_board_info[] = {};
+
+static struct tx51_fec_gpio_setup {
+	iomux_v3_cfg_t pad;
+	unsigned group:4,
+		shift:5,
+		level:1;
+} tx51_fec_gpios[] = {
+	{ MX51_PAD_EIM_A20__GPIO2_14,	2, 14, 0 }, /* PHY reset */
+	{ MX51_PAD_GPIO1_3__GPIO1_3,	1, 3, 0 }, /* PHY power enable */
+	{ MX51_PAD_NANDF_CS3__GPIO3_19,	3, 19, 0 }, /* MDC */
+	{ MX51_PAD_EIM_EB2__GPIO2_22,	2, 22, 0 }, /* MDIO */
+	{ MX51_PAD_NANDF_RB3__GPIO3_11,	3, 11, 0 }, /* RX_CLK */
+	{ MX51_PAD_NANDF_D11__GPIO3_29,	3, 29, 0 }, /* RX_DV */
+	{ MX51_PAD_NANDF_D9__GPIO3_31,	3, 31, 1 }, /* RXD0/Mode0 */
+	{ MX51_PAD_EIM_EB3__GPIO2_23,	2, 23, 1 }, /* RXD1/Mode1 */
+	{ MX51_PAD_EIM_CS2__GPIO2_27,	2, 27, 1 }, /* RXD2/Mode2 */
+	{ MX51_PAD_EIM_CS3__GPIO2_28,	2, 28, 1 }, /* RXD3/nINTSEL */
+	{ MX51_PAD_EIM_CS4__GPIO2_29,	2, 29, 0 }, /* RX_ER/RXD4 */
+	{ MX51_PAD_NANDF_RDY_INT__GPIO3_24,	3, 24, 0 }, /* TX_CLK */
+	{ MX51_PAD_NANDF_CS7__GPIO3_23,	3, 23, 0 }, /* TX_EN */
+	{ MX51_PAD_NANDF_D8__GPIO4_0,	4, 0, 0 }, /* TXD0 */
+	{ MX51_PAD_NANDF_CS4__GPIO3_20,	3, 20, 0 }, /* TXD1 */
+	{ MX51_PAD_NANDF_CS5__GPIO3_21,	3, 21, 0 }, /* TXD2 */
+	{ MX51_PAD_NANDF_CS6__GPIO3_22,	3, 22, 0 }, /* TXD3 */
+	{ MX51_PAD_NANDF_RB2__GPIO3_10,	3, 10, 0 }, /* COL/RMII/CRSDV */
+	{ MX51_PAD_EIM_CS5__GPIO2_30,	2, 30, 0 }, /* CRS */
+	{ MX51_PAD_NANDF_CS2__GPIO3_18,	3, 18, 0 }, /* nINT/TX_ER/TXD4 */
+};
+
+static iomux_v3_cfg_t tx51_fec_pads[] = {
+	MX51_PAD_NANDF_CS2__FEC_TX_ER,
+	MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
+	MX51_PAD_NANDF_CS3__FEC_MDC,
+	MX51_PAD_NANDF_CS4__FEC_TDATA1,
+	MX51_PAD_NANDF_CS5__FEC_TDATA2,
+	MX51_PAD_NANDF_CS6__FEC_TDATA3,
+	MX51_PAD_NANDF_CS7__FEC_TX_EN,
+	MX51_PAD_NANDF_RB2__FEC_COL,
+	MX51_PAD_NANDF_RB3__FEC_RX_CLK,
+	MX51_PAD_NANDF_D8__FEC_TDATA0,
+	MX51_PAD_NANDF_D9__FEC_RDATA0,
+	MX51_PAD_NANDF_D11__FEC_RX_DV,
+	MX51_PAD_EIM_EB2__FEC_MDIO,
+	MX51_PAD_EIM_EB3__FEC_RDATA1,
+	MX51_PAD_EIM_CS2__FEC_RDATA2,
+	MX51_PAD_EIM_CS3__FEC_RDATA3,
+	MX51_PAD_EIM_CS4__FEC_RX_ER,
+	MX51_PAD_EIM_CS5__FEC_CRS,
+};
+
+#define TX51_FEC_PHY_RST	IMX_GPIO_NR(2, 14)
+#define TX51_FEC_PHY_PWR	IMX_GPIO_NR(1, 3)
+#define TX51_FEC_PHY_INT	IMX_GPIO_NR(3, 18)
+
+static inline void tx51_fec_init(void)
+{
+	int i;
+
+	/* Configure LAN8700 pads as GPIO and set up
+	 * necessary strap options for PHY
+	 */
+	for (i = 0; i < ARRAY_SIZE(tx51_fec_gpios); i++) {
+		struct tx51_fec_gpio_setup *gs = &tx51_fec_gpios[i];
+
+		gpio_direction_output(IMX_GPIO_NR(gs->group, gs->shift ), gs->level);
+		mxc_iomux_v3_setup_pad(gs->pad);
+	}
+
+	/*
+	 *Turn on phy power, leave in reset state
+	 */
+	gpio_set_value(TX51_FEC_PHY_PWR, 1);
+
+	/*
+	 * Wait some time to let the phy activate the internal regulator
+	 */
+	mdelay(10);
+
+	/*
+	 * Deassert reset, phy latches the rest of bootstrap pins
+	 */
+	gpio_set_value(TX51_FEC_PHY_RST, 1);
+
+	/* LAN7800 has an internal Power On Reset (POR) signal (OR'ed with
+	 * the external RESET signal) which is deactivated 21ms after
+	 * power on and latches the strap options.
+	 * Delay for 22ms to ensure, that the internal POR is inactive
+	 * before reconfiguring the strap pins.
+	 */
+	mdelay(22);
+
+	/*
+	 * The phy is ready, now configure imx51 pads for fec operation
+	 */
+	mxc_iomux_v3_setup_multiple_pads(tx51_fec_pads,
+			ARRAY_SIZE(tx51_fec_pads));
+}
+
+static void tx51_leds_init(void)
+{
+	int i;
+
+	for (i = 0 ; i < ARRAY_SIZE(tx51_leds) ; i++)
+		led_gpio_register(&tx51_leds[i]);
+}
+
+static int tx51_devices_init(void)
+{
+#ifdef CONFIG_MCI_IMX_ESDHC
+	imx51_add_mmc0(NULL);
+	imx51_add_mmc1(NULL);
+#endif
+
+	imx51_add_nand(&nand_info);
+
+	spi_register_board_info(mx51_tx51_spi_board_info,
+		ARRAY_SIZE(mx51_tx51_spi_board_info));
+	imx51_add_spi0(&tx51_spi_0_data);
+
+	imx51_iim_register_fec_ethaddr();
+	tx51_fec_init();
+	imx51_add_fec(&fec_info);
+
+	tx51_leds_init();
+
+	//Linux Parameters
+	armlinux_set_bootparams((void *)MX51_CSD0_BASE_ADDR + 0x100);
+	armlinux_set_architecture(MACH_TYPE_TX51);
+
+	return 0;
+}
+device_initcall(tx51_devices_init);
+
+static int tx51_part_init(void)
+{
+	devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
+	dev_add_bb_dev("self_raw", "self0");
+	devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw");
+	dev_add_bb_dev("env_raw", "env0");
+
+	return 0;
+}
+late_initcall(tx51_part_init);
+
+static int tx51_console_init(void)
+{
+	imx51_init_lowlevel(800);
+	mxc_iomux_v3_setup_multiple_pads(tx51_pads, ARRAY_SIZE(tx51_pads));
+	imx51_add_uart0();
+
+	return 0;
+}
+console_initcall(tx51_console_init);
diff --git a/arch/arm/boards/karo-tx51/tx51.dox b/arch/arm/boards/karo-tx51/tx51.dox
new file mode 100644
index 0000000000..08268e0576
--- /dev/null
+++ b/arch/arm/boards/karo-tx51/tx51.dox
@@ -0,0 +1,50 @@
+/**
+@page tx51 KARO's TX51 CPU module
+
+@section tx51_cpu_card The CPU module
+
+http://www.karo-electronics.de/
+
+This CPU card is based on a Freescale i.MX51 CPU. The card is shipped with:
+
+- 128 MiB synchronous dynamic RAM (DDR2 type), 200 MHz support
+- 128 MiB NAND K9F1G08U0A (3.3V type)
+- DS1339 RTC
+- LAN8700 Phy
+
+@section tx51_baseboards Supported baseboards
+
+Supported baseboards are:
+- KARO's Starterkit 5 (currently only SD1, FEC implemented but non-working)
+
+@section tx28_stk5_howto How to get barebox for 'KARO's Starterkit 5'
+
+Using the default configuration:
+
+@verbatim
+make ARCH=arm tx51tk5_defconfig
+@endverbatim
+
+Build the binary image:
+
+@verbatim
+make ARCH=arm CROSS_COMPILE=arm-linux-gnueabi-
+@endverbatim
+
+@note replace the arm-linux-gnueabi with your ARM v7 cross compiler.
+
+@note To use the result, you also need the following resources from Freescale:
+- the 'bootlets' archive
+- the 'elftosb2' encryption tool
+- in the case you want to start @b barebox from an attached SD card the
+  'sdimage' tool from Freescale's 'uuc' archive.
+
+@section tx28_mlayout Memory layout when barebox is running:
+
+- 0x90000000 start of SDRAM
+- 0x90000100 start of kernel's boot parameters
+  - below malloc area: stack area
+  - below barebox: malloc area
+- 0x97f00000 start of @b barebox
+
+*/
diff --git a/arch/arm/boards/mini2440/env/config b/arch/arm/boards/mini2440/env/config
index ac8c32a385..77cc34f575 100644
--- a/arch/arm/boards/mini2440/env/config
+++ b/arch/arm/boards/mini2440/env/config
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-machine=mini2440
+hostname=mini2440
 eth0.serverip=
 user=
 
@@ -21,16 +21,16 @@ rootfs_loc=net
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
-rootfsimage=root-${machine}.${rootfs_type}
+rootfsimage=root-${hostname}.${rootfs_type}
 
-kernelimage=zImage-${machine}
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-$machine.lzo
+kernelimage=zImage-${hostname}
+#kernelimage=uImage-$hostname
+#kernelimage=Image-$hostname
+#kernelimage=Image-$hostname.lzo
 
 if [ -n $user ]; then
 	kernelimage="${user}"-"${kernelimage}"
-	nfsroot="${eth0.serverip}:/home/${user}/nfsroot/${machine}"
+	nfsroot="${eth0.serverip}:/home/${user}/nfsroot/${hostname}"
 	rootfsimage="${user}"-"${rootfsimage}"
 else
 	nfsroot="${eth0.serverip}:/path/to/nfs/root"
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index 97e56db2e6..361a3e294f 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -297,8 +297,8 @@ static int mini2440_devices_init(void)
 	reg |= 0x10000;
 	writel(reg, S3C_MISCCR);
 
-	add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
-			   IORESOURCE_MEM, &nand_info);
+	add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL, S3C24X0_NAND_BASE,
+			0, IORESOURCE_MEM, &nand_info);
 
 	add_dm9000_device(0, S3C_CS4_BASE + 0x300, S3C_CS4_BASE + 0x304,
 			  IORESOURCE_MEM_16BIT, &dm9000_data);
@@ -344,8 +344,8 @@ static int mini2440_console_init(void)
 	s3c_gpio_mode(GPH2_TXD0);
 	s3c_gpio_mode(GPH3_RXD0);
 
-	add_generic_device("s3c_serial", -1, NULL, S3C_UART1_BASE, S3C_UART1_SIZE,
-			   IORESOURCE_MEM, NULL);
+	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
+			S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
 	return 0;
 }
 
diff --git a/arch/arm/boards/mioa701/board.c b/arch/arm/boards/mioa701/board.c
index 6a67a03edb..14c81104ff 100644
--- a/arch/arm/boards/mioa701/board.c
+++ b/arch/arm/boards/mioa701/board.c
@@ -123,8 +123,8 @@ static int mioa701_devices_init(void)
 	pxa_add_fb((void *)0x44000000, &mioa701_pxafb_info);
 	pxa_add_mmc((void *)0x41100000, -1, &mioa701_mmc_info);
 	docg3_iospace = map_io_sections(0x0, (void *)0xe0000000, 0x2000);
-	add_generic_device("docg3", -1, NULL, (ulong) docg3_iospace, 0x2000,
-			   IORESOURCE_MEM, NULL);
+	add_generic_device("docg3", DEVICE_ID_DYNAMIC, NULL, (ulong) docg3_iospace,
+			0x2000, IORESOURCE_MEM, NULL);
 	armlinux_set_bootparams((void *)0xa0000100);
 	armlinux_set_architecture(MACH_TYPE_MIOA701);
 
diff --git a/arch/arm/boards/netx/netx.c b/arch/arm/boards/netx/netx.c
index 92d2911e68..7873d32fbf 100644
--- a/arch/arm/boards/netx/netx.c
+++ b/arch/arm/boards/netx/netx.c
@@ -49,8 +49,10 @@ mem_initcall(netx_mem_init);
 static int netx_devices_init(void) {
 	add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
 
-	add_generic_device("netx-eth", -1, NULL, 0, 0, IORESOURCE_MEM, &eth0_data);
-	add_generic_device("netx-eth", -1, NULL, 0, 0, IORESOURCE_MEM, &eth1_data);
+	add_generic_device("netx-eth", DEVICE_ID_DYNAMIC, NULL, 0, 0, IORESOURCE_MEM,
+			&eth0_data);
+	add_generic_device("netx-eth", DEVICE_ID_DYNAMIC, NULL, 0, 0, IORESOURCE_MEM,
+			&eth1_data);
 
 	devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
 
@@ -75,7 +77,7 @@ static int netx_console_init(void)
 	*(volatile unsigned long *)(0x00100808) = 2;
 	*(volatile unsigned long *)(0x0010080c) = 2;
 
-	add_generic_device("netx_serial", -1, NULL, NETX_PA_UART0, 0x40,
+	add_generic_device("netx_serial", DEVICE_ID_DYNAMIC, NULL, NETX_PA_UART0, 0x40,
 			   IORESOURCE_MEM, NULL);
 	return 0;
 }
diff --git a/arch/arm/boards/nhk8815/setup.c b/arch/arm/boards/nhk8815/setup.c
index 42d981cbfd..ae76124c7f 100644
--- a/arch/arm/boards/nhk8815/setup.c
+++ b/arch/arm/boards/nhk8815/setup.c
@@ -69,7 +69,7 @@ static struct resource nhk8815_nand_resources[] = {
 };
 
 static struct device_d nhk8815_nand_device = {
-	.id		= -1,
+	.id		= DEVICE_ID_DYNAMIC,
 	.name		= "nomadik_nand",
 	.num_resources	= ARRAY_SIZE(nhk8815_nand_resources),
 	.resource	= nhk8815_nand_resources,
@@ -95,7 +95,7 @@ static int nhk8815_devices_init(void)
 	writel(0x0000305b, FSMC_BCR(1));
 	writel(0x00033f33, FSMC_BTR(1));
 
-	add_generic_device("smc91c111", -1, NULL, 0x34000300, 16,
+	add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, 0x34000300, 16,
 			   IORESOURCE_MEM, NULL);
 
 	register_device(&nhk8815_nand_device);
diff --git a/arch/arm/boards/omap3evm/board.c b/arch/arm/boards/omap3evm/board.c
index 310814693e..6747ee4034 100644
--- a/arch/arm/boards/omap3evm/board.c
+++ b/arch/arm/boards/omap3evm/board.c
@@ -230,7 +230,7 @@ static struct NS16550_plat serial_plat = {
  */
 static int omap3evm_init_console(void)
 {
-	add_ns16550_device(-1,
+	add_ns16550_device(DEVICE_ID_DYNAMIC,
 #if defined(CONFIG_OMAP3EVM_UART1)
 			OMAP_UART1_BASE,
 #elif defined(CONFIG_OMAP3EVM_UART3)
@@ -260,7 +260,7 @@ static int omap3evm_init_devices(void)
 	gpmc_generic_init(0x10);
 #endif
 #ifdef CONFIG_MCI_OMAP_HSMMC
-	add_generic_device("omap-hsmmc", -1, NULL, OMAP_MMC1_BASE, SZ_4K,
+	add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, OMAP_MMC1_BASE, SZ_4K,
 				IORESOURCE_MEM, NULL);
 #endif
         armlinux_set_bootparams((void *)0x80000100);
diff --git a/arch/arm/boards/panda/board.c b/arch/arm/boards/panda/board.c
index be3ad77826..628d3f1e4e 100644
--- a/arch/arm/boards/panda/board.c
+++ b/arch/arm/boards/panda/board.c
@@ -38,8 +38,8 @@ static struct NS16550_plat serial_plat = {
 static int panda_console_init(void)
 {
 	/* Register the serial port */
-	add_ns16550_device(-1, OMAP44XX_UART3_BASE, 1024, IORESOURCE_MEM_8BIT,
-			   &serial_plat);
+	add_ns16550_device(DEVICE_ID_DYNAMIC, OMAP44XX_UART3_BASE, 1024,
+			IORESOURCE_MEM_8BIT, &serial_plat);
 
 	return 0;
 }
@@ -133,7 +133,7 @@ static int panda_devices_init(void)
 		sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
 	}
 
-	add_generic_device("omap-hsmmc", -1, NULL, 0x4809C100, SZ_4K,
+	add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, 0x4809C100, SZ_4K,
 			   IORESOURCE_MEM, NULL);
 	panda_ehci_init();
 
diff --git a/arch/arm/boards/panda/env/config b/arch/arm/boards/panda/env/config
index 29672be9e6..29a63f333b 100644
--- a/arch/arm/boards/panda/env/config
+++ b/arch/arm/boards/panda/env/config
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-machine=panda
+hostname=panda
 user=
 
 # use 'dhcp' to do dhcp in barebox and in kernel
@@ -18,14 +18,14 @@ kernel_loc=tftp
 # can be either 'net', 'nor', 'nand' or 'initrd'
 rootfs_loc=net
 
-kernelimage=zImage-$machine
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-${machine}.lzo
+kernelimage=zImage-$hostname
+#kernelimage=uImage-$hostname
+#kernelimage=Image-$hostname
+#kernelimage=Image-${hostname}.lzo
 
 if [ -n $user ]; then
 	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname"
 	rootfsimage="$user"-"$rootfsimage"
 else
 	nfsroot="$eth0.serverip:/path/to/nfs/root"
diff --git a/arch/arm/boards/pcm027/Makefile b/arch/arm/boards/pcm027/Makefile
new file mode 100644
index 0000000000..e3830e4f19
--- /dev/null
+++ b/arch/arm/boards/pcm027/Makefile
@@ -0,0 +1,2 @@
+obj-y += board.o
+obj-y += lowlevel_init.o
diff --git a/arch/arm/boards/pcm027/board.c b/arch/arm/boards/pcm027/board.c
new file mode 100644
index 0000000000..ab55c345c8
--- /dev/null
+++ b/arch/arm/boards/pcm027/board.c
@@ -0,0 +1,190 @@
+/*
+ * (C) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *     2010 by Marc Kleine-Budde <kernel@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <environment.h>
+#include <fs.h>
+#include <init.h>
+#include <partition.h>
+#include <sizes.h>
+
+#include <plat/gpio.h>
+#include <mach/mfp-pxa27x.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxafb.h>
+#include <mach/devices.h>
+
+#include <asm/armlinux.h>
+#include <asm/io.h>
+#include <generated/mach-types.h>
+#include <asm/mmu.h>
+
+#define PCM990_CTRL_PHYS	(void *)PXA_CS1_PHYS
+
+#define PCM990_CTRL_REG3	0x0006	/* LCD CTRL REGISTER 3 */
+#define PCM990_CTRL_LCDPWR	0x0001	/* RW LCD Power on */
+#define PCM990_CTRL_LCDON	0x0002	/* RW LCD Latch on */
+#define PCM990_CTRL_LCDPOS1	0x0004	/* RW POS 1 */
+#define PCM990_CTRL_LCDPOS2	0x0008	/* RW POS 2 */
+
+static void lcd_power(int on)
+{
+	void __iomem *ctrl3 = PCM990_CTRL_PHYS + PCM990_CTRL_REG3;
+
+	if (on)
+		writeb(PCM990_CTRL_LCDPWR | PCM990_CTRL_LCDON, ctrl3);
+	else
+		writeb(0x0, ctrl3);
+}
+
+static void backlight_power(int on)
+{
+	if (on) {
+		mdelay(20);
+		gpio_set_value(16, 1);
+	} else {
+		gpio_set_value(16, 0);
+	}
+}
+
+static struct pxafb_videomode pxafb_mode = {
+	.mode = {
+		.pixclock	= 28000,
+		.xres		= 640,
+		.yres		= 480,
+		.hsync_len	= 20,
+		.left_margin	= 103,
+		.right_margin	= 47,
+		.vsync_len	= 6,
+		.upper_margin	= 28,
+		.lower_margin	= 5,
+		.sync		= 0,
+	},
+	.bpp			= 16,
+};
+
+static struct pxafb_platform_data fb_pdata = {
+	.mode			= &pxafb_mode,
+	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
+	.lcd_power		= lcd_power,
+	.backlight_power	= backlight_power,
+};
+
+static int pcm027_mem_init(void)
+{
+	arm_add_mem_device("ram0", 0xa0000000, SZ_64M);
+
+	return 0;
+}
+mem_initcall(pcm027_mem_init);
+
+static unsigned long pin_config[] = {
+	/* Chip Selects */
+	GPIO20_nSDCS_2,
+	GPIO21_nSDCS_3,
+	GPIO15_nCS_1,
+	GPIO78_nCS_2,
+	GPIO80_nCS_4,
+
+	/* Variable Latency I/O Ready Pin */
+	GPIO18_RDY,
+
+	/* FFUART */
+	GPIO85_nPCE_1,		/* enables RX */
+	GPIO34_FFUART_RXD,
+	GPIO35_FFUART_CTS,
+	GPIO36_FFUART_DCD,
+	GPIO37_FFUART_DSR,
+	GPIO38_FFUART_RI,
+	GPIO39_FFUART_TXD,
+	GPIO40_FFUART_DTR,
+	GPIO41_FFUART_RTS,
+
+	/* LCD */
+	GPIO58_LCD_LDD_0,
+	GPIO59_LCD_LDD_1,
+	GPIO60_LCD_LDD_2,
+	GPIO61_LCD_LDD_3,
+	GPIO62_LCD_LDD_4,
+	GPIO63_LCD_LDD_5,
+	GPIO64_LCD_LDD_6,
+	GPIO65_LCD_LDD_7,
+	GPIO66_LCD_LDD_8,
+	GPIO67_LCD_LDD_9,
+	GPIO68_LCD_LDD_10,
+	GPIO69_LCD_LDD_11,
+	GPIO70_LCD_LDD_12,
+	GPIO71_LCD_LDD_13,
+	GPIO72_LCD_LDD_14,
+	GPIO73_LCD_LDD_15,
+	GPIO74_LCD_FCLK,
+	GPIO75_LCD_LCLK,
+	GPIO76_LCD_PCLK,
+	GPIO77_LCD_BIAS,
+	MFP_CFG_OUT(GPIO16, AF0, DRIVE_LOW),	/* backlight */
+
+	/* NIC */
+	GPIO33_nCS_5,
+	GPIO49_nPWE,
+};
+
+static int pcm027_devices_init(void)
+{
+	void *cfi_iospace;
+
+	add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, 0x14000300, 16,
+			IORESOURCE_MEM, NULL);
+
+	cfi_iospace = map_io_sections(0x0, (void *)0xe0000000, SZ_32M);
+	add_cfi_flash_device(DEVICE_ID_DYNAMIC, (unsigned long)cfi_iospace, SZ_32M, 0);
+
+	pxa_add_fb((void *)0x44000000, &fb_pdata);
+
+	armlinux_set_bootparams((void *)0xa0000100);
+	armlinux_set_architecture(MACH_TYPE_PCM027);
+
+	devfs_add_partition("nor0", 0x00000, SZ_512K, PARTITION_FIXED, "self0");
+	devfs_add_partition("nor0", SZ_512K, SZ_256K, PARTITION_FIXED, "env0");
+	protect_file("/dev/env0", 1);
+
+	return 0;
+}
+
+device_initcall(pcm027_devices_init);
+
+static int pcm027_console_init(void)
+{
+	/* route pins */
+	pxa2xx_mfp_config(ARRAY_AND_SIZE(pin_config));
+
+	/* enable clock */
+	CKEN |= CKEN_FFUART;
+
+	pxa_add_uart((void *)0x40100000, 0);
+
+	return 0;
+}
+
+console_initcall(pcm027_console_init);
diff --git a/arch/arm/boards/pcm027/config.h b/arch/arm/boards/pcm027/config.h
new file mode 100644
index 0000000000..555a2be009
--- /dev/null
+++ b/arch/arm/boards/pcm027/config.h
@@ -0,0 +1,328 @@
+/*
+ * Copyright (C) 2005 Phytec Messtechnik GmbH
+ * Juergen Kilb, H. Klaholz <armlinux@phytec.de>
+ *
+ * Copyright (C) 2006 Pengutronix
+ * Sascha Hauer <s.hauer@pengutronix.de>
+ * Robert Schwebel <r.schwebel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * phyCORE-PXA270 configuration settings
+ * Set these to 0/1 to enable or disable the features.
+ */
+
+#define PHYCORE_PXA270_USE_K3FLASH	0
+
+/* 260 MHz or 520 MHZ */
+#define PHYCORE_PXA270_SPEED		520
+
+/*********************************************************************
+ * CONFIG PXA270 GPIO settings                                       *
+ *********************************************************************/
+
+/*
+ * GPIO set "1"
+ *
+ *** REG GPSR0
+ * GP15 == nCS1      is 1
+ * GP20 == nSDCS2    is 1
+ * GP21 == nSDCS3    is 1
+ *** REG GPSR1
+ * GP33 == nCS5      is 1
+ *** REG GPSR2
+ * GP78 == nCS2      is 1
+ * GP80 == nCS4      is 1
+ */
+#define GPSR0_DFT		0x00308000
+#define GPSR1_DFT		0x00000002
+#define GPSR2_DFT		0x00014000
+
+#define CONFIG_GPSR0_VAL	GPSR0_DFT
+#define CONFIG_GPSR1_VAL	GPSR1_DFT
+#define CONFIG_GPSR2_VAL	GPSR2_DFT
+#define CONFIG_GPSR3_VAL	GPSR3_DFT
+
+/*
+ * set Direction "1" GPIO == output else input
+ *
+ ** REG GPDR0
+ * GP03 == PWR_SDA   is output
+ * GP04 == PWR_SCL   is output
+ * GP15 == nCS1      is output
+ * GP20 == nSDCS2    is output
+ * GP21 == nSDCS3    is output
+ ** REG GPDR1
+ * GP33 == nCS5      is output
+ ** REG GPDR2
+ * GP78 == nCS2      is output
+ * GP80 == nCS4      is output
+ * GP90 == LED0      is output
+ * GP91 == LED1      is output
+ */
+
+#define GPDR0_DFT		0x00308018
+#define GPDR1_DFT		0x00000002
+#define GPDR2_DFT		0x00014000
+
+#define CONFIG_GPDR0_VAL	GPDR0_DFT
+#define CONFIG_GPDR1_VAL	GPDR1_DFT
+#define CONFIG_GPDR2_VAL	GPDR2_DFT
+
+/*
+ * set Alternate Funktions
+ *
+ ** REG GAFR0_L
+ * GP15 == nCS1      is AF10
+ ** REG GAFR0_U
+ * GP18 == RDY       is AF01
+ * GP20 == nSDCS2    is AF01
+ * GP21 == nSDCS3    is AF01
+ ** REG GAFR1_L
+ * GP33 == nCS5      is AF10
+ ** REG GAFR2_L
+ * GP78 == nCS2      is AF10
+ ** REG GAFR2_U
+ * GP80 == nCS4      is AF10
+ */
+
+#define GAFR0_L_DFT		0x80000000
+#define GAFR0_U_DFT		0x00000510
+#define GAFR1_L_DFT		0x00000008
+#define GAFR1_U_DFT		0x00000000
+#define GAFR2_L_DFT		0x20000000
+#define GAFR2_U_DFT		0x00000002
+
+#define CONFIG_GAFR0_L_VAL	GAFR0_L_DFT
+#define CONFIG_GAFR0_U_VAL	GAFR0_U_DFT
+#define CONFIG_GAFR1_L_VAL	GAFR1_L_DFT
+#define CONFIG_GAFR1_U_VAL	GAFR1_U_DFT
+#define CONFIG_GAFR2_L_VAL	GAFR2_L_DFT
+#define CONFIG_GAFR2_U_VAL	GAFR2_U_DFT
+
+
+/*
+ * Power Manager Sleep Status Register (PSSR)
+ *
+ * [6] = 0   OTG pad is not holding it's state
+ * [5] = 1   Read Disable Hold: receivers of all gpio pins are disabled
+ * [4] = 1   gpio pins are held in their sleep mode state
+ * [3] = 0   The processor has not been placed in standby mode by
+ *           configuring the PWRMODE register since STS was cleared
+ *           by a reset or by software.
+ * [2] = 1   nVDD_FAULT has been asserted and caused the processor to
+ *           enter deep-sleep mode.
+ * [1] = 1   nBATT_FAULT has been asserted and caused the processor to
+ *           enter deep-sleep mode.
+ * [0] = 1   The processor was placed in sleep mode by configuring the
+ *           PWRMODE register.
+ */
+
+#define CONFIG_PSSR_VAL		0x37
+
+
+/*********************************************************************
+ * CONFIG PXA270 Chipselect settings                                 *
+ *********************************************************************/
+
+/*
+ * Memory settings
+ *
+ * This is the configuration for nCS1/0 -> PLD / flash
+ * configuration for nCS1:
+ * [31]    0    - Slower Device
+ * [30:28] 001  - CS deselect to CS time: 1*(2*MemClk) = 20 ns
+ * [27:24] 0010 - Address to data valid in bursts: (2+1)*MemClk = 30 ns
+ * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
+ * [19]    1    - 16 Bit bus width
+ * [18:16] 011  - burst RAM or FLASH
+ * configuration for nCS0 (J3 Flash):
+ * [15]    0    - Slower Device
+ * [14:12] 001  - CS deselect to CS time: 1*(2*MemClk) = 20 ns
+ * [11:08] 0010 - Address to data valid in bursts: (2+1)*MemClk = 30 ns
+ * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
+ * [03]    0    - 32 Bit bus width
+ * [02:00] 011  - burst RAM or FLASH
+ */
+#if PHYCORE_PXA270_USE_K3FLASH == 0
+#define CONFIG_MSC0_VAL		0x128C1262
+#else
+/* configuration for nCS0 (K3 Flash):
+ * [15]    0    - Slower Device
+ * [14:12] 001  - CS deselect to CS time: 1*(2*MemClk) = 20 ns
+ * [11:08] 0010 - Address to data valid in bursts: (2+1)*MemClk = 30 ns
+ * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
+ * [03]    0    - 32 Bit bus width
+ * [02:00] 011  - burst RAM or FLASH
+ */
+#define CONFIG_MSC0_VAL		0x128C12B3
+#endif
+
+/*
+ * This is the configuration for nCS3/2
+ * configuration for nCS3: POWER
+ *
+ * [31]    0    - Slower Device
+ * [30:28] 111  - RRR3: CS deselect to CS time: 7*(2*MemClk) = 140 ns
+ * [27:24] 1111 - RDN3: Address to data valid in bursts: (15+1)*MemClk = 160 ns
+ * [23:20] 1111 - RDF3: Address for first access: (23+1)*MemClk = 240 ns
+ * [19]    0    - 32 Bit bus width
+ * [18:16] 100  - variable latency I/O
+ * configuration for nCS2: PLD
+ * [15]    0    - Slower Device
+ * [14:12] 111  - RRR2: CS deselect to CS time: 7*(2*MemClk) = 140 ns
+ * [11:08] 1111 - RDN2: Address to data valid in bursts: (15+1)*MemClk = 160 ns
+ * [07:04] 1111 - RDF2: Address for first access: (23+1)*MemClk = 240 ns
+ * [03]    1    - 16 Bit bus width
+ * [02:00] 100  - variable latency I/O
+ */
+#define CONFIG_MSC1_VAL		0x128c128c
+
+/*
+ * This is the configuration for nCS5/4
+ *
+ * configuration for nCS5: LAN Controller
+ * [31]    0    - Slower Device
+ * [30:28] 001  - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
+ * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
+ * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
+ * [19]    0    - 32 Bit bus width
+ * [18:16] 100  - variable latency I/O
+ * configuration for nCS4: USB
+ * [15]    0    - Slower Device
+ * [14:12] 111  - RRR4: CS deselect to CS time: 7*(2*MemClk) = 140 ns
+ * [11:08] 1111 - RDN4: Address to data valid in bursts: (15+1)*MemClk = 160 ns
+ * [07:04] 1111 - RDF4: Address for first access: (23+1)*MemClk = 240 ns
+ * [03]    1    - 16 Bit bus width
+ * [02:00] 100  - variable latency I/O
+ */
+#define CONFIG_MSC2_VAL		0x1234128C
+
+/*********************************************************************
+ * CONFIG PXA270 SDRAM settings                                      *
+ *********************************************************************/
+
+#define CONFIG_DRAM_BASE	0xa0000000
+
+
+/* MDCNFG: SDRAM Configuration Register
+ *
+ * [31]      0	 - Stack1
+ * [30]      0   - dcacx2
+ * [20]      0   - reserved
+ * [31:29]   000 - reserved
+ * [28]      1	 - SA1111 compatiblity mode
+ * [27]      1   - latch return data with return clock
+ * [26]      0   - alternate addressing for pair 2/3
+ * [25:24]   10  - timings
+ * [23]      1   - internal banks in lower partition 2/3 (not used)
+ * [22:21]   10  - row address bits for partition 2/3 (not used)
+ * [20:19]   01  - column address bits for partition 2/3 (not used)
+ * [18]      0   - SDRAM partition 2/3 width is 32 bit
+ * [17]      0   - SDRAM partition 3 disabled
+ * [16]      0   - SDRAM partition 2 disabled
+ * [15]      0	 - Stack1
+ * [14]      0   - dcacx0
+ * [13]      0   - Stack0
+ * [12]      0	 - SA1110 compatiblity mode
+ * [11]      1   - always 1
+ * [10]      0   - no alternate addressing for pair 0/1
+ * [09:08]   10  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
+ * [7]       1   - 4 internal banks in lower partition pair
+ * [06:05]   10  - 13 row address bits for partition 0/1
+ * [04:03]   01  - 9 column address bits for partition 0/1
+ * [02]      0   - SDRAM partition 0/1 width is 32 bit
+ * [01]      0   - disable SDRAM partition 1
+ * [00]      1   - enable  SDRAM partition 0
+ */
+
+/* K4S561633*/
+#define CONFIG_MDCNFG_VAL	0x0AC90AC9
+
+/* MDREFR: SDRAM Refresh Control Register
+ *
+ * [31]    0     - ALTREFA
+ * [30]    0     - ALTREFB
+ * [29]    1     - K0DB4
+ * [28]    0     - reserved
+ * [27]    0     - reserved
+ * [26]    0     - reserved
+ * [25]    1     - K2FREE: not free running
+ * [24]    0     - K1FREE: not free running
+ * [23]    1     - K0FREE: not free running
+ * [22]    0     - SLFRSH: self refresh disabled
+ * [21]    0     - reserved
+ * [20]    0     - APD: no auto power down
+ * [19]    0     - K2DB2: SDCLK2 is MemClk
+ * [18]    0     - K2RUN: disable SDCLK2
+ * [17]    0     - K1DB2: SDCLK1 is MemClk
+ * [16]    1     - K1RUN: enable SDCLK1
+ * [15]    1     - E1PIN: SDRAM clock enable
+ * [14]    1     - K0DB2: SDCLK0 is MemClk
+ * [13]    0     - K0RUN: disable SDCLK0
+ * [12]    0     - RESERVED
+ * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
+ */
+#define CONFIG_MDREFR_VAL	0x2281C018
+
+/* MDMRS: Mode Register Set Configuration Register
+ *
+ * [31]      0       - reserved
+ * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
+ * [22:20]   000     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
+ * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
+ * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
+ * [15]      0       - reserved
+ * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
+ * [06:04]   010     - MDCL0:  SDRAM0/1 Cas Latency.
+ * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
+ * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
+ */
+#define CONFIG_MDMRS_VAL	0x00020022
+
+/*********************************************************************
+ * CONFIG PXA270 Clock generation                                    *
+ *********************************************************************/
+#define CONFIG_FLYCNFG_VAL	0x00010001
+#define CONFIG_SXCNFG_VAL	0x40044004
+#define CONFIG_CKEN		(CKEN_MEMC |  CKEN_OSTIMER)
+
+#if PHYCORE_PXA270_SPEED == 520
+#define CONFIG_CCCR		0x00000290	/* Memory Clock is f. Table;         N=2.5, L=16 => 16x13=208, 208x2,5=520 MHz */
+#elif PHYCORE_PXA270_SPEED == 260
+#define CONFIG_CCCR		0x02000288	/* Memory Clock is System-Bus Freq., N=2.5, L=8  =>  8x13=104, 104x2,5=260 MHz */
+#else
+#error You have specified an illegal speed.
+#endif
+
+/*********************************************************************
+ * CONFIG PXA270 CF interface                                        *
+ *********************************************************************/
+#define CONFIG_MECR_VAL		0x00000003
+#define CONFIG_MCMEM0_VAL	0x00010504
+#define CONFIG_MCMEM1_VAL	0x00010504
+#define CONFIG_MCATT0_VAL	0x00010504
+#define CONFIG_MCATT1_VAL	0x00010504
+#define CONFIG_MCIO0_VAL	0x00004715
+#define CONFIG_MCIO1_VAL	0x00004715
+
+#endif  /* __CONFIG_H */
diff --git a/arch/arm/boards/pcm027/env/config b/arch/arm/boards/pcm027/env/config
new file mode 100644
index 0000000000..3ed963c67b
--- /dev/null
+++ b/arch/arm/boards/pcm027/env/config
@@ -0,0 +1,46 @@
+#!/bin/sh
+
+hostname=pcm027
+eth0.serverip=
+user=
+
+# use 'dhcp' to do dhcp in barebox and in kernel
+# use 'none' if you want to skip kernel ip autoconfiguration
+ip=dhcp
+
+# or set your networking parameters here
+#eth0.ipaddr=a.b.c.d
+#eth0.netmask=a.b.c.d
+#eth0.gateway=a.b.c.d
+#eth0.serverip=a.b.c.d
+
+# can be either 'nfs', 'tftp', 'nor' or 'nand'
+kernel_loc=tftp
+# can be either 'net', 'nor', 'nand' or 'initrd'
+rootfs_loc=net
+
+# can be either 'jffs2' or 'ubifs'
+rootfs_type=ubifs
+rootfsimage=root-$hostname.$rootfs_type
+
+kernelimage=zImage-$hostname
+#kernelimage=uImage-$hostname
+#kernelimage=Image-$hostname
+#kernelimage=Image-$hostname.lzo
+
+if [ -n $user ]; then
+	kernelimage="$user"-"$kernelimage"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname"
+	rootfsimage="$user"-"$rootfsimage"
+else
+	nfsroot="$eth0.serverip:/path/to/nfs/root"
+fi
+
+autoboot_timeout=3
+
+bootargs="console=ttyS0,115200"
+
+nor_parts="512k(barebox)ro,256k(bareboxenv),4M(kernel),-(root)"
+rootfs_mtdblock_nor=3
+
+PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
diff --git a/arch/arm/boards/pcm027/lowlevel_init.S b/arch/arm/boards/pcm027/lowlevel_init.S
new file mode 100644
index 0000000000..a436a330cb
--- /dev/null
+++ b/arch/arm/boards/pcm027/lowlevel_init.S
@@ -0,0 +1,456 @@
+/*
+ * This was originally from the Lubbock u-boot port.
+ *
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <mach/pxa-regs.h>
+#include <mach/regs-ost.h>
+#include <mach/regs-intc.h>
+
+#define GPSR0		0x40E00018	/* GPIO Pin Output Set Register GPIO <31:00> */
+#define GPSR1		0x40E0001C	/* GPIO Pin Output Set Register GPIO <63:32> */
+#define GPSR2		0x40E00020	/* GPIO Pin Output Set Register GPIO <80:64> */
+
+#define GPCR0		0x40E00024	/* GPIO Pin Output Clear Register GPIO <31:00> */
+#define GPCR1		0x40E00028	/* GPIO Pin Output Clear Register GPIO <63:32> */
+#define GPCR2		0x40E0002C	/* GPIO Pin Output Clear Register GPIO <80:64> */
+
+#define GPDR0		0x40E0000C	/* GPIO Pin Direction Register GPIO <31:0o> */
+#define GPDR1		0x40E00010	/* GPIO Pin Direction Register GPIO <63:32> */
+#define GPDR2		0x40E00014	/* GPIO Pin Direction Register GPIO <80:64> */
+
+#define GAFR0_L		0x40E00054	/* GPIO Alternate Function Select Register GPIO <15:00> */
+#define GAFR0_U		0x40E00058	/* GPIO Alternate Function Select Register GPIO <31:16> */
+#define GAFR1_L		0x40E0005C	/* GPIO Alternate Function Select Register GPIO <47:32> */
+#define GAFR1_U		0x40E00060	/* GPIO Alternate Function Select Register GPIO <63:48> */
+#define GAFR2_L		0x40E00064	/* GPIO Alternate Function Select Register GPIO <79:64> */
+#define GAFR2_U		0x40E00068	/* GPIO Alternate Function Select Register GPIO <95:80> */
+
+/*
+ *	Memory setup
+ */
+.globl board_init_lowlevel
+board_init_lowlevel:
+		@ Preserve r8/r7 i.e. kernel entry values
+
+		@ Data cache might be active.
+		@ Be sure to flush kernel binary out of the cache,
+		@ whatever state it is, before it is turned off.
+		@ This is done by fetching through currently executed
+		@ memory to be sure we hit the same cache.
+		bic	r2, pc, #0x1f
+		add	r3, r2, #0x10000	@ 64 kb is quite enough...
+1:		ldr	r0, [r2], #32
+		teq	r2, r3
+		bne	1b
+		mcr	p15, 0, r0, c7, c10, 4	@ drain WB
+		mcr	p15, 0, r0, c7, c7, 0	@ flush I & D caches
+
+		@ disabling MMU and caches
+		mrc	p15, 0, r0, c1, c0, 0	@ read control reg
+		bic	r0, r0, #0x05		@ clear DC, MMU
+		bic	r0, r0, #0x1000		@ clear Icache
+		mcr	p15, 0, r0, c1, c0, 0
+	/* set output */
+	ldr	r0, =GPSR0
+	ldr	r1, =CONFIG_GPSR0_VAL
+	str	r1, [r0]
+
+	ldr	r0, =GPSR1
+	ldr	r1, =CONFIG_GPSR1_VAL
+	str	r1, [r0]
+
+	ldr	r0, =GPSR2
+	ldr	r1, =CONFIG_GPSR2_VAL
+	str	r1, [r0]
+
+	/* set direction */
+	ldr	r0, =GPDR0
+	ldr	r1, =CONFIG_GPDR0_VAL
+	str	r1, [r0]
+
+	ldr	r0, =GPDR1
+	ldr	r1, =CONFIG_GPDR1_VAL
+	str	r1, [r0]
+
+	ldr	r0, =GPDR2
+	ldr	r1, =CONFIG_GPDR2_VAL
+	str	r1, [r0]
+
+	/* alternate function */
+	ldr	r0, =GAFR0_L
+	ldr	r1, =CONFIG_GAFR0_L_VAL
+	str	r1, [r0]
+
+	ldr	r0, =GAFR0_U
+	ldr	r1, =CONFIG_GAFR0_U_VAL
+	str	r1, [r0]
+
+	ldr	r0, =GAFR1_L
+	ldr	r1, =CONFIG_GAFR1_L_VAL
+	str	r1, [r0]
+
+	ldr	r0, =GAFR1_U
+	ldr	r1, =CONFIG_GAFR1_U_VAL
+	str	r1, [r0]
+
+	ldr	r0, =GAFR2_L
+	ldr	r1, =CONFIG_GAFR2_L_VAL
+	str	r1, [r0]
+
+	ldr	r0, =GAFR2_U
+	ldr	r1, =CONFIG_GAFR2_U_VAL
+	str	r1, [r0]
+
+	/* enable GPIO pins */
+	ldr	r0, =PSSR
+	ldr	r1, =CONFIG_PSSR_VAL
+	str	r1, [r0]
+
+	/* -------------------------------------------------------------------- */
+	/* Enable memory interface						*/
+	/*									*/
+	/* The sequence below is based on the recommended init steps		*/
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide,	*/
+	/* Chapter 10.								*/
+	/* -------------------------------------------------------------------- */
+
+	/* -------------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal		*/
+	/*	   clocks to settle. Only necessary after hard reset...		*/
+	/*	   FIXME: can be optimized later				*/
+	/* -------------------------------------------------------------------- */
+
+	ldr	r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov	r2, #0
+	str	r2, [r3]
+	ldr	r4, =0x300			/* really 0x2E1 is about 200usec, */
+						/* so 0x300 should be plenty */
+1:
+	ldr	r2, [r3]
+	cmp	r4, r2
+	bgt	1b
+
+	cmp	pc, #0xa0000000
+	bls	mem_init
+	cmp	pc, #0xb0000000
+	bhi	mem_init
+	b	skip_mem_init
+
+mem_init:
+	ldr	r1, =MDCNFG			/* get memory controller base addr. */
+
+	/* -------------------------------------------------------------------- */
+	/* Step 2a: Initialize Asynchronous static memory controller		*/
+	/* -------------------------------------------------------------------- */
+
+	/* MSC registers: timing, bus width, mem type */
+
+	/* MSC0: nCS(0,1) */
+	ldr	r2, =CONFIG_MSC0_VAL
+	str	r2, [r1, #MSC0_OFFSET]
+	ldr	r2, [r1, #MSC0_OFFSET]		/* read back to ensure */
+						/* that data latches */
+	/* MSC1: nCS(2,3) */
+	ldr	r2, =CONFIG_MSC1_VAL
+	str	r2, [r1, #MSC1_OFFSET]
+	ldr	r2, [r1, #MSC1_OFFSET]
+
+	/* MSC2: nCS(4,5) */
+	ldr	r2, =CONFIG_MSC2_VAL
+	str	r2, [r1, #MSC2_OFFSET]
+	ldr	r2, [r1, #MSC2_OFFSET]
+
+	/* -------------------------------------------------------------------- */
+	/* Step 2b: Initialize Card Interface					*/
+	/* -------------------------------------------------------------------- */
+
+	/* MECR: Memory Expansion Card Register	*/
+	ldr	r2, =CONFIG_MECR_VAL
+	str	r2, [r1, #MECR_OFFSET]
+	ldr	r2, [r1, #MECR_OFFSET]
+
+	/* MCMEM0: Card Interface slot 0 timing	*/
+	ldr	r2, =CONFIG_MCMEM0_VAL
+	str	r2, [r1, #MCMEM0_OFFSET]
+	ldr	r2, [r1, #MCMEM0_OFFSET]
+
+	/* MCMEM1: Card Interface slot 1 timing	*/
+	ldr	r2, =CONFIG_MCMEM1_VAL
+	str	r2, [r1, #MCMEM1_OFFSET]
+	ldr	r2, [r1, #MCMEM1_OFFSET]
+
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+	ldr	r2, =CONFIG_MCATT0_VAL
+	str	r2, [r1, #MCATT0_OFFSET]
+	ldr	r2, [r1, #MCATT0_OFFSET]
+
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+	ldr	r2, =CONFIG_MCATT1_VAL
+	str	r2, [r1, #MCATT1_OFFSET]
+	ldr	r2, [r1, #MCATT1_OFFSET]
+
+	/* MCIO0: Card Interface I/O Space Timing, slot 0 */
+	ldr	r2, =CONFIG_MCIO0_VAL
+	str	r2, [r1, #MCIO0_OFFSET]
+	ldr	r2, [r1, #MCIO0_OFFSET]
+
+	/* MCIO1: Card Interface I/O Space Timing, slot 1 */
+	ldr	r2, =CONFIG_MCIO1_VAL
+	str	r2, [r1, #MCIO1_OFFSET]
+	ldr	r2, [r1, #MCIO1_OFFSET]
+
+	/* -------------------------------------------------------------------- */
+	/* Step 2c: Write FLYCNFG FIXME: what's that???				*/
+	/* -------------------------------------------------------------------- */
+	ldr	r2, =CONFIG_FLYCNFG_VAL
+	str	r2, [r1, #FLYCNFG_OFFSET]
+	str	r2, [r1, #FLYCNFG_OFFSET]
+
+	/* -------------------------------------------------------------------- */
+	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)			*/
+	/* -------------------------------------------------------------------- */
+
+	/* Before accessing MDREFR we need a valid DRI field, so we set	*/
+	/* this to power on defaults + DRI field. */
+
+	ldr	r4, [r1, #MDREFR_OFFSET]
+	ldr	r2, =0xFFF
+	bic	r4, r4, r2
+
+	ldr	r3, =CONFIG_MDREFR_VAL
+	and	r3, r3, r2
+
+	orr	r4, r4, r3
+	str	r4, [r1, #MDREFR_OFFSET]	/* write back MDREFR */
+
+	orr	r4, r4, #MDREFR_K0RUN
+	orr	r4, r4, #MDREFR_K0DB4
+	orr	r4, r4, #MDREFR_K0FREE
+	orr	r4, r4, #MDREFR_K2FREE
+	orr	r4, r4, #MDREFR_K0DB2
+	orr	r4, r4, #MDREFR_K1DB2
+	bic	r4, r4, #MDREFR_K1FREE
+
+	str	r4, [r1, #MDREFR_OFFSET]	/* write back MDREFR */
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	/* Note: preserve the mdrefr value in r4 */
+
+
+	/* -------------------------------------------------------------------- */
+	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals)	*/
+	/* -------------------------------------------------------------------- */
+
+	/* Initialize SXCNFG register. Assert the enable bits */
+
+	/*
+	 * Write SXMRS to cause an MRS command to all enabled banks of
+	 * synchronous static memory. Note that SXLCR need not be
+	 * written at this time.
+	 */
+	ldr	r2, =CONFIG_SXCNFG_VAL
+	str	r2, [r1, #SXCNFG_OFFSET]
+
+	/* -------------------------------------------------------------------- */
+	/* Step 4: Initialize SDRAM						*/
+	/* -------------------------------------------------------------------- */
+	bic	r4, r4, #(MDREFR_K1FREE | MDREFR_K0FREE)
+
+	orr	r4, r4, #MDREFR_K1RUN
+	orr	r4, r4, #MDREFR_K2FREE
+	bic	r4, r4, #MDREFR_K2DB2
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	bic	r4, r4, #MDREFR_SLFRSH
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	orr	r4, r4, #MDREFR_E1PIN
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	nop
+	nop
+
+
+	/*
+	 * Step 4d: write MDCNFG with MDCNFG:DEx deasserted
+	 * (set to 0), to configure but not enable each SDRAM
+	 * partition pair.
+	 */
+	ldr	r4, =CONFIG_MDCNFG_VAL
+	bic	r4, r4,	#(MDCNFG_DE0|MDCNFG_DE1)
+	bic	r4, r4,	#(MDCNFG_DE2|MDCNFG_DE3)
+
+	str	r4, [r1, #MDCNFG_OFFSET]	/* write back MDCNFG */
+	ldr	r4, [r1, #MDCNFG_OFFSET]
+
+
+	/*
+	 * Step 4e: Wait for the clock to the SDRAMs to stabilize,
+	 * 100..200 usec.
+	 */
+	ldr	r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov	r2, #0
+	str	r2, [r3]
+	ldr	r4, =0x300			/* really 0x2E1 is about 200 usec,  */
+						/* so 0x300 should be plenty */
+1:
+	ldr	r2, [r3]
+	cmp	r4, r2
+	bgt	1b
+
+
+	/* Step 4f: Trigger a number (usually 8) refresh cycles by		*/
+	/*		attempting non-burst read or write accesses to disabled */
+	/*		SDRAM, as commonly specified in the power up sequence   */
+	/*		documented in SDRAM data sheets. The address(es) used   */
+	/*		for this purpose must not be cacheable.			*/
+	ldr	r3, =CONFIG_DRAM_BASE
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+
+
+	/*
+	 * Step 4g: Write MDCNFG with enable bits asserted
+	 * (MDCNFG:DEx set to 1)
+	 */
+	ldr	r3, [r1, #MDCNFG_OFFSET]
+	mov	r4, r3
+	orr	r3, r3,	#MDCNFG_DE0
+	str	r3, [r1, #MDCNFG_OFFSET]
+	mov	r0, r3
+
+	/* Step 4h: Write MDMRS. */
+	ldr	r2, =CONFIG_MDMRS_VAL
+	str	r2, [r1, #MDMRS_OFFSET]
+
+	/* enable APD */
+	ldr	r3, [r1, #MDREFR_OFFSET]
+	orr	r3, r3, #MDREFR_APD
+	str	r3, [r1, #MDREFR_OFFSET]
+
+	/* We are finished with Intel's memory controller initialisation */
+skip_mem_init:
+
+wakeup:
+	/* Are we waking from sleep? */
+	ldr	r0, =RCSR
+	ldr	r1, [r0]
+	and	r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
+	str	r1, [r0]
+	teq	r1, #RCSR_SMR
+
+	bne	initirqs
+
+	ldr	r0, =PSSR
+	mov	r1, #PSSR_PH
+	str	r1, [r0]
+
+	/* if so, resume at PSPR */
+	ldr	r0, =PSPR
+	ldr	r1, [r0]
+	mov	pc, r1
+
+	/* -------------------------------------------------------------------- */
+	/* Disable (mask) all interrupts at interrupt controller		*/
+	/* -------------------------------------------------------------------- */
+
+initirqs:
+	mov	r1, #0		/* clear int. level register (IRQ, not FIQ) */
+	ldr	r2, =ICLR
+	str	r1, [r2]
+
+	ldr	r2, =ICMR	/* mask all interrupts at the controller */
+	str	r1, [r2]
+
+	/* -------------------------------------------------------------------- */
+	/* Clock initialisation							*/
+	/* -------------------------------------------------------------------- */
+
+initclks:
+	/* Disable the peripheral clocks, and set the core clock frequency */
+
+	/* Turn Off on-chip peripheral clocks (except for memory) */
+	/* for re-configuration. */
+	ldr	r1, =CKEN
+	ldr	r2, =CONFIG_CKEN
+	str	r2, [r1]
+
+	/* ... and write the core clock config register */
+	ldr	r2, =CONFIG_CCCR
+	ldr	r1, =CCCR
+	str	r2, [r1]
+
+	/* Turn on turbo mode */
+	mrc	p14, 0, r2, c6, c0, 0
+	orr	r2, r2, #0xB			/* Turbo, Fast-Bus, Freq change */
+	mcr	p14, 0, r2, c6, c0, 0
+
+	/* Re-write MDREFR */
+	ldr	r1, =MDCNFG
+	ldr	r2, [r1, #MDREFR_OFFSET]
+	str	r2, [r1, #MDREFR_OFFSET]
+
+	/* enable the 32Khz oscillator for RTC and PowerManager */
+	ldr	r1, =OSCC
+	mov	r2, #OSCC_OON
+	str	r2, [r1]
+
+	/* Interrupt init: Mask all interrupts */
+	ldr	r0, =ICMR			/* enable no sources */
+	mov	r1, #0
+	str	r1, [r0]
+	/* FIXME */
+
+#ifdef NODEBUG
+	/* Disable software and data breakpoints */
+	mov	r0, #0
+	mcr	p15, 0, r0, c14, c8, 0		/* ibcr0 */
+	mcr	p15, 0, r0, c14, c9, 0		/* ibcr1 */
+	mcr	p15, 0, r0, c14, c4, 0		/* dbcon */
+
+	/* Enable all debug functionality */
+	mov	r0, #0x80000000
+	mcr	p14, 0, r0, c10, c0, 0		/* dcsr */
+#endif
+
+	/* -------------------------------------------------------------------- */
+	/* End lowlevel_init							*/
+	/* -------------------------------------------------------------------- */
+
+endlowlevel_init:
+	mov	pc, lr
diff --git a/arch/arm/boards/pcm037/env/config b/arch/arm/boards/pcm037/env/config
index d67d319452..fcdb77764c 100644
--- a/arch/arm/boards/pcm037/env/config
+++ b/arch/arm/boards/pcm037/env/config
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-machine=pcm037
+hostname=pcm037
 eth0.serverip=
 user=
 
@@ -21,16 +21,16 @@ rootfs_loc=net
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
-rootfsimage=root-$machine.$rootfs_type
+rootfsimage=root-$hostname.$rootfs_type
 
-kernelimage=zImage-$machine
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-$machine.lzo
+kernelimage=zImage-$hostname
+#kernelimage=uImage-$hostname
+#kernelimage=Image-$hostname
+#kernelimage=Image-$hostname.lzo
 
 if [ -n $user ]; then
 	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname"
 	rootfsimage="$user"-"$rootfsimage"
 else
 	nfsroot="$eth0.serverip:/path/to/nfs/root"
diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c
index 46f2ce9900..660c9ab428 100644
--- a/arch/arm/boards/pcm037/pcm037.c
+++ b/arch/arm/boards/pcm037/pcm037.c
@@ -188,7 +188,7 @@ static int imx31_devices_init(void)
 	 * Up to 32MiB NOR type flash, connected to
 	 * CS line 0, data width is 16 bit
 	 */
-	add_cfi_flash_device(-1, IMX_CS0_BASE, 32 * 1024 * 1024, 0);
+	add_cfi_flash_device(DEVICE_ID_DYNAMIC, IMX_CS0_BASE, 32 * 1024 * 1024, 0);
 
 	/*
 	 * Create partitions that should be
@@ -212,13 +212,13 @@ static int imx31_devices_init(void)
 	 * connected to CS line 1 and interrupt line
 	 * GPIO3, data width is 16 bit
 	 */
-	add_generic_device("smc911x", -1, NULL,	IMX_CS1_BASE, IMX_CS1_RANGE,
-			IORESOURCE_MEM, NULL);
+	add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL,	IMX_CS1_BASE,
+			IMX_CS1_RANGE, IORESOURCE_MEM, NULL);
 
 #ifdef CONFIG_USB
 	pcm037_usb_init();
-	add_generic_usb_ehci_device(-1, IMX_OTG_BASE, NULL);
-	add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
+	add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE, NULL);
+	add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL);
 #endif
 
 	armlinux_set_bootparams((void *)0x80000100);
diff --git a/arch/arm/boards/pcm038/env/config b/arch/arm/boards/pcm038/env/config
index b1a5f42eff..32be5ec419 100644
--- a/arch/arm/boards/pcm038/env/config
+++ b/arch/arm/boards/pcm038/env/config
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-machine=pcm038
+hostname=pcm038
 eth0.serverip=
 user=
 
@@ -21,16 +21,16 @@ rootfs_loc=net
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
-rootfsimage=root-$machine.$rootfs_type
+rootfsimage=root-$hostname.$rootfs_type
 
-kernelimage=zImage-$machine
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-$machine.lzo
+kernelimage=zImage-$hostname
+#kernelimage=uImage-$hostname
+#kernelimage=Image-$hostname
+#kernelimage=Image-$hostname.lzo
 
 if [ -n $user ]; then
 	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname"
 	rootfsimage="$user"-"$rootfsimage"
 else
 	nfsroot="$eth0.serverip:/path/to/nfs/root"
diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c
index 01129bb291..d481bdc576 100644
--- a/arch/arm/boards/pcm038/pcm038.c
+++ b/arch/arm/boards/pcm038/pcm038.c
@@ -28,7 +28,6 @@
 #include <mach/gpio.h>
 #include <asm/armlinux.h>
 #include <generated/mach-types.h>
-#include <mach/pmic.h>
 #include <partition.h>
 #include <fs.h>
 #include <fcntl.h>
@@ -45,6 +44,7 @@
 #include <mach/spi.h>
 #include <mach/iomux-mx27.h>
 #include <mach/devices-imx27.h>
+#include <mfd/mc13xxx.h>
 
 #include "pll.h"
 
@@ -62,7 +62,7 @@ static struct spi_imx_master pcm038_spi_0_data = {
 
 static struct spi_board_info pcm038_spi_board_info[] = {
 	{
-		.name = "mc13783",
+		.name = "mc13xxx-spi",
 		.max_speed_hz = 3000000,
 		.bus_num = 0,
 		.chip_select = 0,
@@ -306,6 +306,35 @@ static int pcm038_console_init(void)
 
 console_initcall(pcm038_console_init);
 
+#ifdef CONFIG_MFD_MC13XXX
+static int pmic_power(void)
+{
+	struct mc13xxx *mc13xxx;
+
+	mc13xxx = mc13xxx_get();
+	if (!mc13xxx)
+		return -ENODEV;
+
+	mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(0),
+		MC13783_SWX_VOLTAGE(MC13783_SWX_VOLTAGE_1_450) |
+		MC13783_SWX_VOLTAGE_DVS(MC13783_SWX_VOLTAGE_1_450) |
+		MC13783_SWX_VOLTAGE_STANDBY(MC13783_SWX_VOLTAGE_1_450));
+
+	mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(4),
+		MC13783_SW1A_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) |
+		MC13783_SW1A_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) |
+		MC13783_SW1A_SOFTSTART |
+		MC13783_SW1B_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) |
+		MC13783_SW1B_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) |
+		MC13783_SW1B_SOFTSTART |
+		MC13783_SW_PLL_FACTOR(32));
+
+	return 0;
+}
+#else
+# define pmic_power()	(1)
+#endif
+
 /**
  * The spctl0 register is a beast: Seems you can read it
  * only one times without writing it again.
@@ -326,15 +355,13 @@ static inline uint32_t get_pll_spctl10(void)
 static int pcm038_power_init(void)
 {
 	uint32_t spctl0;
-	int ret;
 
 	spctl0 = get_pll_spctl10();
 
 	/* PLL registers already set to their final values? */
 	if (spctl0 == SPCTL0_VAL && MPCTL0 == MPCTL0_VAL) {
 		console_flush();
-		ret = pmic_power();
-		if (ret == 0) {
+		if (!pmic_power()) {
 			/* wait for required power level to run the CPU at 400 MHz */
 			udelay(100000);
 			CSCR = CSCR_VAL_FINAL;
diff --git a/arch/arm/boards/pcm043/env/config b/arch/arm/boards/pcm043/env/config
index 2a355e6704..644c7fb839 100644
--- a/arch/arm/boards/pcm043/env/config
+++ b/arch/arm/boards/pcm043/env/config
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-machine=pcm043
+hostname=pcm043
 eth0.serverip=
 user=
 
@@ -21,16 +21,16 @@ rootfs_loc=net
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
-rootfsimage=root-$machine.$rootfs_type
+rootfsimage=root-$hostname.$rootfs_type
 
-kernelimage=zImage-$machine
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-$machine.lzo
+kernelimage=zImage-$hostname
+#kernelimage=uImage-$hostname
+#kernelimage=Image-$hostname
+#kernelimage=Image-$hostname.lzo
 
 if [ -n $user ]; then
 	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname"
 	rootfsimage="$user"-"$rootfsimage"
 else
 	nfsroot="$eth0.serverip:/path/to/nfs/root"
diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c
index e0dd5fc0d4..6da5dd45fb 100644
--- a/arch/arm/boards/pcm043/pcm043.c
+++ b/arch/arm/boards/pcm043/pcm043.c
@@ -178,7 +178,7 @@ static int imx35_devices_init(void)
 
 device_initcall(imx35_devices_init);
 
-static struct pad_desc pcm043_pads[] = {
+static iomux_v3_cfg_t pcm043_pads[] = {
 	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
 	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
 	MX35_PAD_FEC_RX_DV__FEC_RX_DV,
diff --git a/arch/arm/boards/pcm049/board.c b/arch/arm/boards/pcm049/board.c
index 0c82261d5e..e4043edca1 100644
--- a/arch/arm/boards/pcm049/board.c
+++ b/arch/arm/boards/pcm049/board.c
@@ -50,7 +50,8 @@ static struct NS16550_plat serial_plat = {
 static int pcm049_console_init(void)
 {
 	/* Register the serial port */
-	add_ns16550_device(-1, OMAP44XX_UART3_BASE, 1024, IORESOURCE_MEM_8BIT, &serial_plat);
+	add_ns16550_device(DEVICE_ID_DYNAMIC, OMAP44XX_UART3_BASE, 1024,
+			IORESOURCE_MEM_8BIT, &serial_plat);
 
 	return 0;
 }
@@ -83,7 +84,7 @@ static void pcm049_network_init(void)
 {
 	gpmc_cs_config(5, &net_cfg);
 
-	add_generic_device("smc911x", -1, NULL, 0x2C000000, 0x4000,
+	add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, 0x2C000000, 0x4000,
 			   IORESOURCE_MEM, NULL);
 }
 
@@ -96,10 +97,10 @@ static struct i2c_board_info i2c_devices[] = {
 static int pcm049_devices_init(void)
 {
 	i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
-	add_generic_device("i2c-omap", -1, NULL, 0x48070000, 0x1000,
+	add_generic_device("i2c-omap", DEVICE_ID_DYNAMIC, NULL, 0x48070000, 0x1000,
 				IORESOURCE_MEM, NULL);
 
-	add_generic_device("omap-hsmmc", -1, NULL, 0x4809C100, SZ_4K,
+	add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, 0x4809C100, SZ_4K,
 			   IORESOURCE_MEM, NULL);
 
 	gpmc_generic_init(0x10);
diff --git a/arch/arm/boards/pcm049/env/config b/arch/arm/boards/pcm049/env/config
index f3487141e3..efbe9ea038 100644
--- a/arch/arm/boards/pcm049/env/config
+++ b/arch/arm/boards/pcm049/env/config
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-machine=pcm049
+hostname=pcm049
 eth0.serverip=
 user=
 
@@ -21,16 +21,16 @@ rootfs_loc=net
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
-rootfsimage=root-${machine}.$rootfs_type
+rootfsimage=root-${hostname}.$rootfs_type
 
-kernelimage=zImage-$machine
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-${machine}.lzo
+kernelimage=zImage-$hostname
+#kernelimage=uImage-$hostname
+#kernelimage=Image-$hostname
+#kernelimage=Image-${hostname}.lzo
 
 if [ -n $user ]; then
 	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname"
 	rootfsimage="$user"-"$rootfsimage"
 else
 	nfsroot="$eth0.serverip:/path/to/nfs/root"
diff --git a/arch/arm/boards/phycard-a-l1/env/config b/arch/arm/boards/phycard-a-l1/env/config
index 4a648b92fb..e0f4dcc2af 100644
--- a/arch/arm/boards/phycard-a-l1/env/config
+++ b/arch/arm/boards/phycard-a-l1/env/config
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-machine=pcaal1
+hostname=pcaal1
 #user=
 
 # Enter MAC address here if not retrieved automatically
@@ -26,26 +26,26 @@ rootfs_loc=nand
 rootfs_type=jffs2
 # where is the rootfs in case of 'rootfs_loc=disk' (linux name)
 rootfs_part_linux_dev=mmcblk0p4
-rootfsimage=rootfs-${machine}.$rootfs_type
+rootfsimage=rootfs-${hostname}.$rootfs_type
 
 # where is the kernel image in case of 'kernel_loc=disk'
 kernel_part=disk0.2
 
 # The image type of the kernel. Can be uimage, zimage, raw or raw_lzo
-#kernelimage=zImage-$machine
-kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-$machine.lzo
+#kernelimage=zImage-$hostname
+kernelimage=uImage-$hostname
+#kernelimage=Image-$hostname
+#kernelimage=Image-$hostname.lzo
 
-bareboximage=barebox-${machine}.bin
-bareboxenvimage=barebox-${machine}.bin
+bareboximage=barebox-${hostname}.bin
+bareboxenvimage=barebox-${hostname}.bin
 
 if [ -n $user ]; then
 	bareboximage="$user"-"$bareboximage"
 	bareboxenvimage="$user"-"$bareboxenvimage"
 	kernelimage="$user"-"$kernelimage"
 	rootfsimage="$user"-"$rootfsimage"
-	nfsroot="/home/$user/nfsroot/$machine"
+	nfsroot="/home/$user/nfsroot/$hostname"
 else
 	nfsroot="/path/to/nfs/root"
 fi
diff --git a/arch/arm/boards/phycard-a-l1/pca-a-l1.c b/arch/arm/boards/phycard-a-l1/pca-a-l1.c
index 3fc3542506..c8e93641c4 100644
--- a/arch/arm/boards/phycard-a-l1/pca-a-l1.c
+++ b/arch/arm/boards/phycard-a-l1/pca-a-l1.c
@@ -311,13 +311,13 @@ struct omap_hsmmc_platform_data pcaal1_hsmmc_plat = {
 static int pcaal1_init_devices(void)
 {
 #ifdef CONFIG_MCI_OMAP_HSMMC
-	add_generic_device("omap-hsmmc", -1, NULL, OMAP_MMC1_BASE, SZ_4K,
+	add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, OMAP_MMC1_BASE, SZ_4K,
 			   IORESOURCE_MEM, &pcaal1_hsmmc_plat);
 #endif
 
 #ifdef CONFIG_DRIVER_NET_SMC911X
 	pcaal1_setup_net_chip();
-	add_generic_device("smc911x", -1, NULL, SMC911X_BASE, SZ_4K,
+	add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, SMC911X_BASE, SZ_4K,
 			   IORESOURCE_MEM, NULL);
 #endif
 
diff --git a/arch/arm/boards/phycard-a-xl2/env/config b/arch/arm/boards/phycard-a-xl2/env/config
index 0cbfb16b3e..59e8eb3851 100644
--- a/arch/arm/boards/phycard-a-xl2/env/config
+++ b/arch/arm/boards/phycard-a-xl2/env/config
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-machine=pcaaxl2
+hostname=pcaaxl2
 user=
 
 # use 'dhcp' to do dhcp in barebox and in kernel
@@ -20,16 +20,16 @@ rootfs_loc=net
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
-rootfsimage=root-${machine}.$rootfs_type
+rootfsimage=root-${hostname}.$rootfs_type
 
-kernelimage=zImage-$machine
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-${machine}.lzo
+kernelimage=zImage-$hostname
+#kernelimage=uImage-$hostname
+#kernelimage=Image-$hostname
+#kernelimage=Image-${hostname}.lzo
 
 if [ -n $user ]; then
 	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname"
 	rootfsimage="$user"-"$rootfsimage"
 else
 	nfsroot="$eth0.serverip:/path/to/nfs/root"
diff --git a/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c b/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c
index 72fc18f4ca..7358fe0606 100644
--- a/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c
+++ b/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c
@@ -109,7 +109,7 @@ static int pcaaxl2_devices_init(void)
 	u32 value;
 
 	i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
-	add_generic_device("i2c-omap", -1, NULL, 0x48070000, 0x1000,
+	add_generic_device("i2c-omap", DEVICE_ID_DYNAMIC, NULL, 0x48070000, 0x1000,
 				IORESOURCE_MEM, NULL);
 
 	value = readl(OMAP4_CONTROL_PBIASLITE);
@@ -117,7 +117,7 @@ static int pcaaxl2_devices_init(void)
 	value |= (OMAP4_MMC1_PBIASLITE_PWRDNZ |	OMAP4_MMC1_PWRDNZ);
 	writel(value, OMAP4_CONTROL_PBIASLITE);
 
-	add_generic_device("omap-hsmmc", -1, NULL, 0x4809C100, SZ_4K,
+	add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, 0x4809C100, SZ_4K,
 			   IORESOURCE_MEM, &mmc_device);
 
 	gpmc_generic_init(0x10);
diff --git a/arch/arm/boards/phycard-i.MX27/env/config b/arch/arm/boards/phycard-i.MX27/env/config
index 5db33d0c64..367029bee5 100644
--- a/arch/arm/boards/phycard-i.MX27/env/config
+++ b/arch/arm/boards/phycard-i.MX27/env/config
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-machine=pca100
+hostname=pca100
 eth0.serverip=
 user=
 
@@ -21,16 +21,16 @@ rootfs_loc=net
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
-rootfsimage=root-$machine.$rootfs_type
+rootfsimage=root-$hostname.$rootfs_type
 
-kernelimage=zImage-$machine
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-$machine.lzo
+kernelimage=zImage-$hostname
+#kernelimage=uImage-$hostname
+#kernelimage=Image-$hostname
+#kernelimage=Image-$hostname.lzo
 
 if [ -n $user ]; then
 	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname"
 	rootfsimage="$user"-"$rootfsimage"
 else
 	nfsroot="$eth0.serverip:/path/to/nfs/root"
diff --git a/arch/arm/boards/scb9328/env/config b/arch/arm/boards/scb9328/env/config
index e1c5807bad..a8eace7b24 100644
--- a/arch/arm/boards/scb9328/env/config
+++ b/arch/arm/boards/scb9328/env/config
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-machine=scb9328
+hostname=scb9328
 eth0.serverip=
 user=
 
@@ -21,16 +21,16 @@ rootfs_loc=net
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
-rootfsimage=root-$machine.$rootfs_type
+rootfsimage=root-$hostname.$rootfs_type
 
-kernelimage=zImage-$machine
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-$machine.lzo
+kernelimage=zImage-$hostname
+#kernelimage=uImage-$hostname
+#kernelimage=Image-$hostname
+#kernelimage=Image-$hostname.lzo
 
 if [ -n $user ]; then
 	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname"
 	rootfsimage="$user"-"$rootfsimage"
 else
 	nfsroot="$eth0.serverip:/path/to/nfs/root"
diff --git a/arch/arm/boards/tny-a926x/env/config b/arch/arm/boards/tny-a926x/env/config
index b5215dc46e..514fc9f142 100644
--- a/arch/arm/boards/tny-a926x/env/config
+++ b/arch/arm/boards/tny-a926x/env/config
@@ -3,6 +3,9 @@
 # use 'dhcp' to do dhcp in barebox and in kernel
 # use 'none' if you want to skip kernel ip autoconfiguration
 ip=dhcp-barebox
+[ x$armlinux_architecture = x2058 ] && dhcp_vendor_id=barebox-tny-a9260
+[ x$armlinux_architecture = x2059 ] && dhcp_vendor_id=barebox-tny-a9g20
+[ x$armlinux_architecture = x2140 ] && dhcp_vendor_id=barebox-tny-a9263
 
 # or set your networking parameters here
 #eth0.ipaddr=a.b.c.d
@@ -14,19 +17,21 @@ ip=dhcp-barebox
 kernel_loc=nand
 # can be either 'net', 'nor', 'nand' or 'initrd'
 rootfs_loc=nand
+# can be either 'nfs', 'tftp', 'nor', 'nand' or empty
+oftree_loc=nand
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
 rootfsimage=root.$rootfs_type
 
-#kernelimage=zImage
-kernelimage=uImage
+kernelimage=zImage
+#kernelimage=uImage
 #kernelimage=Image
 #kernelimage=Image.lzo
 
 nand_device=atmel_nand
-nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),4M(kernel),120M(rootfs),-(data)"
-rootfs_mtdblock_nand=5
+nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),4M(kernel),120M(rootfs),-(data)"
+rootfs_mtdblock_nand=6
 
 autoboot_timeout=3
 
diff --git a/arch/arm/boards/tqma53/board.c b/arch/arm/boards/tqma53/board.c
index 184c00f16a..947c3f107a 100644
--- a/arch/arm/boards/tqma53/board.c
+++ b/arch/arm/boards/tqma53/board.c
@@ -43,7 +43,7 @@ static struct fec_platform_data fec_info = {
 	.xcv_type = RMII,
 };
 
-static struct pad_desc tqma53_pads[] = {
+static iomux_v3_cfg_t tqma53_pads[] = {
 	MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
 	MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
 	MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
diff --git a/arch/arm/boards/tqma53/env/config b/arch/arm/boards/tqma53/env/config
index 97b009c700..723b0940f7 100644
--- a/arch/arm/boards/tqma53/env/config
+++ b/arch/arm/boards/tqma53/env/config
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-machine=tqma53
+hostname=tqma53
 serverip=
 user=
 
@@ -21,13 +21,13 @@ rootfs_loc=net
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
-rootfsimage=root-$machine.$rootfs_type
+rootfsimage=root-$hostname.$rootfs_type
 
-kernelimage=zImage-$machine
+kernelimage=zImage-$hostname
 
 if [ -n $user ]; then
 	kernelimage="$user"-"$kernelimage"
-	nfsroot="$serverip:/home/$user/nfsroot/$machine"
+	nfsroot="$serverip:/home/$user/nfsroot/$hostname"
 	rootfsimage="$user"-"$rootfsimage"
 else
 	nfsroot="$serverip:/path/to/nfs/root"
diff --git a/arch/arm/boards/usb-a926x/env/config b/arch/arm/boards/usb-a926x/env/config
index 1f7280382c..dc0a264056 100644
--- a/arch/arm/boards/usb-a926x/env/config
+++ b/arch/arm/boards/usb-a926x/env/config
@@ -3,7 +3,9 @@
 # use 'dhcp' to do dhcp in barebox and in kernel
 # use 'none' if you want to skip kernel ip autoconfiguration
 ip=dhcp-barebox
-dhcp_vendor_id=barebox-at91sam9x5ek
+[ x$armlinux_architecture = x1709 ] && dhcp_vendor_id=barebox-usb-a9260
+[ x$armlinux_architecture = x1710 ] && dhcp_vendor_id=barebox-usb-a9263
+[ x$armlinux_architecture = x1841 ] && dhcp_vendor_id=barebox-usb-a9g20
 
 # or set your networking parameters here
 #eth0.ipaddr=a.b.c.d
@@ -12,22 +14,24 @@ dhcp_vendor_id=barebox-at91sam9x5ek
 #eth0.serverip=a.b.c.d
 
 # can be either 'nfs', 'tftp', 'nor' or 'nand'
-kernel_loc=tftp
+kernel_loc=nfs
 # can be either 'net', 'nor', 'nand' or 'initrd'
 rootfs_loc=net
+# can be either 'nfs', 'tftp', 'nor', 'nand' or empty
+oftree_loc=nfs
 
 # can be either 'jffs2' or 'ubifs'
 rootfs_type=ubifs
 rootfsimage=root.$rootfs_type
 
-#kernelimage=zImage
-kernelimage=uImage
+kernelimage=zImage
+#kernelimage=uImage
 #kernelimage=Image
 #kernelimage=Image.lzo
 
 nand_device=atmel_nand
-nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),4M(kernel),120M(rootfs),-(data)"
-rootfs_mtdblock_nand=5
+nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),4M(kernel),120M(rootfs),-(data)"
+rootfs_mtdblock_nand=6
 
 autoboot_timeout=3
 
diff --git a/arch/arm/boards/versatile/versatilepb.c b/arch/arm/boards/versatile/versatilepb.c
index 4e09de3c34..436f42177c 100644
--- a/arch/arm/boards/versatile/versatilepb.c
+++ b/arch/arm/boards/versatile/versatilepb.c
@@ -54,8 +54,8 @@ static int vpb_devices_init(void)
 	devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");
 	devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
 
-	add_generic_device("smc91c111", -1, NULL, VERSATILE_ETH_BASE, 64 * 1024,
-			   IORESOURCE_MEM, NULL);
+	add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, VERSATILE_ETH_BASE,
+			64 * 1024, IORESOURCE_MEM, NULL);
 
 	armlinux_set_architecture(MACH_TYPE_VERSATILE_PB);
 	armlinux_set_bootparams((void *)(0x00000100));
diff --git a/arch/arm/configs/at91sam9260ek_defconfig b/arch/arm/configs/at91sam9260ek_defconfig
index c288d396fd..ec8ab226a6 100644
--- a/arch/arm/configs/at91sam9260ek_defconfig
+++ b/arch/arm/configs/at91sam9260ek_defconfig
@@ -51,6 +51,7 @@ CONFIG_NET_NETCONSOLE=y
 CONFIG_DRIVER_NET_MACB=y
 # CONFIG_SPI is not set
 CONFIG_MTD=y
+# CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
 # CONFIG_NAND_ECC_HW is not set
 # CONFIG_NAND_ECC_HW_SYNDROME is not set
@@ -69,4 +70,3 @@ CONFIG_LED_TRIGGERS=y
 CONFIG_FS_FAT=y
 CONFIG_FS_FAT_WRITE=y
 CONFIG_FS_FAT_LFN=y
-CONFIG_ZLIB=y
diff --git a/arch/arm/configs/at91sam9263ek_defconfig b/arch/arm/configs/at91sam9263ek_defconfig
index f59eab979c..ec9c1b668c 100644
--- a/arch/arm/configs/at91sam9263ek_defconfig
+++ b/arch/arm/configs/at91sam9263ek_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARCH_AT91SAM9263=y
+# CONFIG_CMD_ARM_CPUINFO is not set
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_MMU=y
 CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
@@ -29,6 +30,7 @@ CONFIG_CMD_BOOTM_INITRD=y
 CONFIG_CMD_BOOTM_OFTREE=y
 CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
 CONFIG_CMD_UIMAGE=y
+# CONFIG_CMD_BOOTZ is not set
 # CONFIG_CMD_BOOTU is not set
 CONFIG_CMD_RESET=y
 CONFIG_CMD_GO=y
@@ -47,6 +49,7 @@ CONFIG_DRIVER_NET_MACB=y
 # CONFIG_SPI is not set
 CONFIG_DRIVER_CFI=y
 # CONFIG_DRIVER_CFI_INTEL is not set
+# CONFIG_DRIVER_CFI_BANK_WIDTH_4 is not set
 CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
diff --git a/arch/arm/configs/at91sam9g20ek_defconfig b/arch/arm/configs/at91sam9g20ek_defconfig
index 9473488fc2..49876c0ca7 100644
--- a/arch/arm/configs/at91sam9g20ek_defconfig
+++ b/arch/arm/configs/at91sam9g20ek_defconfig
@@ -52,6 +52,7 @@ CONFIG_NET_NETCONSOLE=y
 CONFIG_DRIVER_NET_MACB=y
 # CONFIG_SPI is not set
 CONFIG_MTD=y
+# CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
 # CONFIG_NAND_ECC_HW is not set
 # CONFIG_NAND_ECC_HW_SYNDROME is not set
@@ -70,4 +71,3 @@ CONFIG_LED_TRIGGERS=y
 CONFIG_FS_FAT=y
 CONFIG_FS_FAT_WRITE=y
 CONFIG_FS_FAT_LFN=y
-CONFIG_ZLIB=y
diff --git a/arch/arm/configs/freescale-mx6-arm2_defconfig b/arch/arm/configs/freescale-mx6-arm2_defconfig
new file mode 100644
index 0000000000..c150cc7f03
--- /dev/null
+++ b/arch/arm/configs/freescale-mx6-arm2_defconfig
@@ -0,0 +1,69 @@
+CONFIG_ARCH_IMX=y
+CONFIG_ARCH_IMX6=y
+CONFIG_IMX_IIM=y
+CONFIG_IMX_IIM_FUSE_BLOW=y
+CONFIG_AEABI=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
+CONFIG_MMU=y
+CONFIG_MALLOC_SIZE=0x8000000
+CONFIG_MALLOC_TLSF=y
+CONFIG_KALLSYMS=y
+CONFIG_LONGHELP=y
+CONFIG_GLOB=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/freescale-mx6-arm2/env/"
+CONFIG_DEBUG_INFO=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
+CONFIG_CMD_UIMAGE=y
+# CONFIG_CMD_BOOTZ is not set
+# CONFIG_CMD_BOOTU is not set
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_NET=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_NFS=y
+CONFIG_NET_PING=y
+CONFIG_NET_TFTP=y
+CONFIG_NET_TFTP_PUSH=y
+CONFIG_NET_NETCONSOLE=y
+CONFIG_DRIVER_NET_FEC_IMX=y
+CONFIG_NET_USB=y
+CONFIG_NET_USB_ASIX=y
+CONFIG_NET_USB_SMSC95XX=y
+# CONFIG_SPI is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_IMX_ESDHC=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_ZLIB=y
+CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/freescale_mx51_babbage_defconfig b/arch/arm/configs/freescale_mx51_babbage_defconfig
index 19e49eff32..c4f7aeff78 100644
--- a/arch/arm/configs/freescale_mx51_babbage_defconfig
+++ b/arch/arm/configs/freescale_mx51_babbage_defconfig
@@ -58,7 +58,7 @@ CONFIG_CFI_BUFFER_WRITE=y
 CONFIG_MCI=y
 CONFIG_MCI_STARTUP=y
 CONFIG_MCI_IMX_ESDHC=y
-CONFIG_I2C_MC13892=y
+CONFIG_MFD_MC13XXX=y
 CONFIG_FS_FAT=y
 CONFIG_FS_FAT_WRITE=y
 CONFIG_FS_FAT_LFN=y
diff --git a/arch/arm/configs/freescale_mx53_loco_defconfig b/arch/arm/configs/freescale_mx53_loco_defconfig
index f31d5bf4c9..6cb4c174e2 100644
--- a/arch/arm/configs/freescale_mx53_loco_defconfig
+++ b/arch/arm/configs/freescale_mx53_loco_defconfig
@@ -57,6 +57,9 @@ CONFIG_DRIVER_NET_FEC_IMX=y
 # CONFIG_SPI is not set
 CONFIG_I2C=y
 CONFIG_I2C_IMX=y
+CONFIG_USB=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_STORAGE=y
 CONFIG_MCI=y
 CONFIG_MCI_STARTUP=y
 CONFIG_MCI_IMX_ESDHC=y
diff --git a/arch/arm/configs/mx21ads_defconfig b/arch/arm/configs/mx21ads_defconfig
index 175c229381..e63a386bfe 100644
--- a/arch/arm/configs/mx21ads_defconfig
+++ b/arch/arm/configs/mx21ads_defconfig
@@ -2,8 +2,8 @@ CONFIG_ARCH_IMX=y
 CONFIG_ARCH_IMX21=y
 CONFIG_IMX_CLKO=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_TEXT_BASE=0xc1000000
-CONFIG_MALLOC_SIZE=0x500000
+CONFIG_TEXT_BASE=0xc3000000
+CONFIG_MALLOC_SIZE=0x2000000
 CONFIG_LONGHELP=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
diff --git a/arch/arm/configs/mx27ads_defconfig b/arch/arm/configs/mx27ads_defconfig
index e92fb9c8f5..34fe81d66a 100644
--- a/arch/arm/configs/mx27ads_defconfig
+++ b/arch/arm/configs/mx27ads_defconfig
@@ -32,7 +32,6 @@ CONFIG_NET_DHCP=y
 CONFIG_NET_PING=y
 CONFIG_NET_TFTP=y
 CONFIG_DRIVER_SPI_IMX=y
-CONFIG_DRIVER_SPI_MC13783=y
 CONFIG_DRIVER_CFI=y
 # CONFIG_DRIVER_CFI_INTEL is not set
 CONFIG_CFI_BUFFER_WRITE=y
diff --git a/arch/arm/configs/neso_defconfig b/arch/arm/configs/neso_defconfig
index fe5110fa8f..5744dc1c71 100644
--- a/arch/arm/configs/neso_defconfig
+++ b/arch/arm/configs/neso_defconfig
@@ -72,4 +72,3 @@ CONFIG_USB_ULPI=y
 CONFIG_VIDEO=y
 CONFIG_DRIVER_VIDEO_IMX=y
 CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY=y
-CONFIG_DRIVER_SPI_MC13783=y
diff --git a/arch/arm/configs/pcm027_defconfig b/arch/arm/configs/pcm027_defconfig
new file mode 100644
index 0000000000..9760e66065
--- /dev/null
+++ b/arch/arm/configs/pcm027_defconfig
@@ -0,0 +1,61 @@
+CONFIG_ARCH_PXA=y
+CONFIG_MACH_PCM027=y
+CONFIG_AEABI=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
+CONFIG_MMU=y
+CONFIG_MALLOC_SIZE=0x1000000
+CONFIG_MALLOC_TLSF=y
+CONFIG_KALLSYMS=y
+CONFIG_LONGHELP=y
+CONFIG_GLOB=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_PARTITION=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm027/env"
+CONFIG_DEBUG_INFO=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_AUTOMOUNT=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
+CONFIG_CMD_UIMAGE=y
+# CONFIG_CMD_BOOTZ is not set
+# CONFIG_CMD_BOOTU is not set
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_NET=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_PING=y
+CONFIG_NET_TFTP=y
+CONFIG_NET_TFTP_PUSH=y
+CONFIG_DRIVER_SERIAL_PXA=y
+CONFIG_DRIVER_NET_SMC91111=y
+# CONFIG_SPI is not set
+CONFIG_DRIVER_CFI=y
+CONFIG_VIDEO=y
+CONFIG_DRIVER_VIDEO_PXA=y
+CONFIG_FS_TFTP=y
+CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/pcm038_defconfig b/arch/arm/configs/pcm038_defconfig
index 17a5e14502..4cb83e5059 100644
--- a/arch/arm/configs/pcm038_defconfig
+++ b/arch/arm/configs/pcm038_defconfig
@@ -76,3 +76,4 @@ CONFIG_DRIVER_VIDEO_IMX=y
 CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY=y
 CONFIG_ZLIB=y
 CONFIG_LZO_DECOMPRESS=y
+CONFIG_MFD_MC13XXX=y
diff --git a/arch/arm/configs/tny_a9260_defconfig b/arch/arm/configs/tny_a9260_defconfig
index 2388305db0..83293fb67c 100644
--- a/arch/arm/configs/tny_a9260_defconfig
+++ b/arch/arm/configs/tny_a9260_defconfig
@@ -4,6 +4,7 @@ CONFIG_CALAO_MOB_TNY_MD2=y
 CONFIG_AEABI=y
 # CONFIG_CMD_ARM_CPUINFO is not set
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_MMU=y
 CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MALLOC_TLSF=y
@@ -22,7 +23,6 @@ CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/tny-a926x/env"
 CONFIG_CMD_EDIT=y
 CONFIG_CMD_SLEEP=y
 CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_LOADENV=y
 CONFIG_CMD_EXPORT=y
 CONFIG_CMD_PRINTENV=y
 CONFIG_CMD_READLINE=y
@@ -59,6 +59,7 @@ CONFIG_NET_NETCONSOLE=y
 CONFIG_DRIVER_NET_MACB=y
 CONFIG_DRIVER_SPI_ATMEL=y
 CONFIG_MTD=y
+# CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
 # CONFIG_NAND_ECC_HW is not set
 # CONFIG_NAND_ECC_HW_SYNDROME is not set
@@ -68,4 +69,3 @@ CONFIG_UBI=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_SERIAL=y
 CONFIG_EEPROM_AT25=y
-CONFIG_ZLIB=y
diff --git a/arch/arm/configs/tny_a9263_defconfig b/arch/arm/configs/tny_a9263_defconfig
index d1bc418a37..dd68ba4d6d 100644
--- a/arch/arm/configs/tny_a9263_defconfig
+++ b/arch/arm/configs/tny_a9263_defconfig
@@ -4,6 +4,7 @@ CONFIG_CALAO_MOB_TNY_MD2=y
 CONFIG_AEABI=y
 # CONFIG_CMD_ARM_CPUINFO is not set
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_MMU=y
 CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MALLOC_TLSF=y
@@ -22,7 +23,6 @@ CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/tny-a926x/env"
 CONFIG_CMD_EDIT=y
 CONFIG_CMD_SLEEP=y
 CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_LOADENV=y
 CONFIG_CMD_EXPORT=y
 CONFIG_CMD_PRINTENV=y
 CONFIG_CMD_READLINE=y
@@ -59,6 +59,7 @@ CONFIG_NET_NETCONSOLE=y
 CONFIG_DRIVER_NET_MACB=y
 CONFIG_DRIVER_SPI_ATMEL=y
 CONFIG_MTD=y
+# CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
 # CONFIG_NAND_ECC_HW is not set
 # CONFIG_NAND_ECC_HW_SYNDROME is not set
@@ -68,4 +69,3 @@ CONFIG_UBI=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_SERIAL=y
 CONFIG_EEPROM_AT25=y
-CONFIG_ZLIB=y
diff --git a/arch/arm/configs/tny_a9g20_defconfig b/arch/arm/configs/tny_a9g20_defconfig
index 983c68a102..62250cb5a4 100644
--- a/arch/arm/configs/tny_a9g20_defconfig
+++ b/arch/arm/configs/tny_a9g20_defconfig
@@ -4,6 +4,7 @@ CONFIG_CALAO_MOB_TNY_MD2=y
 CONFIG_AEABI=y
 # CONFIG_CMD_ARM_CPUINFO is not set
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_MMU=y
 CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MALLOC_TLSF=y
@@ -22,7 +23,6 @@ CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/tny-a926x/env"
 CONFIG_CMD_EDIT=y
 CONFIG_CMD_SLEEP=y
 CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_LOADENV=y
 CONFIG_CMD_EXPORT=y
 CONFIG_CMD_PRINTENV=y
 CONFIG_CMD_READLINE=y
@@ -59,6 +59,7 @@ CONFIG_NET_NETCONSOLE=y
 CONFIG_DRIVER_NET_MACB=y
 CONFIG_DRIVER_SPI_ATMEL=y
 CONFIG_MTD=y
+# CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
 # CONFIG_NAND_ECC_HW is not set
 # CONFIG_NAND_ECC_HW_SYNDROME is not set
@@ -68,4 +69,3 @@ CONFIG_UBI=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_SERIAL=y
 CONFIG_EEPROM_AT25=y
-CONFIG_ZLIB=y
diff --git a/arch/arm/configs/tx51stk5_defconfig b/arch/arm/configs/tx51stk5_defconfig
new file mode 100644
index 0000000000..7fff0f0d10
--- /dev/null
+++ b/arch/arm/configs/tx51stk5_defconfig
@@ -0,0 +1,148 @@
+CONFIG_GENERIC_LINKER_SCRIPT=y
+CONFIG_ARM=y
+CONFIG_ARM_LINUX=y
+CONFIG_ARCH_IMX=y
+CONFIG_CPU_32=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_ARCH_IMX_INTERNAL_BOOT=y
+CONFIG_ARCH_IMX_INTERNAL_BOOT_NAND=y
+CONFIG_ARCH_IMX51=y
+CONFIG_MACH_TX51=y
+CONFIG_IMX_IIM=y
+CONFIG_AEABI=y
+CONFIG_CMD_ARM_CPUINFO=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_EXCEPTIONS=y
+CONFIG_ARM_UNWIND=y
+CONFIG_GREGORIAN_CALENDER=y
+CONFIG_HAS_KALLSYMS=y
+CONFIG_HAS_MODULES=y
+CONFIG_CMD_MEMORY=y
+CONFIG_ENV_HANDLING=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_BLOCK=y
+CONFIG_BLOCK_WRITE=y
+CONFIG_FILETYPE=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_BANNER=y
+CONFIG_ENVIRONMENT_VARIABLES=y
+CONFIG_MMU=y
+CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y
+CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y
+CONFIG_MEMORY_LAYOUT_DEFAULT=y
+CONFIG_MALLOC_TLSF=y
+CONFIG_KALLSYMS=y
+CONFIG_LONGHELP=y
+CONFIG_SHELL_HUSH=y
+CONFIG_GLOB=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_HUSH_GETOPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_DYNAMIC_CRC_TABLE=y
+CONFIG_ERRNO_MESSAGES=y
+CONFIG_TIMESTAMP=y
+CONFIG_CONSOLE_FULL=y
+CONFIG_CONSOLE_ACTIVATE_FIRST=y
+CONFIG_PARTITION=y
+CONFIG_PARTITION_DISK=y
+CONFIG_PARTITION_DISK_DOS=y
+CONFIG_DEFAULT_ENVIRONMENT=y
+CONFIG_DEFAULT_ENVIRONMENT_COMPRESSED=y
+CONFIG_DEFAULT_ENVIRONMENT_COMPRESSED_GZIP=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_COMMAND_SUPPORT=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TRUE=y
+CONFIG_CMD_FALSE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_LS=y
+CONFIG_CMD_RM=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_MKDIR=y
+CONFIG_CMD_RMDIR=y
+CONFIG_CMD_CP=y
+CONFIG_CMD_PWD=y
+CONFIG_CMD_CD=y
+CONFIG_CMD_MOUNT=y
+CONFIG_CMD_UMOUNT=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_CLEAR=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_MTEST=y
+CONFIG_CMD_MTEST_ALTERNATIVE=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_TEST=y
+CONFIG_CMD_VERSION=y
+CONFIG_CMD_HELP=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_DEVINFO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_LED=y
+CONFIG_NET=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_PING=y
+CONFIG_NET_TFTP=y
+CONFIG_NET_TFTP_PUSH=y
+CONFIG_DRIVER_SERIAL_IMX=y
+CONFIG_ARCH_HAS_FEC_IMX=y
+CONFIG_MIIDEV=y
+CONFIG_DRIVER_NET_FEC_IMX=y
+CONFIG_DRIVER_SPI_IMX_2_3=y
+CONFIG_MTD=y
+CONFIG_MTD_WRITE=y
+CONFIG_MTD_OOB_DEVICE=y
+CONFIG_NAND=y
+CONFIG_NAND_ECC_SOFT=y
+CONFIG_NAND_ECC_HW=y
+CONFIG_NAND_ECC_HW_SYNDROME=y
+CONFIG_NAND_ECC_HW_NONE=y
+CONFIG_NAND_INFO=y
+CONFIG_NAND_READ_OOB=y
+CONFIG_NAND_BBT=y
+CONFIG_NAND_IMX=y
+CONFIG_MTD_NAND_IDS=y
+CONFIG_UBI=y
+CONFIG_DISK=y
+CONFIG_DISK_WRITE=y
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_INFO=y
+CONFIG_MCI_WRITE=y
+CONFIG_MCI_IMX_ESDHC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_FS_RAMFS=y
+CONFIG_FS_DEVFS=y
+CONFIG_FS_FAT=y
+CONFIG_PARTITION_NEED_MTD=y
+CONFIG_PARAMETER=y
+CONFIG_UNCOMPRESS=y
+CONFIG_ZLIB=y
+CONFIG_PROCESS_ESCAPE_SEQUENCE=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_CRC32=y
diff --git a/arch/arm/configs/usb_a9260_defconfig b/arch/arm/configs/usb_a9260_defconfig
index c0143c0f20..85e7878207 100644
--- a/arch/arm/configs/usb_a9260_defconfig
+++ b/arch/arm/configs/usb_a9260_defconfig
@@ -3,6 +3,7 @@ CONFIG_MACH_USB_A9260=y
 CONFIG_AEABI=y
 # CONFIG_CMD_ARM_CPUINFO is not set
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_MMU=y
 CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_PROMPT="USB-9G20:"
@@ -21,7 +22,6 @@ CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/usb-a926x/env"
 CONFIG_CMD_EDIT=y
 CONFIG_CMD_SLEEP=y
 CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_LOADENV=y
 CONFIG_CMD_EXPORT=y
 CONFIG_CMD_PRINTENV=y
 CONFIG_CMD_READLINE=y
@@ -33,12 +33,14 @@ CONFIG_CMD_LOADB=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MD5SUM=y
 CONFIG_CMD_SHA1SUM=y
-CONFIG_CMD_SHA256SUM=y
 CONFIG_CMD_MTEST=y
 CONFIG_CMD_MTEST_ALTERNATIVE=y
 CONFIG_CMD_FLASH=y
 CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
 CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
 CONFIG_CMD_UIMAGE=y
 # CONFIG_CMD_BOOTZ is not set
 # CONFIG_CMD_BOOTU is not set
@@ -61,6 +63,7 @@ CONFIG_NET_RESOLV=y
 CONFIG_DRIVER_NET_MACB=y
 # CONFIG_SPI is not set
 CONFIG_MTD=y
+# CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
 # CONFIG_NAND_ECC_HW is not set
 # CONFIG_NAND_ECC_HW_SYNDROME is not set
diff --git a/arch/arm/configs/usb_a9263_128mib_defconfig b/arch/arm/configs/usb_a9263_128mib_defconfig
index cfbb93cd60..23bc3d7fb7 100644
--- a/arch/arm/configs/usb_a9263_128mib_defconfig
+++ b/arch/arm/configs/usb_a9263_128mib_defconfig
@@ -4,9 +4,10 @@ CONFIG_AEABI=y
 # CONFIG_CMD_ARM_CPUINFO is not set
 CONFIG_AT91_HAVE_SRAM_128M=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_MMU=y
 CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
-CONFIG_PROMPT="USB-9G20:"
+CONFIG_PROMPT="USB-9263:"
 CONFIG_LONGHELP=y
 CONFIG_GLOB=y
 CONFIG_PROMPT_HUSH_PS2="y"
@@ -22,7 +23,6 @@ CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/usb-a926x/env"
 CONFIG_CMD_EDIT=y
 CONFIG_CMD_SLEEP=y
 CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_LOADENV=y
 CONFIG_CMD_EXPORT=y
 CONFIG_CMD_PRINTENV=y
 CONFIG_CMD_READLINE=y
@@ -34,12 +34,14 @@ CONFIG_CMD_LOADB=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MD5SUM=y
 CONFIG_CMD_SHA1SUM=y
-CONFIG_CMD_SHA256SUM=y
 CONFIG_CMD_MTEST=y
 CONFIG_CMD_MTEST_ALTERNATIVE=y
 CONFIG_CMD_FLASH=y
 CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
 CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
 CONFIG_CMD_UIMAGE=y
 # CONFIG_CMD_BOOTZ is not set
 # CONFIG_CMD_BOOTU is not set
@@ -62,6 +64,7 @@ CONFIG_NET_RESOLV=y
 CONFIG_DRIVER_NET_MACB=y
 # CONFIG_SPI is not set
 CONFIG_MTD=y
+# CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
 # CONFIG_NAND_ECC_HW is not set
 # CONFIG_NAND_ECC_HW_SYNDROME is not set
diff --git a/arch/arm/configs/usb_a9263_defconfig b/arch/arm/configs/usb_a9263_defconfig
index 1e9ee589b8..96ea3e1879 100644
--- a/arch/arm/configs/usb_a9263_defconfig
+++ b/arch/arm/configs/usb_a9263_defconfig
@@ -3,9 +3,10 @@ CONFIG_MACH_USB_A9263=y
 CONFIG_AEABI=y
 # CONFIG_CMD_ARM_CPUINFO is not set
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_MMU=y
 CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
-CONFIG_PROMPT="USB-9G20:"
+CONFIG_PROMPT="USB-9263:"
 CONFIG_LONGHELP=y
 CONFIG_GLOB=y
 CONFIG_PROMPT_HUSH_PS2="y"
@@ -33,12 +34,14 @@ CONFIG_CMD_LOADB=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MD5SUM=y
 CONFIG_CMD_SHA1SUM=y
-CONFIG_CMD_SHA256SUM=y
 CONFIG_CMD_MTEST=y
 CONFIG_CMD_MTEST_ALTERNATIVE=y
 CONFIG_CMD_FLASH=y
 CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
 CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
 CONFIG_CMD_UIMAGE=y
 # CONFIG_CMD_BOOTZ is not set
 # CONFIG_CMD_BOOTU is not set
@@ -61,6 +64,7 @@ CONFIG_NET_RESOLV=y
 CONFIG_DRIVER_NET_MACB=y
 # CONFIG_SPI is not set
 CONFIG_MTD=y
+# CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
 # CONFIG_NAND_ECC_HW is not set
 # CONFIG_NAND_ECC_HW_SYNDROME is not set
diff --git a/arch/arm/configs/usb_a9g20_128mib_defconfig b/arch/arm/configs/usb_a9g20_128mib_defconfig
index 4ba4fe82b8..c25d7dec57 100644
--- a/arch/arm/configs/usb_a9g20_128mib_defconfig
+++ b/arch/arm/configs/usb_a9g20_128mib_defconfig
@@ -4,6 +4,7 @@ CONFIG_AEABI=y
 # CONFIG_CMD_ARM_CPUINFO is not set
 CONFIG_AT91_HAVE_SRAM_128M=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_MMU=y
 CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_PROMPT="USB-9G20:"
@@ -22,7 +23,6 @@ CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/usb-a926x/env"
 CONFIG_CMD_EDIT=y
 CONFIG_CMD_SLEEP=y
 CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_LOADENV=y
 CONFIG_CMD_EXPORT=y
 CONFIG_CMD_PRINTENV=y
 CONFIG_CMD_READLINE=y
@@ -34,12 +34,14 @@ CONFIG_CMD_LOADB=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MD5SUM=y
 CONFIG_CMD_SHA1SUM=y
-CONFIG_CMD_SHA256SUM=y
 CONFIG_CMD_MTEST=y
 CONFIG_CMD_MTEST_ALTERNATIVE=y
 CONFIG_CMD_FLASH=y
 CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
 CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
 CONFIG_CMD_UIMAGE=y
 # CONFIG_CMD_BOOTZ is not set
 # CONFIG_CMD_BOOTU is not set
@@ -62,6 +64,7 @@ CONFIG_NET_RESOLV=y
 CONFIG_DRIVER_NET_MACB=y
 # CONFIG_SPI is not set
 CONFIG_MTD=y
+# CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
 # CONFIG_NAND_ECC_HW is not set
 # CONFIG_NAND_ECC_HW_SYNDROME is not set
diff --git a/arch/arm/configs/usb_a9g20_defconfig b/arch/arm/configs/usb_a9g20_defconfig
index 616144b5a5..d645adb618 100644
--- a/arch/arm/configs/usb_a9g20_defconfig
+++ b/arch/arm/configs/usb_a9g20_defconfig
@@ -3,6 +3,7 @@ CONFIG_MACH_USB_A9G20=y
 CONFIG_AEABI=y
 # CONFIG_CMD_ARM_CPUINFO is not set
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_MMU=y
 CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_PROMPT="USB-9G20:"
@@ -21,7 +22,6 @@ CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/usb-a926x/env"
 CONFIG_CMD_EDIT=y
 CONFIG_CMD_SLEEP=y
 CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_LOADENV=y
 CONFIG_CMD_EXPORT=y
 CONFIG_CMD_PRINTENV=y
 CONFIG_CMD_READLINE=y
@@ -33,12 +33,14 @@ CONFIG_CMD_LOADB=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MD5SUM=y
 CONFIG_CMD_SHA1SUM=y
-CONFIG_CMD_SHA256SUM=y
 CONFIG_CMD_MTEST=y
 CONFIG_CMD_MTEST_ALTERNATIVE=y
 CONFIG_CMD_FLASH=y
 CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
 CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
 CONFIG_CMD_UIMAGE=y
 # CONFIG_CMD_BOOTZ is not set
 # CONFIG_CMD_BOOTU is not set
@@ -61,6 +63,7 @@ CONFIG_NET_RESOLV=y
 CONFIG_DRIVER_NET_MACB=y
 # CONFIG_SPI is not set
 CONFIG_MTD=y
+# CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
 # CONFIG_NAND_ECC_HW is not set
 # CONFIG_NAND_ECC_HW_SYNDROME is not set
diff --git a/arch/arm/cpu/cpuinfo.c b/arch/arm/cpu/cpuinfo.c
index 09acb5f4de..ca986f8013 100644
--- a/arch/arm/cpu/cpuinfo.c
+++ b/arch/arm/cpu/cpuinfo.c
@@ -22,6 +22,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <complete.h>
 
 #define CPU_ARCH_UNKNOWN	0
 #define CPU_ARCH_ARMv3		1
@@ -181,5 +182,6 @@ static int do_cpuinfo(int argc, char *argv[])
 BAREBOX_CMD_START(cpuinfo)
 	.cmd            = do_cpuinfo,
 	.usage          = "Show info about CPU",
+	BAREBOX_CMD_COMPLETE(empty_complete)
 BAREBOX_CMD_END
 
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index defc89b7fd..c4a50c301c 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -13,6 +13,9 @@
 #include <errno.h>
 #include <sizes.h>
 #include <libbb.h>
+#include <magicvar.h>
+#include <libfdt.h>
+#include <binfmt.h>
 
 #include <asm/byteorder.h>
 #include <asm/setup.h>
@@ -123,6 +126,70 @@ struct zimage_header {
 
 #define ZIMAGE_MAGIC 0x016F2818
 
+static int do_bootz_linux_fdt(int fd, struct image_data *data)
+{
+	struct fdt_header __header, *header;
+	struct resource *r = data->os_res;
+	struct resource *of_res = data->os_res;
+	void *oftree;
+	int ret;
+
+	u32 end;
+
+	header = &__header;
+	ret = read(fd, header, sizeof(*header));
+	if (ret < sizeof(*header))
+		return ret;
+
+	if (file_detect_type(header) != filetype_oftree)
+		return -ENXIO;
+
+	end = be32_to_cpu(header->totalsize);
+
+	if (IS_BUILTIN(CONFIG_OFTREE)) {
+		oftree = malloc(end + 0x8000);
+		if (!oftree) {
+			perror("zImage: oftree malloc");
+			return -ENOMEM;
+		}
+	} else {
+
+		of_res = request_sdram_region("oftree", r->start + r->size, end);
+		if (!of_res) {
+			perror("zImage: oftree request_sdram_region");
+			return -ENOMEM;
+		}
+
+		oftree = (void*)of_res->start;
+	}
+
+	memcpy(oftree, header, sizeof(*header));
+
+	end -= sizeof(*header);
+
+	ret = read_full(fd, oftree + sizeof(*header), end);
+	if (ret < 0)
+		return ret;
+	if (ret < end) {
+		printf("premature end of image\n");
+		return -EIO;
+	}
+
+	if (IS_BUILTIN(CONFIG_OFTREE)) {
+		fdt_open_into(oftree, oftree, end + 0x8000);
+
+		ret = of_fix_tree(oftree);
+		if (ret)
+			return ret;
+
+		data->oftree = oftree;
+	}
+
+	pr_info("zImage: concatenated oftree detected\n");
+
+	return 0;
+}
+
 static int do_bootz_linux(struct image_data *data)
 {
 	int fd, ret, swap = 0;
@@ -173,6 +240,8 @@ static int do_bootz_linux(struct image_data *data)
 
 	data->os_res = request_sdram_region("zimage", load_address, end);
 	if (!data->os_res) {
+		pr_err("bootm/zImage: failed to request memory at 0x%lx to 0x%lx (%d).\n",
+		       load_address, load_address + end, end);
 		ret = -ENOMEM;
 		goto err_out;
 	}
@@ -196,6 +265,10 @@ static int do_bootz_linux(struct image_data *data)
 			*(u32 *)ptr = swab32(*(u32 *)ptr);
 	}
 
+	ret = do_bootz_linux_fdt(fd, data);
+	if (ret && ret != -ENXIO)
+		return ret;
+
 	return __do_bootm_linux(data, swap);
 
 err_out:
@@ -231,12 +304,177 @@ static struct image_handler barebox_handler = {
 	.filetype = filetype_arm_barebox,
 };
 
+#include <aimage.h>
+
+static int aimage_load_resource(int fd, struct resource *r, void* buf, int ps)
+{
+	int ret;
+	void *image = (void *)r->start;
+	unsigned to_read = ps - r->size % ps;
+
+	ret = read_full(fd, image, r->size);
+	if (ret < 0)
+		return ret;
+
+	ret = read_full(fd, buf, to_read);
+	if (ret < 0)
+		printf("could not read dummy %d\n", to_read);
+
+	return ret;
+}
+
+static int do_bootm_aimage(struct image_data *data)
+{
+	struct resource *snd_stage_res;
+	int fd, ret;
+	struct android_header __header, *header;
+	void *buf;
+	int to_read;
+	struct android_header_comp *cmp;
+
+	fd = open(data->os_file, O_RDONLY);
+	if (fd < 0) {
+		perror("open");
+		return 1;
+	}
+
+	header = &__header;
+	ret = read(fd, header, sizeof(*header));
+	if (ret < sizeof(*header)) {
+		printf("could not read %s\n", data->os_file);
+		goto err_out;
+	}
+
+	printf("Android Image for '%s'\n", header->name);
+
+	/*
+	 * As on tftp we do not support lseek and we will just have to seek
+	 * for the size of a page - 1 max just buffer instead to read to dummy
+	 * data
+	 */
+	buf = xmalloc(header->page_size);
+
+	to_read = header->page_size - sizeof(*header);
+	ret = read_full(fd, buf, to_read);
+	if (ret < 0) {
+		printf("could not read dummy %d from %s\n", to_read, data->os_file);
+		goto err_out;
+	}
+
+	cmp = &header->kernel;
+	data->os_res = request_sdram_region("akernel", cmp->load_addr, cmp->size);
+	if (!data->os_res) {
+		ret = -ENOMEM;
+		goto err_out;
+	}
+
+	ret = aimage_load_resource(fd, data->os_res, buf, header->page_size);
+	if (ret < 0) {
+		perror("could not read kernel");
+		goto err_out;
+	}
+
+	/*
+	 * fastboot always expect a ramdisk
+	 * in barebox we can be less restrictive
+	 */
+	cmp = &header->ramdisk;
+	if (cmp->size) {
+		data->initrd_res = request_sdram_region("ainitrd", cmp->load_addr, cmp->size);
+		if (!data->initrd_res) {
+			ret = -ENOMEM;
+			goto err_out;
+		}
+
+		ret = aimage_load_resource(fd, data->initrd_res, buf, header->page_size);
+		if (ret < 0) {
+			perror("could not read initrd");
+			goto err_out;
+		}
+	}
+
+	if (!getenv("aimage_noverwrite_bootargs"))
+		setenv("bootargs", header->cmdline);
+
+	if (!getenv("aimage_noverwrite_tags"))
+		armlinux_set_bootparams((void*)header->tags_addr);
+
+	if (data->oftree) {
+		ret = of_fix_tree(data->oftree);
+		if (ret)
+			goto err_out;
+	}
+
+	cmp = &header->second_stage;
+	if (cmp->size) {
+		void (*second)(void);
+
+		snd_stage_res = request_sdram_region("asecond", cmp->load_addr, cmp->size);
+		if (!snd_stage_res) {
+			ret = -ENOMEM;
+			goto err_out;
+		}
+
+		ret = aimage_load_resource(fd, snd_stage_res, buf, header->page_size);
+		if (ret < 0) {
+			perror("could not read initrd");
+			goto err_out;
+		}
+
+		second = (void*)snd_stage_res->start;
+		shutdown_barebox();
+
+		second();
+
+		reset_cpu(0);
+	}
+
+	return __do_bootm_linux(data, 0);
+
+err_out:
+	close(fd);
+
+	return ret;
+}
+
+static struct image_handler aimage_handler = {
+	.name = "ARM Android Image",
+	.bootm = do_bootm_aimage,
+	.filetype = filetype_aimage,
+};
+
+#ifdef CONFIG_CMD_BOOTM_AIMAGE
+BAREBOX_MAGICVAR(aimage_noverwrite_bootargs, "Disable overwrite of the bootargs with the one present in aimage");
+BAREBOX_MAGICVAR(aimage_noverwrite_tags, "Disable overwrite of the tags addr with the one present in aimage");
+#endif
+
+static struct binfmt_hook binfmt_aimage_hook = {
+	.type = filetype_aimage,
+	.exec = "bootm",
+};
+
+static struct binfmt_hook binfmt_arm_zimage_hook = {
+	.type = filetype_arm_zimage,
+	.exec = "bootm",
+};
+
+static struct binfmt_hook binfmt_barebox_hook = {
+	.type = filetype_arm_barebox,
+	.exec = "bootm",
+};
+
 static int armlinux_register_image_handler(void)
 {
 	register_image_handler(&barebox_handler);
 	register_image_handler(&uimage_handler);
 	register_image_handler(&rawimage_handler);
 	register_image_handler(&zimage_handler);
+	if (IS_BUILTIN(CONFIG_CMD_BOOTM_AIMAGE)) {
+		register_image_handler(&aimage_handler);
+		binfmt_register(&binfmt_aimage_hook);
+	}
+	binfmt_register(&binfmt_arm_zimage_hook);
+	binfmt_register(&binfmt_barebox_hook);
 
 	return 0;
 }
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 7e721e5ccf..a165cc9459 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -38,8 +38,8 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
 	if (!data)
 		return;
 
-	add_generic_device("at91_ohci", -1, NULL, AT91RM9200_UHP_BASE, 1024 * 1024,
-			   IORESOURCE_MEM, data);
+	add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91RM9200_UHP_BASE,
+			1024 * 1024, IORESOURCE_MEM, data);
 }
 #else
 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
@@ -60,8 +60,8 @@ void __init at91_add_device_udc(struct at91_udc_data *data)
 	if (data->pullup_pin > 0)
 		at91_set_gpio_output(data->pullup_pin, 0);
 
-	add_generic_device("at91_udc", -1, NULL, AT91RM9200_BASE_UDP, SZ_16K,
-			   IORESOURCE_MEM, data);
+	add_generic_device("at91_udc", DEVICE_ID_DYNAMIC, NULL, AT91RM9200_BASE_UDP,
+			SZ_16K, IORESOURCE_MEM, data);
 }
 #else
 void __init at91_add_device_udc(struct at91_udc_data *data) {}
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 17dbd1a1e4..33f070a91e 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -40,8 +40,8 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
 	if (!data)
 		return;
 
-	add_generic_device("at91_ohci", -1, NULL, AT91SAM9260_UHP_BASE, 1024 * 1024,
-			   IORESOURCE_MEM, data);
+	add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9260_UHP_BASE,
+			1024 * 1024, IORESOURCE_MEM, data);
 }
 #else
 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
@@ -59,8 +59,8 @@ void __init at91_add_device_udc(struct at91_udc_data *data)
 		at91_set_deglitch(data->vbus_pin, 1);
 	}
 
-	add_generic_device("at91_udc", -1, NULL, AT91SAM9260_BASE_UDP, SZ_16K,
-			   IORESOURCE_MEM, data);
+	add_generic_device("at91_udc", DEVICE_ID_DYNAMIC, NULL, AT91SAM9260_BASE_UDP,
+			SZ_16K,  IORESOURCE_MEM, data);
 }
 #else
 void __init at91_add_device_udc(struct at91_udc_data *data) {}
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 8a63d2a4eb..82d17a275e 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -43,8 +43,8 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
 	if (!data)
 		return;
 
-	add_generic_device("at91_ohci", -1, NULL, AT91SAM9261_UHP_BASE, 1024 * 1024,
-			   IORESOURCE_MEM, data);
+	add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9261_UHP_BASE,
+			1024 * 1024, IORESOURCE_MEM, data);
 }
 #else
 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
@@ -62,8 +62,8 @@ void __init at91_add_device_udc(struct at91_udc_data *data)
 		at91_set_deglitch(data->vbus_pin, 1);
 	}
 
-	add_generic_device("at91_udc", -1, NULL, AT91SAM9261_BASE_UDP, SZ_16K,
-			   IORESOURCE_MEM, data);
+	add_generic_device("at91_udc", DEVICE_ID_DYNAMIC, NULL, AT91SAM9261_BASE_UDP,
+			SZ_16K, IORESOURCE_MEM, data);
 }
 #else
 void __init at91_add_device_udc(struct at91_udc_data *data) {}
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index b28e9e26f3..4500d813f6 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -48,8 +48,8 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
 			at91_set_gpio_output(data->vbus_pin[i], 0);
 	}
 
-	add_generic_device("at91_ohci", -1, NULL, AT91SAM9263_UHP_BASE, 1024 * 1024,
-			   IORESOURCE_MEM, data);
+	add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9263_UHP_BASE,
+			1024 * 1024, IORESOURCE_MEM, data);
 }
 #else
 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
@@ -67,7 +67,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data)
 		at91_set_deglitch(data->vbus_pin, 1);
 	}
 
-	add_generic_device("at91_udc", -1, NULL, AT91SAM9263_BASE_UDP, SZ_16K,
+	add_generic_device("at91_udc", DEVICE_ID_DYNAMIC, NULL, AT91SAM9263_BASE_UDP, SZ_16K,
 			   IORESOURCE_MEM, data);
 }
 #else
@@ -145,7 +145,7 @@ void at91_add_device_nand(struct atmel_nand_data *data)
 	if (data->det_pin)
 		at91_set_gpio_input(data->det_pin, 1);
 
-	add_generic_device_res("atmel_nand", -1, nand_resources,
+	add_generic_device_res("atmel_nand", DEVICE_ID_DYNAMIC, nand_resources,
 			       ARRAY_SIZE(nand_resources), data);
 }
 #else
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index ca96f58a7f..273cd0eecc 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -46,8 +46,8 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
 			at91_set_gpio_output(data->vbus_pin[i], 0);
 	}
 
-	add_generic_device("at91_ohci", -1, NULL, AT91SAM9G45_OHCI_BASE, 1024 * 1024,
-			   IORESOURCE_MEM, data);
+	add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9G45_OHCI_BASE,
+			1024 * 1024, IORESOURCE_MEM, data);
 }
 #else
 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
@@ -125,7 +125,7 @@ void at91_add_device_nand(struct atmel_nand_data *data)
 	if (data->det_pin)
 		at91_set_gpio_input(data->det_pin, 1);
 
-	add_generic_device_res("atmel_nand", -1, nand_resources,
+	add_generic_device_res("atmel_nand", DEVICE_ID_DYNAMIC, nand_resources,
 			       ARRAY_SIZE(nand_resources), data);
 }
 #else
diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
index 76f67b0c39..51a2024fbe 100644
--- a/arch/arm/mach-at91/at91sam9x5_devices.c
+++ b/arch/arm/mach-at91/at91sam9x5_devices.c
@@ -47,8 +47,8 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
 			at91_set_gpio_output(data->vbus_pin[i], 0);
 	}
 
-	add_generic_device("at91_ohci", -1, NULL, AT91SAM9X5_OHCI_BASE, SZ_1M,
-			   IORESOURCE_MEM, data);
+	add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9X5_OHCI_BASE,
+			SZ_1M, IORESOURCE_MEM, data);
 }
 #else
 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 75e87fe544..32367627d4 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -24,6 +24,8 @@ config ARCH_TEXT_BASE
 	default 0x87f00000 if MACH_GUF_CUPID
 	default 0x93d00000 if MACH_TX25
 	default 0x7ff00000 if MACH_TQMA53
+	default 0x97f00000 if MACH_TX51
+	default 0x4fc00000 if MACH_MX6Q_ARM2
 
 config BOARDINFO
 	default "Eukrea CPUIMX25" if MACH_EUKREA_CPUIMX25
@@ -46,6 +48,8 @@ config BOARDINFO
 	default "Garz+Fricke Cupid" if MACH_GUF_CUPID
 	default "Ka-Ro tx25" if MACH_TX25
 	default "TQ tqma53" if MACH_TQMA53
+	default "Ka-Ro tx51" if MACH_TX51
+	default "Freescale i.MX6q armadillo2" if MACH_MX6Q_ARM2
 
 choice
 	prompt "Select boot mode"
@@ -68,7 +72,7 @@ choice
 
 config ARCH_IMX_INTERNAL_BOOT
 	bool "support internal boot mode"
-	depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51 || ARCH_IMX53
+	depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51 || ARCH_IMX53 || ARCH_IMX6
 
 config ARCH_IMX_EXTERNAL_BOOT
 	bool "support external boot mode"
@@ -165,6 +169,11 @@ config ARCH_IMX53
 	select CPU_V7
 	select ARCH_HAS_FEC_IMX
 
+config ARCH_IMX6
+	bool "i.MX6"
+	select ARCH_HAS_FEC_IMX
+	select CPU_V7
+
 endchoice
 
 # ----------------------------------------------------------
@@ -280,7 +289,7 @@ config MACH_PCM038
 	select MACH_HAS_LOWLEVEL_INIT
 	select SPI
 	select DRIVER_SPI_IMX
-	select DRIVER_SPI_MC13783
+	select MFD_MC13XXX
 	help
 	  Say Y here if you are using Phytec's phyCORE-i.MX27 (pcm038) equipped
 	  with a Freescale i.MX27 Processor
@@ -338,7 +347,7 @@ config MACH_FREESCALE_MX35_3STACK
 	select MACH_HAS_LOWLEVEL_INIT
 	select I2C
 	select I2C_IMX
-	select I2C_MC13892
+	select MFD_MC13XXX
 	select I2C_MC9SDZ60
 	help
 	  Say Y here if you are using the Freescale MX35 3stack board equipped
@@ -381,6 +390,12 @@ config MACH_EUKREA_CPUIMX51SD
 	  Say Y here if you are using Eukrea's CPUIMX51 equipped
 	  with a Freescale i.MX51 Processor
 
+config MACH_TX51
+	bool "Ka-Ro TX51"
+	help
+	  Say Y here if you are using the Ka-Ro tx51 board
+
+
 endchoice
 
 endif
@@ -412,6 +427,19 @@ endchoice
 
 endif
 
+if ARCH_IMX6
+
+choice
+
+	prompt "i.MX6 Board Type"
+
+config MACH_MX6Q_ARM2
+	bool "Freescale i.MX6q Armadillo2"
+
+endchoice
+
+endif
+
 # ----------------------------------------------------------
 
 menu "Board specific settings       "
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index a9aa9e2655..03e24218c1 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o
 obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o
 obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o imx5.o
 obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o imx5.o
+obj-$(CONFIG_ARCH_IMX6) += speed-imx6.o imx6.o iomux-v3.o
 obj-$(CONFIG_IMX_CLKO)	+= clko.o
 obj-$(CONFIG_IMX_IIM)	+= iim.o
 obj-$(CONFIG_NAND_IMX) += nand.o
diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c
index 381a564580..fe0c99ea72 100644
--- a/arch/arm/mach-imx/imx35.c
+++ b/arch/arm/mach-imx/imx35.c
@@ -37,7 +37,8 @@ int imx_silicon_revision()
 {
 	uint32_t reg;
 	reg = readl(IMX_IIM_BASE + IIM_SREV);
-	reg += IMX35_CHIP_REVISION_1_0;
+	/* 0×00 = TO 1.0, First silicon */
+	reg += IMX_CHIP_REV_1_0;
 
 	return (reg & 0xFF);
 }
diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c
index 02704c1188..25cc6dae5d 100644
--- a/arch/arm/mach-imx/imx51.c
+++ b/arch/arm/mach-imx/imx51.c
@@ -20,8 +20,8 @@
 #include <sizes.h>
 #include <environment.h>
 #include <io.h>
-#include <mach/imx51-regs.h>
 #include <mach/imx5.h>
+#include <mach/imx-regs.h>
 #include <mach/clock-imx51_53.h>
 
 #include "gpio.h"
@@ -53,19 +53,19 @@ static int query_silicon_revision(void)
 	rev = readl(rom + SI_REV);
 	switch (rev) {
 	case 0x1:
-		mx51_silicon_revision = MX51_CHIP_REV_1_0;
+		mx51_silicon_revision = IMX_CHIP_REV_1_0;
 		mx51_rev_string = "1.0";
 		break;
 	case 0x2:
-		mx51_silicon_revision = MX51_CHIP_REV_1_1;
+		mx51_silicon_revision = IMX_CHIP_REV_1_1;
 		mx51_rev_string = "1.1";
 		break;
 	case 0x10:
-		mx51_silicon_revision = MX51_CHIP_REV_2_0;
+		mx51_silicon_revision = IMX_CHIP_REV_2_0;
 		mx51_rev_string = "2.0";
 		break;
 	case 0x20:
-		mx51_silicon_revision = MX51_CHIP_REV_3_0;
+		mx51_silicon_revision = IMX_CHIP_REV_3_0;
 		mx51_rev_string = "3.0";
 		break;
 	default:
@@ -186,7 +186,7 @@ coredevice_initcall(imx51_boot_save_loc);
 #define setup_pll_455(base)	imx5_setup_pll((base), 455,  (( 9 << 4) + ((2 - 1) << 0)), (48 - 1), 23)
 #define setup_pll_216(base)	imx5_setup_pll((base), 216,  (( 6 << 4) + ((3 - 1) << 0)), ( 4 - 1),  3)
 
-void imx51_init_lowlevel(void)
+void imx51_init_lowlevel(unsigned int cpufreq_mhz)
 {
 	void __iomem *ccm = (void __iomem *)MX51_CCM_BASE_ADDR;
 	u32 r;
@@ -194,7 +194,7 @@ void imx51_init_lowlevel(void)
 	imx5_init_lowlevel();
 
 	/* disable write combine for TO 2 and lower revs */
-	if (imx_silicon_revision() < MX51_CHIP_REV_3_0) {
+	if (imx_silicon_revision() < IMX_CHIP_REV_3_0) {
 		__asm__ __volatile__("mrc 15, 1, %0, c9, c0, 1":"=r"(r));
 		r |= (1 << 25);
 		__asm__ __volatile__("mcr 15, 1, %0, c9, c0, 1" : : "r"(r));
@@ -220,7 +220,16 @@ void imx51_init_lowlevel(void)
 	/* Switch ARM to step clock */
 	writel(0x4, ccm + MX5_CCM_CCSR);
 
-	setup_pll_800((void __iomem *)MX51_PLL1_BASE_ADDR);
+	switch (cpufreq_mhz) {
+	case 600:
+		setup_pll_600((void __iomem *)MX51_PLL1_BASE_ADDR);
+		break;
+	default:
+		/* Default maximum 800MHz */
+		setup_pll_800((void __iomem *)MX51_PLL1_BASE_ADDR);
+		break;
+	}
+
 	setup_pll_665((void __iomem *)MX51_PLL3_BASE_ADDR);
 
 	/* Switch peripheral to PLL 3 */
diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c
index 8742c46d0b..b5dbc39dad 100644
--- a/arch/arm/mach-imx/imx53.c
+++ b/arch/arm/mach-imx/imx53.c
@@ -154,10 +154,15 @@ void imx53_init_lowlevel(unsigned int cpufreq_mhz)
 
 	writel(0x00016154, ccm + MX5_CCM_CBCMR);
 
-	/* change uart clk parent to pll2 */
 	r = readl(ccm + MX5_CCM_CSCMR1);
-	r &= ~(3 << 24);
-	r |= (1 << 24);
+
+	/* change uart clk parent to pll2 */
+	r &= ~MX5_CCM_CSCMR1_UART_CLK_SEL_MASK;
+	r |= 1 << MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
+
+	/* USB phy clock from osc */
+	r &= ~(1 << MX5_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET);
+
 	writel(r, ccm + MX5_CCM_CSCMR1);
 
 	/* make sure change is effective */
@@ -187,6 +192,12 @@ void imx53_init_lowlevel(unsigned int cpufreq_mhz)
 	r &= ~MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK;
 	r |= 1 << MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET;
 
+	r &= ~MX5_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
+	r &= ~MX5_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
+
+	r |= 3 << MX5_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
+	r |= 1 << MX5_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
+
 	writel(r, ccm + MX5_CCM_CSCDR1);
 
 	/* Restore the default values in the Gate registers */
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
new file mode 100644
index 0000000000..a443343853
--- /dev/null
+++ b/arch/arm/mach-imx/imx6.c
@@ -0,0 +1,71 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <init.h>
+#include <common.h>
+#include <io.h>
+#include <sizes.h>
+#include <mach/imx6-regs.h>
+
+#include "gpio.h"
+
+void *imx_gpio_base[] = {
+	(void *)MX6_GPIO1_BASE_ADDR,
+	(void *)MX6_GPIO2_BASE_ADDR,
+	(void *)MX6_GPIO3_BASE_ADDR,
+	(void *)MX6_GPIO4_BASE_ADDR,
+	(void *)MX6_GPIO5_BASE_ADDR,
+	(void *)MX6_GPIO6_BASE_ADDR,
+	(void *)MX6_GPIO7_BASE_ADDR,
+};
+
+int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32;
+
+void imx6_init_lowlevel(void)
+{
+	void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR;
+	void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR;
+
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	writel(0x77777777, aips1);
+	writel(0x77777777, aips1 + 0x4);
+	writel(0, aips1 + 0x40);
+	writel(0, aips1 + 0x44);
+	writel(0, aips1 + 0x48);
+	writel(0, aips1 + 0x4c);
+	writel(0, aips1 + 0x50);
+
+	writel(0x77777777, aips2);
+	writel(0x77777777, aips2 + 0x4);
+	writel(0, aips2 + 0x40);
+	writel(0, aips2 + 0x44);
+	writel(0, aips2 + 0x48);
+	writel(0, aips2 + 0x4c);
+	writel(0, aips2 + 0x50);
+
+	/* enable all clocks */
+	writel(0xffffffff, 0x020c4068);
+	writel(0xffffffff, 0x020c406c);
+	writel(0xffffffff, 0x020c4070);
+	writel(0xffffffff, 0x020c4074);
+	writel(0xffffffff, 0x020c4078);
+	writel(0xffffffff, 0x020c407c);
+	writel(0xffffffff, 0x020c4080);
+}
diff --git a/arch/arm/mach-imx/include/mach/clock-imx6.h b/arch/arm/mach-imx/include/mach/clock-imx6.h
new file mode 100644
index 0000000000..8e5e9d92b0
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/clock-imx6.h
@@ -0,0 +1,347 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_MX6_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX6_CRM_REGS_H__
+
+#define MXC_CCM_BASE   MX6_CCM_BASE_ADDR
+
+/* Register addresses of CCM*/
+#define MXC_CCM_CCR		(MXC_CCM_BASE + 0x00)
+#define MXC_CCM_CCDR		(MXC_CCM_BASE + 0x04)
+#define MXC_CCM_CSR		(MXC_CCM_BASE + 0x08)
+#define MXC_CCM_CCSR		(MXC_CCM_BASE + 0x0C)
+#define MXC_CCM_CACRR		(MXC_CCM_BASE + 0x10)
+#define MXC_CCM_CBCDR		(MXC_CCM_BASE + 0x14)
+#define MXC_CCM_CBCMR		(MXC_CCM_BASE + 0x18)
+#define MXC_CCM_CSCMR1		(MXC_CCM_BASE + 0x1C)
+#define MXC_CCM_CSCMR2		(MXC_CCM_BASE + 0x20)
+#define MXC_CCM_CSCDR1		(MXC_CCM_BASE + 0x24)
+#define MXC_CCM_CS1CDR		(MXC_CCM_BASE + 0x28)
+#define MXC_CCM_CS2CDR		(MXC_CCM_BASE + 0x2C)
+#define MXC_CCM_CDCDR		(MXC_CCM_BASE + 0x30)
+#define MXC_CCM_CHSCDR		(MXC_CCM_BASE + 0x34)
+#define MXC_CCM_CSCDR2		(MXC_CCM_BASE + 0x38)
+#define MXC_CCM_CSCDR3		(MXC_CCM_BASE + 0x3C)
+#define MXC_CCM_CSCDR4		(MXC_CCM_BASE + 0x40)
+#define MXC_CCM_CWDR		(MXC_CCM_BASE + 0x44)
+#define MXC_CCM_CDHIPR		(MXC_CCM_BASE + 0x48)
+#define MXC_CCM_CDCR		(MXC_CCM_BASE + 0x4C)
+#define MXC_CCM_CTOR		(MXC_CCM_BASE + 0x50)
+#define MXC_CCM_CLPCR		(MXC_CCM_BASE + 0x54)
+#define MXC_CCM_CISR		(MXC_CCM_BASE + 0x58)
+#define MXC_CCM_CIMR		(MXC_CCM_BASE + 0x5C)
+#define MXC_CCM_CCOSR		(MXC_CCM_BASE + 0x60)
+#define MXC_CCM_CGPR		(MXC_CCM_BASE + 0x64)
+#define MXC_CCM_CCGR0		(MXC_CCM_BASE + 0x68)
+#define MXC_CCM_CCGR1		(MXC_CCM_BASE + 0x6C)
+#define MXC_CCM_CCGR2		(MXC_CCM_BASE + 0x70)
+#define MXC_CCM_CCGR3		(MXC_CCM_BASE + 0x74)
+#define MXC_CCM_CCGR4		(MXC_CCM_BASE + 0x78)
+#define MXC_CCM_CCGR5		(MXC_CCM_BASE + 0x7C)
+#define MXC_CCM_CCGR6		(MXC_CCM_BASE + 0x80)
+#define MXC_CCM_CCGR7		(MXC_CCM_BASE + 0x80)
+#define MXC_CCM_CMEOR		(MXC_CCM_BASE + 0x88)
+
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_RBC_EN				(1 << 27)
+#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK 		(0x3F << 21)
+#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 		(21)
+#define MXC_CCM_CCR_WB_COUNT_MASK 			(0x7)
+#define MXC_CCM_CCR_WB_COUNT_OFFSET			(1 << 16)
+#define MXC_CCM_CCR_COSC_EN				(1 << 12)
+#define MXC_CCM_CCR_OSCNT_MASK				(0xFF)
+#define MXC_CCM_CCR_OSCNT_OFFSET			(0)
+
+/* Define the bits in register CCDR */
+#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK			(1 << 16)
+#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK			(1 << 17)
+
+/* Define the bits in register CSR */
+#define MXC_CCM_CSR_COSC_READY				(1 << 5)
+#define MXC_CCM_CSR_REF_EN_B				(1 << 0)
+
+/* Define the bits in register CCSR */
+#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS			(1 << 15)
+#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS			(1 << 14)
+#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS			(1 << 13)
+#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS			(1 << 12)
+#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS			(1 << 11)
+#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS			(1 << 10)
+#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS			(1 << 9)
+#define MXC_CCM_CCSR_STEP_SEL				(1 << 8)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL			(1 << 2)
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL			(1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL			(1 << 0)
+
+/* Define the bits in register CACRR */
+#define MXC_CCM_CACRR_ARM_PODF_OFFSET			(0)
+#define MXC_CCM_CACRR_ARM_PODF_MASK			(0x7)
+
+/* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK		(0x7 << 27)
+#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET		(27)
+#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL			(1 << 26)
+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL			(1 << 25)
+#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK		(0x7 << 19)
+#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET		(19)
+#define MXC_CCM_CBCDR_AXI_PODF_MASK			(0x7 << 16)
+#define MXC_CCM_CBCDR_AXI_PODF_OFFSET			(16)
+#define MXC_CCM_CBCDR_AHB_PODF_MASK			(0x7 << 10)
+#define MXC_CCM_CBCDR_AHB_PODF_OFFSET			(10)
+#define MXC_CCM_CBCDR_IPG_PODF_MASK			(0x3 << 8)
+#define MXC_CCM_CBCDR_IPG_PODF_OFFSET			(8)
+#define MXC_CCM_CBCDR_AXI_ALT_SEL			(1 << 7)
+#define MXC_CCM_CBCDR_AXI_SEL				(1 << 6)
+#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK		(0x7 << 3)
+#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET		(3)
+#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK		(0x7 << 0)
+#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET		(0)
+
+/* Define the bits in register CBCMR */
+#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK		(0x7 << 29)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET		(29)
+#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK		(0x7 << 26)
+#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET		(26)
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK		(0x7 << 23)
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET		(23)
+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK		(0x3 << 21)
+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET	(21)
+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL		(1 << 20)
+#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK		(0x3 << 18)
+#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET		(18)
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK		(0x3 << 16)
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET		(16)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET		(14)
+#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK		(0x3 << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET		(12)
+#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL			(1 << 11)
+#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL			(1 << 10)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK		(0x3 << 8)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET	(8)
+#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK		(0x3 << 4)
+#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET		(4)
+#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL			(1 << 1)
+#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL			(1 << 0)
+
+/* Define the bits in register CSCMR1 */
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK		(0x3 << 29)
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET		(29)
+#define MXC_CCM_CSCMR1_ACLK_EMI_MASK			(0x3 << 27)
+#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET			(27)
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK		(0x7 << 23)
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET	(23)
+#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK		(0x7 << 20)
+#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET		(20)
+#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL			(1 << 19)
+#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL			(1 << 18)
+#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL			(1 << 17)
+#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL			(1 << 16)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET		(14)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK		(0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		(12)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 10)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		(10)
+#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK			(0x3F)
+
+/* Define the bits in register CSCMR2 */
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK		(0x3 << 19)
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET		(19)
+#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV			(1 << 11)
+#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV			(1 << 10)
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK			(0x3F << 2)
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET		(2)
+
+/* Define the bits in register CSCDR1 */
+#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK		(0x7 << 25)
+#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET		(25)
+#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK			(0x7 << 22)
+#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET		(22)
+#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK			(0x7 << 19)
+#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET		(19)
+#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK			(0x7 << 16)
+#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET		(16)
+#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK			(0x7 << 11)
+#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET		(11)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		(8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		(6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		(0x3F)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		(0)
+
+/* Define the bits in register CS1CDR */
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK		(0x3F << 25)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET		(25)
+#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK		(0x3F << 16)
+#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET		(16)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK		(0x3 << 9)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET		(9)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK		(0x7 << 6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET		(6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK		(0x3F)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET		(0)
+
+/* Define the bits in register CS2CDR */
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK		(0x3F << 21)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET		(21)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK		(0x7 << 18)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET		(18)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK		(0x3 << 16)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET		(16)
+#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK		(0x7 << 12)
+#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET		(12)
+#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK		(0x7 << 9)
+#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET		(9)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK		(0x7 << 6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET		(6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK		(0x3F)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET		(0)
+
+/* Define the bits in register CDCDR */
+#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK			(0x7 << 29)
+#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET		(29)
+#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL			(1 << 28)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK		(0x7 << 25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET		(25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK		(0x7 << 19)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET		(19)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK		(0x3 << 20)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET		(20)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK		(0x7 << 12)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET		(12)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK		(0x7 << 9)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET		(9)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK		(0x3 << 7)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET		(7)
+
+/* Define the bits in register CHSCCDR */
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET	(15)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK		(0x7 << 12)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET		(12)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK		(0x7 << 9)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET		(9)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK	(0x7 << 6)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET	(6)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK		(0x7 << 3)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET		(3)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK		(0x7)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET		(0)
+
+/* Define the bits in register CSCDR2 */
+#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK		(0x3F << 19)
+#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET		(19)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET	(15)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK		(0x7 << 12)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET		(12)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK		(0x7 << 9)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET		(9)
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK	(0x7 << 6)
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET	(6)
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK		(0x7 << 3)
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET		(3)
+#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK		(0x7)
+#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET		(0)
+
+/* Define the bits in register CSCDR3 */
+#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK		(0x7 << 16)
+#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET		(16)
+#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET		(14)
+#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK		(0x7 << 11)
+#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET		(11)
+#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK		(0x3 << 9)
+#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET		(9)
+
+/* Define the bits in register CDHIPR */
+#define MXC_CCM_CDHIPR_ARM_PODF_BUSY			(1 << 16)
+#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY		(1 << 5)
+#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY		(1 << 4)
+#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY		(1 << 3)
+#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY		(1 << 2)
+#define MXC_CCM_CDHIPR_AHB_PODF_BUSY			(1 << 1)
+#define MXC_CCM_CDHIPR_AXI_PODF_BUSY			(1)
+
+/* Define the bits in register CLPCR */
+#define MXC_CCM_CLPCR_MASK_L2CC_IDLE			(1 << 27)
+#define MXC_CCM_CLPCR_MASK_SCU_IDLE			(1 << 26)
+#define MXC_CCM_CLPCR_MASK_CORE3_WFI			(1 << 25)
+#define MXC_CCM_CLPCR_MASK_CORE2_WFI			(1 << 24)
+#define MXC_CCM_CLPCR_MASK_CORE1_WFI			(1 << 23)
+#define MXC_CCM_CLPCR_MASK_CORE0_WFI			(1 << 22)
+#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS		(1 << 21)
+#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS		(1 << 19)
+#define MXC_CCM_CLPCR_WB_CORE_AT_LPM			(1 << 17)
+#define MXC_CCM_CLPCR_WB_PER_AT_LPM			(1 << 17)
+#define MXC_CCM_CLPCR_COSC_PWRDOWN			(1 << 11)
+#define MXC_CCM_CLPCR_STBY_COUNT_MASK			(0x3 << 9)
+#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET			(9)
+#define MXC_CCM_CLPCR_VSTBY				(1 << 8)
+#define MXC_CCM_CLPCR_DIS_REF_OSC			(1 << 7)
+#define MXC_CCM_CLPCR_SBYOS				(1 << 6)
+#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM		(1 << 5)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK			(0x3 << 3)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET		(3)
+#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY		(1 << 2)
+#define MXC_CCM_CLPCR_LPM_MASK				(0x3)
+#define MXC_CCM_CLPCR_LPM_OFFSET			(0)
+
+/* Define the bits in register CISR */
+#define MXC_CCM_CISR_ARM_PODF_LOADED			(1 << 26)
+#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED		(1 << 23)
+#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED		(1 << 22)
+#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED		(1 << 21)
+#define MXC_CCM_CISR_AHB_PODF_LOADED			(1 << 20)
+#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED		(1 << 19)
+#define MXC_CCM_CISR_AXI_PODF_LOADED			(1 << 17)
+#define MXC_CCM_CISR_COSC_READY				(1 << 6)
+#define MXC_CCM_CISR_LRF_PLL				(1)
+
+/* Define the bits in register CIMR */
+#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED		(1 << 26)
+#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED		(1 << 23)
+#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED		(1 << 22)
+#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED		(1 << 21)
+#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED		(1 << 20)
+#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED	(1 << 22)
+#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED		(1 << 17)
+#define MXC_CCM_CIMR_MASK_COSC_READY			(1 << 6)
+#define MXC_CCM_CIMR_MASK_LRF_PLL			(1)
+
+/* Define the bits in register CCOSR */
+#define MXC_CCM_CCOSR_CKO2_EN_OFFSET			(1 << 24)
+#define MXC_CCM_CCOSR_CKO2_DIV_MASK			(0x7 << 21)
+#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET			(21)
+#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET			(16)
+#define MXC_CCM_CCOSR_CKO2_SEL_MASK			(0x1F << 16)
+#define MXC_CCM_CCOSR_CKOL_EN				(0x1 << 7)
+#define MXC_CCM_CCOSR_CKOL_DIV_MASK			(0x7 << 4)
+#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET			(4)
+#define MXC_CCM_CCOSR_CKOL_SEL_MASK			(0xF)
+#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET			(0)
+
+/* Define the bits in registers CGPR */
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE		(1 << 4)
+#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS			(1 << 2)
+#define MXC_CCM_CGPR_PMIC_DELAY_SCALER			(1)
+
+#endif				/* __ARCH_ARM_MACH_MX6_CRM_REGS_H__ */
diff --git a/arch/arm/mach-imx/include/mach/devices-imx51.h b/arch/arm/mach-imx/include/mach/devices-imx51.h
index 27fcaa2c43..9ad6476aa0 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx51.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx51.h
@@ -76,7 +76,7 @@ static inline struct device_d *imx51_add_nand(struct imx_nand_platform_data *pda
 	memcpy(dev->resource, res, sizeof(struct resource) * ARRAY_SIZE(res));
 	dev->num_resources = ARRAY_SIZE(res);
 	strcpy(dev->name, "imx_nand");
-	dev->id = -1;
+	dev->id = DEVICE_ID_DYNAMIC;
 	dev->platform_data = pdata;
 
 	register_device(dev);
diff --git a/arch/arm/mach-imx/include/mach/devices-imx53.h b/arch/arm/mach-imx/include/mach/devices-imx53.h
index 1fc2417afd..a9fe454d39 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx53.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx53.h
@@ -75,7 +75,7 @@ static inline struct device_d *imx53_add_nand(struct imx_nand_platform_data *pda
 	memcpy(dev->resource, res, sizeof(struct resource) * ARRAY_SIZE(res));
 	dev->num_resources = ARRAY_SIZE(res);
 	strcpy(dev->name, "imx_nand");
-	dev->id = -1;
+	dev->id = DEVICE_ID_DYNAMIC;
 	dev->platform_data = pdata;
 
 	register_device(dev);
diff --git a/arch/arm/mach-imx/include/mach/devices-imx6.h b/arch/arm/mach-imx/include/mach/devices-imx6.h
new file mode 100644
index 0000000000..e4a72accd6
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/devices-imx6.h
@@ -0,0 +1,46 @@
+#include <mach/devices.h>
+
+static inline struct device_d *imx6_add_uart0(void)
+{
+	return imx_add_uart((void *)MX6_UART1_BASE_ADDR, 0);
+}
+
+static inline struct device_d *imx6_add_uart1(void)
+{
+	return imx_add_uart((void *)MX6_UART2_BASE_ADDR, 1);
+}
+
+static inline struct device_d *imx6_add_uart2(void)
+{
+	return imx_add_uart((void *)MX6_UART3_BASE_ADDR, 2);
+}
+
+static inline struct device_d *imx6_add_uart3(void)
+{
+	return imx_add_uart((void *)MX6_UART4_BASE_ADDR, 3);
+}
+
+static inline struct device_d *imx6_add_mmc0(struct esdhc_platform_data *pdata)
+{
+	return imx_add_esdhc((void *)MX6_USDHC1_BASE_ADDR, 0, pdata);
+}
+
+static inline struct device_d *imx6_add_mmc1(struct esdhc_platform_data *pdata)
+{
+	return imx_add_esdhc((void *)MX6_USDHC2_BASE_ADDR, 1, pdata);
+}
+
+static inline struct device_d *imx6_add_mmc2(struct esdhc_platform_data *pdata)
+{
+	return imx_add_esdhc((void *)MX6_USDHC3_BASE_ADDR, 2, pdata);
+}
+
+static inline struct device_d *imx6_add_mmc3(struct esdhc_platform_data *pdata)
+{
+	return imx_add_esdhc((void *)MX6_USDHC4_BASE_ADDR, 3, pdata);
+}
+
+static inline struct device_d *imx6_add_fec(struct fec_platform_data *pdata)
+{
+	return imx_add_fec((void *)MX6_ENET_BASE_ADDR, pdata);
+}
diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h
index 8ff04fbc81..99f301205c 100644
--- a/arch/arm/mach-imx/include/mach/generic.h
+++ b/arch/arm/mach-imx/include/mach/generic.h
@@ -3,9 +3,6 @@ int imx_silicon_revision(void);
 #define IMX27_CHIP_REVISION_1_0   0
 #define IMX27_CHIP_REVISION_2_0   1
 
-#define IMX35_CHIP_REVISION_1_0   0x10
-#define IMX35_CHIP_REVISION_2_0   0x20
-
 u64 imx_uid(void);
 
 
@@ -57,5 +54,11 @@ u64 imx_uid(void);
 #define cpu_is_mx53()	(0)
 #endif
 
+#ifdef CONFIG_ARCH_IMX6
+#define cpu_is_mx6()	(1)
+#else
+#define cpu_is_mx6()	(0)
+#endif
+
 #define cpu_is_mx23()	(0)
 #define cpu_is_mx28()	(0)
diff --git a/arch/arm/mach-imx/include/mach/imx-regs.h b/arch/arm/mach-imx/include/mach/imx-regs.h
index 789397efcb..82c7bacbc9 100644
--- a/arch/arm/mach-imx/include/mach/imx-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx-regs.h
@@ -55,6 +55,8 @@
 # include <mach/imx51-regs.h>
 #elif defined CONFIG_ARCH_IMX53
 # include <mach/imx53-regs.h>
+#elif defined CONFIG_ARCH_IMX6
+# include <mach/imx6-regs.h>
 #else
 # error "unknown i.MX soc type"
 #endif
@@ -107,7 +109,15 @@
 
 /* silicon revisions  */
 #define IMX_CHIP_REV_1_0	0x10
+#define IMX_CHIP_REV_1_1	0x11
+#define IMX_CHIP_REV_1_2	0x12
+#define IMX_CHIP_REV_1_3	0x13
 #define IMX_CHIP_REV_2_0	0x20
 #define IMX_CHIP_REV_2_1	0x21
+#define IMX_CHIP_REV_2_2	0x22
+#define IMX_CHIP_REV_2_3	0x23
+#define IMX_CHIP_REV_3_0	0x30
+#define IMX_CHIP_REV_3_1	0x31
+#define IMX_CHIP_REV_3_2	0x32
 
 #endif				/* _IMX_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx5.h b/arch/arm/mach-imx/include/mach/imx5.h
index c33f75e9a4..4c19d28001 100644
--- a/arch/arm/mach-imx/include/mach/imx5.h
+++ b/arch/arm/mach-imx/include/mach/imx5.h
@@ -1,8 +1,8 @@
 #ifndef __MACH_MX5_H
 #define __MACH_MX5_H
 
+void imx51_init_lowlevel(unsigned int cpufreq_mhz);
 void imx53_init_lowlevel(unsigned int cpufreq_mhz);
-void imx51_init_lowlevel(void);
 void imx5_setup_pll(void __iomem *base, int freq, u32 op, u32 mfd, u32 mfn);
 void imx5_init_lowlevel(void);
 
diff --git a/arch/arm/mach-imx/include/mach/imx51-regs.h b/arch/arm/mach-imx/include/mach/imx51-regs.h
index 90e81cb6ff..3eb0a1f894 100644
--- a/arch/arm/mach-imx/include/mach/imx51-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx51-regs.h
@@ -130,17 +130,4 @@
 #define MX51_CS4_BASE_ADDR		0xCC000000
 #define MX51_CS5_BASE_ADDR		0xCE000000
 
-/* silicon revisions specific to i.MX51 */
-#define MX51_CHIP_REV_1_0	0x10
-#define MX51_CHIP_REV_1_1	0x11
-#define MX51_CHIP_REV_1_2	0x12
-#define MX51_CHIP_REV_1_3	0x13
-#define MX51_CHIP_REV_2_0	0x20
-#define MX51_CHIP_REV_2_1	0x21
-#define MX51_CHIP_REV_2_2	0x22
-#define MX51_CHIP_REV_2_3	0x23
-#define MX51_CHIP_REV_3_0	0x30
-#define MX51_CHIP_REV_3_1	0x31
-#define MX51_CHIP_REV_3_2	0x32
-
 #endif /* __MACH_IMX51_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx6-anadig.h b/arch/arm/mach-imx/include/mach/imx6-anadig.h
new file mode 100644
index 0000000000..5a1b36ab04
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx6-anadig.h
@@ -0,0 +1,721 @@
+/*
+ * Freescale ANADIG Register Definitions
+ *
+ * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#ifndef __ARCH_ARM___ANADIG_H
+#define __ARCH_ARM___ANADIG_H
+
+#define HW_ANADIG_PLL_SYS	(0x00000000)
+#define HW_ANADIG_PLL_SYS_SET	(0x00000004)
+#define HW_ANADIG_PLL_SYS_CLR	(0x00000008)
+#define HW_ANADIG_PLL_SYS_TOG	(0x0000000c)
+
+#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
+#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
+#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
+#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
+#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
+#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v)  (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
+#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_SYS_DIV_SELECT      0
+#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
+#define BF_ANADIG_PLL_SYS_DIV_SELECT(v)  (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
+
+#define HW_ANADIG_USB1_PLL_480_CTRL	(0x00000010)
+#define HW_ANADIG_USB1_PLL_480_CTRL_SET	(0x00000014)
+#define HW_ANADIG_USB1_PLL_480_CTRL_CLR	(0x00000018)
+#define HW_ANADIG_USB1_PLL_480_CTRL_TOG	(0x0000001c)
+
+#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
+#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC      14
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v)  (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
+#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
+#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
+#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
+#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0      2
+#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
+#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v)  (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
+#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT      0
+#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
+#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v)  (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
+
+#define HW_ANADIG_USB2_PLL_480_CTRL	(0x00000020)
+#define HW_ANADIG_USB2_PLL_480_CTRL_SET	(0x00000024)
+#define HW_ANADIG_USB2_PLL_480_CTRL_CLR	(0x00000028)
+#define HW_ANADIG_USB2_PLL_480_CTRL_TOG	(0x0000002c)
+
+#define BM_ANADIG_USB2_PLL_480_CTRL_LOCK 0x80000000
+#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
+#define BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC      14
+#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(v)  (((v) << 14) & BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
+#define BM_ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
+#define BM_ANADIG_USB2_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_CP 0x00000400
+#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_CP 0x00000200
+#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_LF 0x00000100
+#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_LF 0x00000080
+#define BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
+#define BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0      2
+#define BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0 0x0000001C
+#define BF_ANADIG_USB2_PLL_480_CTRL_CONTROL0(v)  (((v) << 2) & BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0)
+#define BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT      0
+#define BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT 0x00000003
+#define BF_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT(v)  (((v) << 0) & BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT)
+
+#define HW_ANADIG_PLL_528	(0x00000030)
+#define HW_ANADIG_PLL_528_SET	(0x00000034)
+#define HW_ANADIG_PLL_528_CLR	(0x00000038)
+#define HW_ANADIG_PLL_528_TOG	(0x0000003c)
+
+#define BM_ANADIG_PLL_528_LOCK 0x80000000
+#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_528_BYPASS 0x00010000
+#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v)  (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_528_ENABLE 0x00002000
+#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_528_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_528_HALF_LF 0x00000080
+#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
+
+#define HW_ANADIG_PLL_528_SS	(0x00000040)
+
+#define BP_ANADIG_PLL_528_SS_STOP      16
+#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
+#define BF_ANADIG_PLL_528_SS_STOP(v) (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
+#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
+#define BP_ANADIG_PLL_528_SS_STEP      0
+#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
+#define BF_ANADIG_PLL_528_SS_STEP(v)  (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
+
+#define HW_ANADIG_PLL_528_NUM	(0x00000050)
+
+#define BP_ANADIG_PLL_528_NUM_A      0
+#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
+#define BF_ANADIG_PLL_528_NUM_A(v)  (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
+
+#define HW_ANADIG_PLL_528_DENOM	(0x00000060)
+
+#define BP_ANADIG_PLL_528_DENOM_B      0
+#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
+#define BF_ANADIG_PLL_528_DENOM_B(v)  (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
+
+#define HW_ANADIG_PLL_AUDIO	(0x00000070)
+#define HW_ANADIG_PLL_AUDIO_SET	(0x00000074)
+#define HW_ANADIG_PLL_AUDIO_CLR	(0x00000078)
+#define HW_ANADIG_PLL_AUDIO_TOG	(0x0000007c)
+
+#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
+#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
+#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT      19
+#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
+#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v)  (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
+#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v)  (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
+#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_AUDIO_DIV_SELECT      0
+#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
+#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v)  (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
+
+#define HW_ANADIG_PLL_AUDIO_NUM	(0x00000080)
+
+#define BP_ANADIG_PLL_AUDIO_NUM_A      0
+#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
+#define BF_ANADIG_PLL_AUDIO_NUM_A(v)  (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
+
+#define HW_ANADIG_PLL_AUDIO_DENOM	(0x00000090)
+
+#define BP_ANADIG_PLL_AUDIO_DENOM_B      0
+#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
+#define BF_ANADIG_PLL_AUDIO_DENOM_B(v)  (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
+
+#define HW_ANADIG_PLL_VIDEO	(0x000000a0)
+#define HW_ANADIG_PLL_VIDEO_SET	(0x000000a4)
+#define HW_ANADIG_PLL_VIDEO_CLR	(0x000000a8)
+#define HW_ANADIG_PLL_VIDEO_TOG	(0x000000ac)
+
+#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
+#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
+#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT      19
+#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
+#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v)  (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
+#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
+#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v)  (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
+#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_VIDEO_DIV_SELECT      0
+#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
+#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v)  (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
+
+#define HW_ANADIG_PLL_VIDEO_NUM	(0x000000b0)
+
+#define BP_ANADIG_PLL_VIDEO_NUM_A      0
+#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
+#define BF_ANADIG_PLL_VIDEO_NUM_A(v)  (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
+
+#define HW_ANADIG_PLL_VIDEO_DENOM	(0x000000c0)
+
+#define BP_ANADIG_PLL_VIDEO_DENOM_B      0
+#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
+#define BF_ANADIG_PLL_VIDEO_DENOM_B(v)  (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
+
+#define HW_ANADIG_PLL_MLB	(0x000000d0)
+#define HW_ANADIG_PLL_MLB_SET	(0x000000d4)
+#define HW_ANADIG_PLL_MLB_CLR	(0x000000d8)
+#define HW_ANADIG_PLL_MLB_TOG	(0x000000dc)
+
+#define BM_ANADIG_PLL_MLB_LOCK 0x80000000
+#define BP_ANADIG_PLL_MLB_MLB_FLT_RES_SEL      26
+#define BM_ANADIG_PLL_MLB_MLB_FLT_RES_SEL 0x1C000000
+#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_SEL(v)  (((v) << 26) & BM_ANADIG_PLL_MLB_MLB_FLT_RES_SEL)
+#define BP_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG      23
+#define BM_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG 0x03800000
+#define BF_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG(v)  (((v) << 23) & BM_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG)
+#define BP_ANADIG_PLL_MLB_VDDD_DELAY_CFG      20
+#define BM_ANADIG_PLL_MLB_VDDD_DELAY_CFG 0x00700000
+#define BF_ANADIG_PLL_MLB_VDDD_DELAY_CFG(v)  (((v) << 20) & BM_ANADIG_PLL_MLB_VDDD_DELAY_CFG)
+#define BP_ANADIG_PLL_MLB_VDDA_DELAY_CFG      17
+#define BM_ANADIG_PLL_MLB_VDDA_DELAY_CFG 0x000E0000
+#define BF_ANADIG_PLL_MLB_VDDA_DELAY_CFG(v)  (((v) << 17) & BM_ANADIG_PLL_MLB_VDDA_DELAY_CFG)
+#define BM_ANADIG_PLL_MLB_BYPASS 0x00010000
+#define BP_ANADIG_PLL_MLB_PHASE_SEL      12
+#define BM_ANADIG_PLL_MLB_PHASE_SEL 0x00003000
+#define BF_ANADIG_PLL_MLB_PHASE_SEL(v)  (((v) << 12) & BM_ANADIG_PLL_MLB_PHASE_SEL)
+#define BM_ANADIG_PLL_MLB_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_MLB_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_MLB_HALF_CP 0x00000200
+
+#define HW_ANADIG_PLL_ENET	(0x000000e0)
+#define HW_ANADIG_PLL_ENET_SET	(0x000000e4)
+#define HW_ANADIG_PLL_ENET_CLR	(0x000000e8)
+#define HW_ANADIG_PLL_ENET_TOG	(0x000000ec)
+
+#define BM_ANADIG_PLL_ENET_LOCK 0x80000000
+#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
+#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
+#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
+#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v)  (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
+#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_ENET_DIV_SELECT      0
+#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
+#define BF_ANADIG_PLL_ENET_DIV_SELECT(v)  (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
+
+#define HW_ANADIG_PFD_480	(0x000000f0)
+#define HW_ANADIG_PFD_480_SET	(0x000000f4)
+#define HW_ANADIG_PFD_480_CLR	(0x000000f8)
+#define HW_ANADIG_PFD_480_TOG	(0x000000fc)
+
+#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
+#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
+#define BP_ANADIG_PFD_480_PFD3_FRAC      24
+#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
+#define BF_ANADIG_PFD_480_PFD3_FRAC(v)  (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
+#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
+#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
+#define BP_ANADIG_PFD_480_PFD2_FRAC      16
+#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
+#define BF_ANADIG_PFD_480_PFD2_FRAC(v)  (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
+#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
+#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
+#define BP_ANADIG_PFD_480_PFD1_FRAC      8
+#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
+#define BF_ANADIG_PFD_480_PFD1_FRAC(v)  (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
+#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
+#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
+#define BP_ANADIG_PFD_480_PFD0_FRAC      0
+#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
+#define BF_ANADIG_PFD_480_PFD0_FRAC(v)  (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
+
+#define HW_ANADIG_PFD_528	(0x00000100)
+#define HW_ANADIG_PFD_528_SET	(0x00000104)
+#define HW_ANADIG_PFD_528_CLR	(0x00000108)
+#define HW_ANADIG_PFD_528_TOG	(0x0000010c)
+
+#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
+#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
+#define BP_ANADIG_PFD_528_PFD3_FRAC      24
+#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
+#define BF_ANADIG_PFD_528_PFD3_FRAC(v)  (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
+#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
+#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
+#define BP_ANADIG_PFD_528_PFD2_FRAC      16
+#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
+#define BF_ANADIG_PFD_528_PFD2_FRAC(v)  (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
+#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
+#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
+#define BP_ANADIG_PFD_528_PFD1_FRAC      8
+#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
+#define BF_ANADIG_PFD_528_PFD1_FRAC(v)  (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
+#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
+#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
+#define BP_ANADIG_PFD_528_PFD0_FRAC      0
+#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
+#define BF_ANADIG_PFD_528_PFD0_FRAC(v)  (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
+
+#define HW_ANADIG_REG_1P1	(0x00000110)
+#define HW_ANADIG_REG_1P1_SET	(0x00000114)
+#define HW_ANADIG_REG_1P1_CLR	(0x00000118)
+#define HW_ANADIG_REG_1P1_TOG	(0x0000011c)
+
+#define BM_ANADIG_REG_1P1_OK_VDD1P1 0x00020000
+#define BM_ANADIG_REG_1P1_BO_VDD1P1 0x00010000
+#define BP_ANADIG_REG_1P1_OUTPUT_TRG      8
+#define BM_ANADIG_REG_1P1_OUTPUT_TRG 0x00001F00
+#define BF_ANADIG_REG_1P1_OUTPUT_TRG(v)  (((v) << 8) & BM_ANADIG_REG_1P1_OUTPUT_TRG)
+#define BP_ANADIG_REG_1P1_BO_OFFSET      4
+#define BM_ANADIG_REG_1P1_BO_OFFSET 0x00000070
+#define BF_ANADIG_REG_1P1_BO_OFFSET(v)  (((v) << 4) & BM_ANADIG_REG_1P1_BO_OFFSET)
+#define BM_ANADIG_REG_1P1_ENABLE_PULLDOWN 0x00000008
+#define BM_ANADIG_REG_1P1_ENABLE_ILIMIT 0x00000004
+#define BM_ANADIG_REG_1P1_ENABLE_BO 0x00000002
+#define BM_ANADIG_REG_1P1_ENABLE_LINREG 0x00000001
+
+#define HW_ANADIG_REG_3P0	(0x00000120)
+#define HW_ANADIG_REG_3P0_SET	(0x00000124)
+#define HW_ANADIG_REG_3P0_CLR	(0x00000128)
+#define HW_ANADIG_REG_3P0_TOG	(0x0000012c)
+
+#define BM_ANADIG_REG_3P0_OK_VDD3P0 0x00020000
+#define BM_ANADIG_REG_3P0_BO_VDD3P0 0x00010000
+#define BP_ANADIG_REG_3P0_OUTPUT_TRG      8
+#define BM_ANADIG_REG_3P0_OUTPUT_TRG 0x00001F00
+#define BF_ANADIG_REG_3P0_OUTPUT_TRG(v)  (((v) << 8) & BM_ANADIG_REG_3P0_OUTPUT_TRG)
+#define BM_ANADIG_REG_3P0_VBUS_SEL 0x00000080
+#define BP_ANADIG_REG_3P0_BO_OFFSET      4
+#define BM_ANADIG_REG_3P0_BO_OFFSET 0x00000070
+#define BF_ANADIG_REG_3P0_BO_OFFSET(v)  (((v) << 4) & BM_ANADIG_REG_3P0_BO_OFFSET)
+#define BM_ANADIG_REG_3P0_ENABLE_ILIMIT 0x00000004
+#define BM_ANADIG_REG_3P0_ENABLE_BO 0x00000002
+#define BM_ANADIG_REG_3P0_ENABLE_LINREG 0x00000001
+
+#define HW_ANADIG_REG_2P5	(0x00000130)
+#define HW_ANADIG_REG_2P5_SET	(0x00000134)
+#define HW_ANADIG_REG_2P5_CLR	(0x00000138)
+#define HW_ANADIG_REG_2P5_TOG	(0x0000013c)
+
+#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x00040000
+#define BM_ANADIG_REG_2P5_OK_VDD2P5 0x00020000
+#define BM_ANADIG_REG_2P5_BO_VDD2P5 0x00010000
+#define BP_ANADIG_REG_2P5_OUTPUT_TRG      8
+#define BM_ANADIG_REG_2P5_OUTPUT_TRG 0x00001F00
+#define BF_ANADIG_REG_2P5_OUTPUT_TRG(v)  (((v) << 8) & BM_ANADIG_REG_2P5_OUTPUT_TRG)
+#define BP_ANADIG_REG_2P5_BO_OFFSET      4
+#define BM_ANADIG_REG_2P5_BO_OFFSET 0x00000070
+#define BF_ANADIG_REG_2P5_BO_OFFSET(v)  (((v) << 4) & BM_ANADIG_REG_2P5_BO_OFFSET)
+#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x00000008
+#define BM_ANADIG_REG_2P5_ENABLE_ILIMIT 0x00000004
+#define BM_ANADIG_REG_2P5_ENABLE_BO 0x00000002
+#define BM_ANADIG_REG_2P5_ENABLE_LINREG 0x00000001
+
+#define HW_ANADIG_REG_CORE	(0x00000140)
+#define HW_ANADIG_REG_CORE_SET	(0x00000144)
+#define HW_ANADIG_REG_CORE_CLR	(0x00000148)
+#define HW_ANADIG_REG_CORE_TOG	(0x0000014c)
+
+#define BM_ANADIG_REG_CORE_REF_SHIFT 0x80000000
+#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
+#define BP_ANADIG_REG_CORE_RAMP_RATE      27
+#define BM_ANADIG_REG_CORE_RAMP_RATE 0x18000000
+#define BF_ANADIG_REG_CORE_RAMP_RATE(v)  (((v) << 27) & BM_ANADIG_REG_CORE_RAMP_RATE)
+#define BP_ANADIG_REG_CORE_REG2_ADJ      23
+#define BM_ANADIG_REG_CORE_REG2_ADJ 0x07800000
+#define BF_ANADIG_REG_CORE_REG2_ADJ(v)  (((v) << 23) & BM_ANADIG_REG_CORE_REG2_ADJ)
+#define BP_ANADIG_REG_CORE_REG2_TRG      18
+#define BM_ANADIG_REG_CORE_REG2_TRG 0x007C0000
+#define BF_ANADIG_REG_CORE_REG2_TRG(v)  (((v) << 18) & BM_ANADIG_REG_CORE_REG2_TRG)
+#define BP_ANADIG_REG_CORE_REG1_ADJ      14
+#define BM_ANADIG_REG_CORE_REG1_ADJ 0x0003C000
+#define BF_ANADIG_REG_CORE_REG1_ADJ(v)  (((v) << 14) & BM_ANADIG_REG_CORE_REG1_ADJ)
+#define BP_ANADIG_REG_CORE_REG1_TRG      9
+#define BM_ANADIG_REG_CORE_REG1_TRG 0x00003E00
+#define BF_ANADIG_REG_CORE_REG1_TRG(v)  (((v) << 9) & BM_ANADIG_REG_CORE_REG1_TRG)
+#define BP_ANADIG_REG_CORE_REG0_ADJ      5
+#define BM_ANADIG_REG_CORE_REG0_ADJ 0x000001E0
+#define BF_ANADIG_REG_CORE_REG0_ADJ(v)  (((v) << 5) & BM_ANADIG_REG_CORE_REG0_ADJ)
+#define BP_ANADIG_REG_CORE_REG0_TRG      0
+#define BM_ANADIG_REG_CORE_REG0_TRG 0x0000001F
+#define BF_ANADIG_REG_CORE_REG0_TRG(v)  (((v) << 0) & BM_ANADIG_REG_CORE_REG0_TRG)
+
+#define HW_ANADIG_ANA_MISC0	(0x00000150)
+#define HW_ANADIG_ANA_MISC0_SET	(0x00000154)
+#define HW_ANADIG_ANA_MISC0_CLR	(0x00000158)
+#define HW_ANADIG_ANA_MISC0_TOG	(0x0000015c)
+
+#define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY      26
+#define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY 0x1C000000
+#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v)  (((v) << 26) & BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
+#define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL 0x02000000
+#define BP_ANADIG_ANA_MISC0_ANAMUX      21
+#define BM_ANADIG_ANA_MISC0_ANAMUX 0x01E00000
+#define BF_ANADIG_ANA_MISC0_ANAMUX(v)  (((v) << 21) & BM_ANADIG_ANA_MISC0_ANAMUX)
+#define BM_ANADIG_ANA_MISC0_ANAMUX_EN 0x00100000
+#define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH      18
+#define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 0x000C0000
+#define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v)  (((v) << 18) & BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
+#define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN 0x00020000
+#define BM_ANADIG_ANA_MISC0_OSC_XTALOK 0x00010000
+#define BP_ANADIG_ANA_MISC0_OSC_I      14
+#define BM_ANADIG_ANA_MISC0_OSC_I 0x0000C000
+#define BF_ANADIG_ANA_MISC0_OSC_I(v)  (((v) << 14) & BM_ANADIG_ANA_MISC0_OSC_I)
+#define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN 0x00002000
+#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x00001000
+#define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST      8
+#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 0x00000300
+#define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v)  (((v) << 8) & BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
+#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP 0x00000080
+#define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ      4
+#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x00000070
+#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v)  (((v) << 4) & BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
+#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
+#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER 0x00000004
+#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP 0x00000002
+#define BM_ANADIG_ANA_MISC0_REFTOP_PWD 0x00000001
+
+#define HW_ANADIG_ANA_MISC1	(0x00000160)
+#define HW_ANADIG_ANA_MISC1_SET	(0x00000164)
+#define HW_ANADIG_ANA_MISC1_CLR	(0x00000168)
+#define HW_ANADIG_ANA_MISC1_TOG	(0x0000016c)
+
+#define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO 0x80000000
+#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO 0x40000000
+#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO 0x20000000
+#define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN 0x00002000
+#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN 0x00001000
+#define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN 0x00000800
+#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN 0x00000400
+#define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL      5
+#define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 0x000003E0
+#define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v)  (((v) << 5) & BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
+#define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL      0
+#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0x0000001F
+#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v)  (((v) << 0) & BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
+
+#define HW_ANADIG_ANA_MISC2	(0x00000170)
+#define HW_ANADIG_ANA_MISC2_SET	(0x00000174)
+#define HW_ANADIG_ANA_MISC2_CLR	(0x00000178)
+#define HW_ANADIG_ANA_MISC2_TOG	(0x0000017c)
+
+#define BP_ANADIG_ANA_MISC2_CONTROL3      30
+#define BM_ANADIG_ANA_MISC2_CONTROL3 0xC0000000
+#define BF_ANADIG_ANA_MISC2_CONTROL3(v) (((v) << 30) & BM_ANADIG_ANA_MISC2_CONTROL3)
+#define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME      28
+#define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME 0x30000000
+#define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v)  (((v) << 28) & BM_ANADIG_ANA_MISC2_REG2_STEP_TIME)
+#define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME      26
+#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME 0x0C000000
+#define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v)  (((v) << 26) & BM_ANADIG_ANA_MISC2_REG1_STEP_TIME)
+#define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME      24
+#define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME 0x03000000
+#define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v)  (((v) << 24) & BM_ANADIG_ANA_MISC2_REG0_STEP_TIME)
+#define BM_ANADIG_ANA_MISC2_CONTROL2 0x00800000
+#define BM_ANADIG_ANA_MISC2_REG2_OK 0x00400000
+#define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO 0x00200000
+#define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS 0x00080000
+#define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET      16
+#define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET 0x00070000
+#define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v)  (((v) << 16) & BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
+#define BM_ANADIG_ANA_MISC2_CONTROL1 0x00008000
+#define BM_ANADIG_ANA_MISC2_REG1_OK 0x00004000
+#define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO 0x00002000
+#define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS 0x00000800
+#define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET      8
+#define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET 0x00000700
+#define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v)  (((v) << 8) & BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET)
+#define BM_ANADIG_ANA_MISC2_CONTROL0 0x00000080
+#define BM_ANADIG_ANA_MISC2_REG0_OK 0x00000040
+#define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO 0x00000020
+#define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS 0x00000008
+#define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET      0
+#define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0x00000007
+#define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v)  (((v) << 0) & BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
+
+#define HW_ANADIG_TEMPSENSE0	(0x00000180)
+#define HW_ANADIG_TEMPSENSE0_SET	(0x00000184)
+#define HW_ANADIG_TEMPSENSE0_CLR	(0x00000188)
+#define HW_ANADIG_TEMPSENSE0_TOG	(0x0000018c)
+
+#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE      20
+#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE 0xFFF00000
+#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) (((v) << 20) & BM_ANADIG_TEMPSENSE0_ALARM_VALUE)
+#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE      8
+#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE 0x000FFF00
+#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v)  (((v) << 8) & BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
+#define BM_ANADIG_TEMPSENSE0_TEST 0x00000040
+#define BP_ANADIG_TEMPSENSE0_VBGADJ      3
+#define BM_ANADIG_TEMPSENSE0_VBGADJ 0x00000038
+#define BF_ANADIG_TEMPSENSE0_VBGADJ(v)  (((v) << 3) & BM_ANADIG_TEMPSENSE0_VBGADJ)
+#define BM_ANADIG_TEMPSENSE0_FINISHED 0x00000004
+#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP 0x00000002
+#define BM_ANADIG_TEMPSENSE0_POWER_DOWN 0x00000001
+
+#define HW_ANADIG_TEMPSENSE1	(0x00000190)
+#define HW_ANADIG_TEMPSENSE1_SET	(0x00000194)
+#define HW_ANADIG_TEMPSENSE1_CLR	(0x00000198)
+#define HW_ANADIG_TEMPSENSE1_TOG	(0x0000019c)
+
+#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ      0
+#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ 0x0000FFFF
+#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v)  (((v) << 0) & BM_ANADIG_TEMPSENSE1_MEASURE_FREQ)
+
+#define HW_ANADIG_USB1_VBUS_DETECT	(0x000001a0)
+#define HW_ANADIG_USB1_VBUS_DETECT_SET	(0x000001a4)
+#define HW_ANADIG_USB1_VBUS_DETECT_CLR	(0x000001a8)
+#define HW_ANADIG_USB1_VBUS_DETECT_TOG	(0x000001ac)
+
+#define BM_ANADIG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000
+#define BM_ANADIG_USB1_VBUS_DETECT_CHARGE_VBUS 0x08000000
+#define BM_ANADIG_USB1_VBUS_DETECT_DISCHARGE_VBUS 0x04000000
+#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000
+#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_5VDETECT 0x00080000
+#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_TO_B 0x00040000
+#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE 0x00000080
+#define BM_ANADIG_USB1_VBUS_DETECT_AVALID_OVERRIDE 0x00000040
+#define BM_ANADIG_USB1_VBUS_DETECT_BVALID_OVERRIDE 0x00000020
+#define BM_ANADIG_USB1_VBUS_DETECT_SESSEND_OVERRIDE 0x00000010
+#define BM_ANADIG_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN 0x00000008
+#define BP_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH      0
+#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH 0x00000007
+#define BF_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH(v)  (((v) << 0) & BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH)
+
+#define HW_ANADIG_USB1_CHRG_DETECT	(0x000001b0)
+#define HW_ANADIG_USB1_CHRG_DETECT_SET	(0x000001b4)
+#define HW_ANADIG_USB1_CHRG_DETECT_CLR	(0x000001b8)
+#define HW_ANADIG_USB1_CHRG_DETECT_TOG	(0x000001bc)
+
+#define BM_ANADIG_USB1_CHRG_DETECT_BGR_BIAS 0x00800000
+#define BM_ANADIG_USB1_CHRG_DETECT_EN_B 0x00100000
+#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B 0x00080000
+#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CONTACT 0x00040000
+#define BM_ANADIG_USB1_CHRG_DETECT_FORCE_DETECT 0x00000001
+
+#define HW_ANADIG_USB1_VBUS_DET_STAT	(0x000001c0)
+#define HW_ANADIG_USB1_VBUS_DET_STAT_SET	(0x000001c4)
+#define HW_ANADIG_USB1_VBUS_DET_STAT_CLR	(0x000001c8)
+#define HW_ANADIG_USB1_VBUS_DET_STAT_TOG	(0x000001cc)
+
+#define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID 0x00000008
+#define BM_ANADIG_USB1_VBUS_DET_STAT_AVALID 0x00000004
+#define BM_ANADIG_USB1_VBUS_DET_STAT_BVALID 0x00000002
+#define BM_ANADIG_USB1_VBUS_DET_STAT_SESSEND 0x00000001
+
+#define HW_ANADIG_USB1_CHRG_DET_STAT	(0x000001d0)
+#define HW_ANADIG_USB1_CHRG_DET_STAT_SET	(0x000001d4)
+#define HW_ANADIG_USB1_CHRG_DET_STAT_CLR	(0x000001d8)
+#define HW_ANADIG_USB1_CHRG_DET_STAT_TOG	(0x000001dc)
+
+#define BM_ANADIG_USB1_CHRG_DET_STAT_DP_STATE 0x00000008
+#define BM_ANADIG_USB1_CHRG_DET_STAT_DM_STATE 0x00000004
+#define BM_ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED 0x00000002
+#define BM_ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT 0x00000001
+
+#define HW_ANADIG_USB1_LOOPBACK	(0x000001e0)
+#define HW_ANADIG_USB1_LOOPBACK_SET	(0x000001e4)
+#define HW_ANADIG_USB1_LOOPBACK_CLR	(0x000001e8)
+#define HW_ANADIG_USB1_LOOPBACK_TOG	(0x000001ec)
+
+#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST1 0x00000100
+#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST0 0x00000080
+#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HIZ 0x00000040
+#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN 0x00000020
+#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_LS_MODE 0x00000010
+#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HS_MODE 0x00000008
+#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 0x00000004
+#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST0 0x00000002
+#define BM_ANADIG_USB1_LOOPBACK_UTMI_TESTSTART 0x00000001
+
+#define HW_ANADIG_USB1_MISC	(0x000001f0)
+#define HW_ANADIG_USB1_MISC_SET	(0x000001f4)
+#define HW_ANADIG_USB1_MISC_CLR	(0x000001f8)
+#define HW_ANADIG_USB1_MISC_TOG	(0x000001fc)
+
+#define BM_ANADIG_USB1_MISC_EN_CLK_UTMI 0x40000000
+#define BM_ANADIG_USB1_MISC_RX_VPIN_FS 0x20000000
+#define BM_ANADIG_USB1_MISC_RX_VMIN_FS 0x10000000
+#define BM_ANADIG_USB1_MISC_RX_RXD_FS 0x08000000
+#define BM_ANADIG_USB1_MISC_RX_SQUELCH 0x04000000
+#define BM_ANADIG_USB1_MISC_RX_DISCON_DET 0x02000000
+#define BM_ANADIG_USB1_MISC_RX_HS_DATA 0x01000000
+#define BM_ANADIG_USB1_MISC_EN_DEGLITCH 0x00000002
+#define BM_ANADIG_USB1_MISC_HS_USE_EXTERNAL_R 0x00000001
+
+#define HW_ANADIG_USB2_VBUS_DETECT	(0x00000200)
+#define HW_ANADIG_USB2_VBUS_DETECT_SET	(0x00000204)
+#define HW_ANADIG_USB2_VBUS_DETECT_CLR	(0x00000208)
+#define HW_ANADIG_USB2_VBUS_DETECT_TOG	(0x0000020c)
+
+#define BM_ANADIG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000
+#define BM_ANADIG_USB2_VBUS_DETECT_CHARGE_VBUS 0x08000000
+#define BM_ANADIG_USB2_VBUS_DETECT_DISCHARGE_VBUS 0x04000000
+#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000
+#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_5VDETECT 0x00080000
+#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_TO_B 0x00040000
+#define BP_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH      0
+#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH 0x00000007
+#define BF_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH(v)  (((v) << 0) & BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH)
+
+#define HW_ANADIG_USB2_CHRG_DETECT	(0x00000210)
+#define HW_ANADIG_USB2_CHRG_DETECT_SET	(0x00000214)
+#define HW_ANADIG_USB2_CHRG_DETECT_CLR	(0x00000218)
+#define HW_ANADIG_USB2_CHRG_DETECT_TOG	(0x0000021c)
+
+#define BM_ANADIG_USB2_CHRG_DETECT_BGR_BIAS 0x00800000
+#define BM_ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
+#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
+#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CONTACT 0x00040000
+#define BM_ANADIG_USB2_CHRG_DETECT_FORCE_DETECT 0x00000001
+
+#define HW_ANADIG_USB2_VBUS_DET_STAT	(0x00000220)
+#define HW_ANADIG_USB2_VBUS_DET_STAT_SET	(0x00000224)
+#define HW_ANADIG_USB2_VBUS_DET_STAT_CLR	(0x00000228)
+#define HW_ANADIG_USB2_VBUS_DET_STAT_TOG	(0x0000022c)
+
+#define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID 0x00000008
+#define BM_ANADIG_USB2_VBUS_DET_STAT_AVALID 0x00000004
+#define BM_ANADIG_USB2_VBUS_DET_STAT_BVALID 0x00000002
+#define BM_ANADIG_USB2_VBUS_DET_STAT_SESSEND 0x00000001
+
+#define HW_ANADIG_USB2_CHRG_DET_STAT	(0x00000230)
+#define HW_ANADIG_USB2_CHRG_DET_STAT_SET	(0x00000234)
+#define HW_ANADIG_USB2_CHRG_DET_STAT_CLR	(0x00000238)
+#define HW_ANADIG_USB2_CHRG_DET_STAT_TOG	(0x0000023c)
+
+#define BM_ANADIG_USB2_CHRG_DET_STAT_DP_STATE 0x00000008
+#define BM_ANADIG_USB2_CHRG_DET_STAT_DM_STATE 0x00000004
+#define BM_ANADIG_USB2_CHRG_DET_STAT_CHRG_DETECTED 0x00000002
+#define BM_ANADIG_USB2_CHRG_DET_STAT_PLUG_CONTACT 0x00000001
+
+#define HW_ANADIG_USB2_LOOPBACK	(0x00000240)
+#define HW_ANADIG_USB2_LOOPBACK_SET	(0x00000244)
+#define HW_ANADIG_USB2_LOOPBACK_CLR	(0x00000248)
+#define HW_ANADIG_USB2_LOOPBACK_TOG	(0x0000024c)
+
+#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST1 0x00000100
+#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST0 0x00000080
+#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HIZ 0x00000040
+#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN 0x00000020
+#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_LS_MODE 0x00000010
+#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HS_MODE 0x00000008
+#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 0x00000004
+#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST0 0x00000002
+#define BM_ANADIG_USB2_LOOPBACK_UTMI_TESTSTART 0x00000001
+
+#define HW_ANADIG_USB2_MISC	(0x00000250)
+#define HW_ANADIG_USB2_MISC_SET	(0x00000254)
+#define HW_ANADIG_USB2_MISC_CLR	(0x00000258)
+#define HW_ANADIG_USB2_MISC_TOG	(0x0000025c)
+
+#define BM_ANADIG_USB2_MISC_EN_CLK_UTMI 0x40000000
+#define BM_ANADIG_USB2_MISC_RX_VPIN_FS 0x20000000
+#define BM_ANADIG_USB2_MISC_RX_VMIN_FS 0x10000000
+#define BM_ANADIG_USB2_MISC_RX_RXD_FS 0x08000000
+#define BM_ANADIG_USB2_MISC_RX_SQUELCH 0x04000000
+#define BM_ANADIG_USB2_MISC_RX_DISCON_DET 0x02000000
+#define BM_ANADIG_USB2_MISC_RX_HS_DATA 0x01000000
+#define BM_ANADIG_USB2_MISC_EN_DEGLITCH 0x00000002
+#define BM_ANADIG_USB2_MISC_HS_USE_EXTERNAL_R 0x00000001
+
+#define HW_ANADIG_DIGPROG	(0x00000260)
+
+#define BP_ANADIG_DIGPROG_MAJOR      8
+#define BM_ANADIG_DIGPROG_MAJOR 0x00FFFF00
+#define BF_ANADIG_DIGPROG_MAJOR(v)  (((v) << 8) & BM_ANADIG_DIGPROG_MAJOR)
+#define BP_ANADIG_DIGPROG_MINOR      0
+#define BM_ANADIG_DIGPROG_MINOR 0x000000FF
+#define BF_ANADIG_DIGPROG_MINOR(v)  (((v) << 0) & BM_ANADIG_DIGPROG_MINOR)
+#endif /* __ARCH_ARM___ANADIG_H */
diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h
new file mode 100644
index 0000000000..e62cc79a07
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx6-regs.h
@@ -0,0 +1,132 @@
+#ifndef __MACH_IMX6_REGS_H
+#define __MACH_IMX6_REGS_H
+
+#define IMX_TIM1_BASE	0x02098000
+#define IMX_WDT_BASE	0x020bc000
+#define IMX_IOMUXC_BASE 0x020e0000
+
+#define GPT_TCTL	0x00
+#define GPT_TPRER	0x04
+#define GPT_TCMP	0x10
+#define GPT_TCR		0x1c
+#define GPT_TCN		0x24
+#define GPT_TSTAT	0x08
+
+/* Part 2: Bitfields */
+#define TCTL_SWR	(1<<15)	/* Software reset */
+#define TCTL_FRR	(1<<9)	/* Freerun / restart */
+#define TCTL_CAP	(3<<6)	/* Capture Edge */
+#define TCTL_OM		(1<<5)	/* output mode */
+#define TCTL_IRQEN	(1<<4)	/* interrupt enable */
+#define TCTL_CLKSOURCE	(6)	/* Clock source bit position */
+#define TCTL_TEN	(1)	/* Timer enable */
+#define TPRER_PRES	(0xff)	/* Prescale */
+#define TSTAT_CAPT	(1<<1)	/* Capture event */
+#define TSTAT_COMP	(1)	/* Compare event */
+
+#define MX6_AIPS1_ARB_BASE_ADDR		0x02000000
+#define MX6_AIPS2_ARB_BASE_ADDR		0x02100000
+
+/* Defines for Blocks connected via AIPS (SkyBlue) */
+#define MX6_ATZ1_BASE_ADDR              MX6_AIPS1_ARB_BASE_ADDR
+#define MX6_ATZ2_BASE_ADDR              MX6_AIPS2_ARB_BASE_ADDR
+
+#define IPU_CTRL_BASE_ADDR	0x02400000
+
+/* slots 0,7 of SDMA reserved, therefore left unused in IPMUX3 */
+#define MX6_SPDIF_BASE_ADDR             (MX6_ATZ1_BASE_ADDR + 0x04000)
+#define MX6_ECSPI1_BASE_ADDR            (MX6_ATZ1_BASE_ADDR + 0x08000)
+#define MX6_ECSPI2_BASE_ADDR            (MX6_ATZ1_BASE_ADDR + 0x0C000)
+#define MX6_ECSPI3_BASE_ADDR            (MX6_ATZ1_BASE_ADDR + 0x10000)
+#define MX6_ECSPI4_BASE_ADDR            (MX6_ATZ1_BASE_ADDR + 0x14000)
+#define MX6_ECSPI5_BASE_ADDR            (MX6_ATZ1_BASE_ADDR + 0x18000)
+#define MX6_UART1_BASE_ADDR             (MX6_ATZ1_BASE_ADDR + 0x20000)
+#define MX6_ESAI1_BASE_ADDR             (MX6_ATZ1_BASE_ADDR + 0x24000)
+#define MX6_SSI1_BASE_ADDR              (MX6_ATZ1_BASE_ADDR + 0x28000)
+#define MX6_SSI2_BASE_ADDR              (MX6_ATZ1_BASE_ADDR + 0x2C000)
+#define MX6_SSI3_BASE_ADDR              (MX6_ATZ1_BASE_ADDR + 0x30000)
+#define MX6_ASRC_BASE_ADDR              (MX6_ATZ1_BASE_ADDR + 0x34000)
+#define MX6_SPBA_BASE_ADDR              (MX6_ATZ1_BASE_ADDR + 0x3C000)
+#define MX6_VPU_BASE_ADDR               (MX6_ATZ1_BASE_ADDR + 0x40000)
+
+/* ATZ#1- On Platform */
+#define MX6_AIPS1_ON_BASE_ADDR          (MX6_ATZ1_BASE_ADDR + 0x7C000)
+
+/* ATZ#1- Off Platform */
+#define MX6_AIPS1_OFF_BASE_ADDR         (MX6_ATZ1_BASE_ADDR + 0x80000)
+
+#define MX6_PWM1_BASE_ADDR              (MX6_AIPS1_OFF_BASE_ADDR + 0x0000)
+#define MX6_PWM2_BASE_ADDR              (MX6_AIPS1_OFF_BASE_ADDR + 0x4000)
+#define MX6_PWM3_BASE_ADDR              (MX6_AIPS1_OFF_BASE_ADDR + 0x8000)
+#define MX6_PWM4_BASE_ADDR              (MX6_AIPS1_OFF_BASE_ADDR + 0xC000)
+#define MX6_CAN1_BASE_ADDR              (MX6_AIPS1_OFF_BASE_ADDR + 0x10000)
+#define MX6_CAN2_BASE_ADDR              (MX6_AIPS1_OFF_BASE_ADDR + 0x14000)
+#define MX6_GPT_BASE_ADDR               (MX6_AIPS1_OFF_BASE_ADDR + 0x18000)
+#define MX6_GPIO1_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x1C000)
+#define MX6_GPIO2_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x20000)
+#define MX6_GPIO3_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x24000)
+#define MX6_GPIO4_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x28000)
+#define MX6_GPIO5_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x2C000)
+#define MX6_GPIO6_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x30000)
+#define MX6_GPIO7_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x34000)
+#define MX6_KPP_BASE_ADDR               (MX6_AIPS1_OFF_BASE_ADDR + 0x38000)
+#define MX6_WDOG1_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x3C000)
+#define MX6_WDOG2_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x40000)
+#define MX6_CCM_BASE_ADDR               (MX6_AIPS1_OFF_BASE_ADDR + 0x44000)
+#define MX6_ANATOP_BASE_ADDR            (MX6_AIPS1_OFF_BASE_ADDR + 0x48000)
+#define MX6_SNVS_BASE_ADDR              (MX6_AIPS1_OFF_BASE_ADDR + 0x4C000)
+#define MX6_EPIT1_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x50000)
+#define MX6_EPIT2_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x54000)
+#define MX6_SRC_BASE_ADDR               (MX6_AIPS1_OFF_BASE_ADDR + 0x58000)
+#define MX6_GPC_BASE_ADDR               (MX6_AIPS1_OFF_BASE_ADDR + 0x5C000)
+#define MX6_IOMUXC_BASE_ADDR            (MX6_AIPS1_OFF_BASE_ADDR + 0x60000)
+#define MX6_DCIC1_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x64000)
+#define MX6_DCIC2_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x68000)
+#define MX6_DMA_REQ_PORT_HOST_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x6C000)
+
+/* ATZ#2- On Platform */
+#define MX6_AIPS2_ON_BASE_ADDR          (MX6_ATZ2_BASE_ADDR + 0x7C000)
+
+/* ATZ#2- Off Platform */
+#define MX6_AIPS2_OFF_BASE_ADDR         (MX6_ATZ2_BASE_ADDR + 0x80000)
+
+/* ATZ#2  - Global enable (0) */
+#define MX6_CAAM_BASE_ADDR              (MX6_ATZ2_BASE_ADDR)
+#define MX6_ARM_BASE_ADDR		(MX6_ATZ2_BASE_ADDR + 0x40000)
+
+#define MX6_USBOH3_PL301_BASE_ADDR      (MX6_AIPS2_OFF_BASE_ADDR + 0x0000)
+#define MX6_USBOH3_USB_BASE_ADDR        (MX6_AIPS2_OFF_BASE_ADDR + 0x4000)
+#define MX6_OTG_BASE_ADDR		MX6_USBOH3_USB_BASE_ADDR
+#define MX6_ENET_BASE_ADDR              (MX6_AIPS2_OFF_BASE_ADDR + 0x8000)
+#define MX6_MLB_BASE_ADDR               (MX6_AIPS2_OFF_BASE_ADDR + 0xC000)
+
+#define MX6_USDHC1_BASE_ADDR            (MX6_AIPS2_OFF_BASE_ADDR + 0x10000)
+#define MX6_USDHC2_BASE_ADDR            (MX6_AIPS2_OFF_BASE_ADDR + 0x14000)
+#define MX6_USDHC3_BASE_ADDR            (MX6_AIPS2_OFF_BASE_ADDR + 0x18000)
+#define MX6_USDHC4_BASE_ADDR            (MX6_AIPS2_OFF_BASE_ADDR + 0x1C000)
+#define MX6_I2C1_BASE_ADDR              (MX6_AIPS2_OFF_BASE_ADDR + 0x20000)
+#define MX6_I2C2_BASE_ADDR              (MX6_AIPS2_OFF_BASE_ADDR + 0x24000)
+#define MX6_I2C3_BASE_ADDR              (MX6_AIPS2_OFF_BASE_ADDR + 0x28000)
+#define MX6_ROMCP_BASE_ADDR             (MX6_AIPS2_OFF_BASE_ADDR + 0x2C000)
+#define MX6_MMDC_P0_BASE_ADDR           (MX6_AIPS2_OFF_BASE_ADDR + 0x30000)
+#define MX6_MMDC_P1_BASE_ADDR           (MX6_AIPS2_OFF_BASE_ADDR + 0x34000)
+#define MX6_WEIM_BASE_ADDR              (MX6_AIPS2_OFF_BASE_ADDR + 0x38000)
+#define MX6_OCOTP_BASE_ADDR             (MX6_AIPS2_OFF_BASE_ADDR + 0x3C000)
+#define MX6_CSU_BASE_ADDR               (MX6_AIPS2_OFF_BASE_ADDR + 0x40000)
+#define MX6_IP2APB_PERFMON1_BASE_ADDR   (MX6_AIPS2_OFF_BASE_ADDR + 0x44000)
+#define MX6_IP2APB_PERFMON2_BASE_ADDR   (MX6_AIPS2_OFF_BASE_ADDR + 0x48000)
+#define MX6_IP2APB_PERFMON3_BASE_ADDR   (MX6_AIPS2_OFF_BASE_ADDR + 0x4C000)
+#define MX6_IP2APB_TZASC1_BASE_ADDR     (MX6_AIPS2_OFF_BASE_ADDR + 0x50000)
+#define MX6_IP2APB_TZASC2_BASE_ADDR     (MX6_AIPS2_OFF_BASE_ADDR + 0x54000)
+#define MX6_AUDMUX_BASE_ADDR            (MX6_AIPS2_OFF_BASE_ADDR + 0x58000)
+#define MX6_MIPI_CSI2_BASE_ADDR         (MX6_AIPS2_OFF_BASE_ADDR + 0x5C000)
+#define MX6_MIPI_DSI_BASE_ADDR          (MX6_AIPS2_OFF_BASE_ADDR + 0x60000)
+#define MX6_VDOA_BASE_ADDR              (MX6_AIPS2_OFF_BASE_ADDR + 0x64000)
+#define MX6_UART2_BASE_ADDR             (MX6_AIPS2_OFF_BASE_ADDR + 0x68000)
+#define MX6_UART3_BASE_ADDR             (MX6_AIPS2_OFF_BASE_ADDR + 0x6C000)
+#define MX6_UART4_BASE_ADDR             (MX6_AIPS2_OFF_BASE_ADDR + 0x70000)
+#define MX6_UART5_BASE_ADDR             (MX6_AIPS2_OFF_BASE_ADDR + 0x74000)
+#define MX6_IP2APB_USBPHY1_BASE_ADDR    (MX6_AIPS2_OFF_BASE_ADDR + 0x78000)
+#define MX6_IP2APB_USBPHY2_BASE_ADDR    (MX6_AIPS2_OFF_BASE_ADDR + 0x7C000)
+
+#endif /* __MACH_IMX6_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx6.h b/arch/arm/mach-imx/include/mach/imx6.h
new file mode 100644
index 0000000000..518cf98978
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx6.h
@@ -0,0 +1,6 @@
+#ifndef __MACH_IMX6_H
+#define __MACH_IMX6_H
+
+void imx6_init_lowlevel(void);
+
+#endif /* __MACH_IMX6_H */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx51.h b/arch/arm/mach-imx/include/mach/iomux-mx51.h
index 872072edd5..c7f5169a6a 100644
--- a/arch/arm/mach-imx/include/mach/iomux-mx51.h
+++ b/arch/arm/mach-imx/include/mach/iomux-mx51.h
@@ -1,354 +1,813 @@
 /*
- * Copyright (C) 2009 by Sascha Hauer <s.hauer@pengutronix.de>
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option, NO_PAD_CTRL) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
  *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
  */
 
 #ifndef __MACH_IOMUX_MX51_H__
 #define __MACH_IOMUX_MX51_H__
 
 #include <mach/iomux-v3.h>
-
-#define MX51_FEC_PAD_CTRL      (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
-
+#define __NA_	0x000
+
+
+/* Pad control groupings */
+#define MX51_UART_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
+				PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+#define MX51_I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
+				PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
+				PAD_CTL_HYS)
+#define MX51_ESDHC_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
+				PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
+				PAD_CTL_HYS)
+#define MX51_USBH1_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
+				PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
+				PAD_CTL_HYS | PAD_CTL_PUE)
+#define MX51_ECSPI_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_HYS | \
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
 #define MX51_SDHCI_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
-		PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
-		PAD_CTL_SRE_FAST | PAD_CTL_DVS)
+				PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
+				PAD_CTL_SRE_FAST | PAD_CTL_DVS)
+#define MX51_GPIO_PAD_CTRL	(PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
+
+#define MX51_PAD_CTRL_2		(PAD_CTL_PKE | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_3		(PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
+#define MX51_PAD_CTRL_4		(PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_5		(PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 
 /*
  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named
- * GPIO_<unit>_<num> see also iomux-v3.h
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
+ * See also iomux-v3.h
  */
 
-/*								  PAD    MUX   ALT INPSE PATH */
-#define MX51_PAD_EIM_DA0__EIM_DA0			IOMUX_PAD(0x7A8, 0x1C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA1__EIM_DA1			IOMUX_PAD(0x7A8, 0x20, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA2__EIM_DA2			IOMUX_PAD(0x7A8, 0x24, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA3__EIM_DA3			IOMUX_PAD(0x7A8, 0x28, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA4__EIM_DA4			IOMUX_PAD(0x7AC, 0x2C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA5__EIM_DA5			IOMUX_PAD(0x7AC, 0x30, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA6__EIM_DA6			IOMUX_PAD(0x7AC, 0x34, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA7__EIM_DA7			IOMUX_PAD(0x7AC, 0x38, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA8__EIM_DA8			IOMUX_PAD(0x7B0, 0x3C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA9__EIM_DA9			IOMUX_PAD(0x7B0, 0x40, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA10__EIM_DA10			IOMUX_PAD(0x7B0, 0x44, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA11__EIM_DA11			IOMUX_PAD(0x7B0, 0x48, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA12__EIM_DA12			IOMUX_PAD(0x7BC, 0x4C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA13__EIM_DA13			IOMUX_PAD(0x7BC, 0x50, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA14__EIM_DA14			IOMUX_PAD(0x7BC, 0x54, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA15__EIM_DA15			IOMUX_PAD(0x7BC, 0x58, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__EIM_D16			IOMUX_PAD(0x3F0, 0x5C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__EIM_D17			IOMUX_PAD(0x3F4, 0x60, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__EIM_D18			IOMUX_PAD(0x3F8, 0x64, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__EIM_D19			IOMUX_PAD(0x3FC, 0x68, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__EIM_D20			IOMUX_PAD(0x400, 0x6C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__EIM_D21			IOMUX_PAD(0x404, 0x70, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__EIM_D22			IOMUX_PAD(0x408, 0x74, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__EIM_D23			IOMUX_PAD(0x40C, 0x78, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__EIM_D24			IOMUX_PAD(0x410, 0x7C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__EIM_D25			IOMUX_PAD(0x414, 0x80, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__EIM_D26			IOMUX_PAD(0x418, 0x84, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__EIM_D27			IOMUX_PAD(0x41C, 0x88, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__EIM_D28			IOMUX_PAD(0x420, 0x8C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__EIM_D29			IOMUX_PAD(0x424, 0x90, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__EIM_D30			IOMUX_PAD(0x428, 0x94, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__EIM_D31			IOMUX_PAD(0x42C, 0x98, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A16__EIM_A16			IOMUX_PAD(0x430, 0x9C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A17__EIM_A17			IOMUX_PAD(0x434, 0xA0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A18__EIM_A18			IOMUX_PAD(0x438, 0xA4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A19__EIM_A19			IOMUX_PAD(0x43C, 0xA8, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX51_PAD_EIM_A20__EIM_A20			IOMUX_PAD(0x440, 0xAC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A20__GPIO2_14			IOMUX_PAD(0x440, 0xAC, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX51_PAD_EIM_A21__EIM_A21			IOMUX_PAD(0x444, 0xB0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A22__EIM_A22			IOMUX_PAD(0x448, 0xB4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A23__EIM_A23			IOMUX_PAD(0x44C, 0xB8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A24__EIM_A24			IOMUX_PAD(0x450, 0xBC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__EIM_A25			IOMUX_PAD(0x454, 0xC0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__EIM_A26			IOMUX_PAD(0x458, 0xC4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__EIM_A27			IOMUX_PAD(0x45C, 0xC8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB0__EIM_EB0			IOMUX_PAD(0x460, 0xCC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB1__EIM_EB1			IOMUX_PAD(0x464, 0xD0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX51_PAD_EIM_EB2__EIM_EB2			IOMUX_PAD(0x468, 0xD4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__FEC_MDIO			IOMUX_PAD(0x468, 0x0d4, 3, 0x954,   0, MX51_FEC_PAD_CTRL)
-
-#define MX51_PAD_EIM_EB3__EIM_EB3			IOMUX_PAD(0x46C, 0xD8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__FEC_RDATA1			IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c,   0, MX51_FEC_PAD_CTRL)
-
-#define MX51_PAD_EIM_OE__EIM_OE				IOMUX_PAD(0x470, 0xDC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS0__EIM_CS0			IOMUX_PAD(0x474, 0xE0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS1__EIM_CS1			IOMUX_PAD(0x478, 0xE4, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX51_PAD_EIM_CS2__EIM_CS2			IOMUX_PAD(0x47C, 0xE8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__FEC_RDATA2			IOMUX_PAD(0x47c, 0x0e8, 3, 0x960,   0, MX51_FEC_PAD_CTRL)
-
-#define MX51_PAD_EIM_CS3__EIM_CS3			IOMUX_PAD(0x480, 0xEC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__FEC_RDATA3			IOMUX_PAD(0x480, 0x0ec, 3, 0x964,   0, MX51_FEC_PAD_CTRL)
-
-#define MX51_PAD_EIM_CS4__EIM_CS4			IOMUX_PAD(0x484, 0xF0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__FEC_RX_ER			IOMUX_PAD(0x484, 0x0f0, 3, 0x970,   0, MX51_FEC_PAD_CTRL)
-
-#define MX51_PAD_EIM_CS5__EIM_CS5			IOMUX_PAD(0x488, 0xF4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__FEC_CRS			IOMUX_PAD(0x52C, 0xF4, 3, 0x950, 0, MX51_FEC_PAD_CTRL)
-
-#define MX51_PAD_EIM_DTACK__EIM_DTACK			IOMUX_PAD(0x48C, 0xF8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DTACK__GPIO2_31			IOMUX_PAD(0x48c, 0xf8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_LBA__EIM_LBA			IOMUX_PAD(0x494, 0xFC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CRE__EIM_CRE			IOMUX_PAD(0x4A0, 0x100, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__DRAM_CS1			IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__NANDF_WE_B			IOMUX_PAD(0x4E4, 0x108, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__NANDF_RE_B			IOMUX_PAD(0x4E8, 0x10C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_ALE__NANDF_ALE			IOMUX_PAD(0x4EC, 0x110, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CLE__NANDF_CLE			IOMUX_PAD(0x4F0, 0x114, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__NANDF_WP_B			IOMUX_PAD(0x4F4, 0x118, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__NANDF_RB0			IOMUX_PAD(0x4F8, 0x11C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__NANDF_RB1			IOMUX_PAD(0x4FC, 0x120, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX51_PAD_NANDF_RB2__NANDF_RB2			IOMUX_PAD(0x500, 0x124, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__FEC_COL			IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_FEC_PAD_CTRL)
-
-#define MX51_PAD_NANDF_RB3__NANDF_RB3			IOMUX_PAD(0x504, 0x128, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__FEC_RX_CLK			IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_FEC_PAD_CTRL)
+/* Raw pin modes without pad control */
+/*							  PAD    MUX ALT INPSE PATH PADCTRL */
+
+/* The same pins as above but with the default pad control values applied */
+#define MX51_PAD_EIM_D16__AUD4_RXFS		IOMUX_PAD(0x3f0, 0x05c, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__AUD5_TXD		IOMUX_PAD(0x3f0, 0x05c, 7, 0x8d8, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__EIM_D16		IOMUX_PAD(0x3f0, 0x05c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__GPIO2_0		IOMUX_PAD(0x3f0, 0x05c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__I2C1_SDA		IOMUX_PAD(0x3f0, 0x05c, 0x14, 0x9b4, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D16__UART2_CTS		IOMUX_PAD(0x3f0, 0x05c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D16__USBH2_DATA0		IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D17__AUD5_RXD		IOMUX_PAD(0x3f4, 0x060, 7, 0x8d4, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D17__EIM_D17		IOMUX_PAD(0x3f4, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D17__GPIO2_1		IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D17__UART2_RXD		IOMUX_PAD(0x3f4, 0x060, 3, 0x9ec, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D17__UART3_CTS		IOMUX_PAD(0x3f4, 0x060, 4, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D17__USBH2_DATA1		IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__AUD5_TXC		IOMUX_PAD(0x3f8, 0x064, 7, 0x8e4, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__EIM_D18		IOMUX_PAD(0x3f8, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__GPIO2_2		IOMUX_PAD(0x3f8, 0x064, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__UART2_TXD		IOMUX_PAD(0x3f8, 0x064, 3, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D18__UART3_RTS		IOMUX_PAD(0x3f8, 0x064, 4, 0x9f0, 1, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D18__USBH2_DATA2		IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__AUD4_RXC		IOMUX_PAD(0x3fc, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__AUD5_TXFS		IOMUX_PAD(0x3fc, 0x068, 7, 0x8e8, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__EIM_D19		IOMUX_PAD(0x3fc, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__GPIO2_3		IOMUX_PAD(0x3fc, 0x068, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__I2C1_SCL		IOMUX_PAD(0x3fc, 0x068, 0x14, 0x9b0, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D19__UART2_RTS		IOMUX_PAD(0x3fc, 0x068, 3, 0x9e8, 1, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D19__USBH2_DATA3		IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__AUD4_TXD		IOMUX_PAD(0x400, 0x06c, 5, 0x8c8, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__EIM_D20		IOMUX_PAD(0x400, 0x06c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__GPIO2_4		IOMUX_PAD(0x400, 0x06c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB	IOMUX_PAD(0x400, 0x06c, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__USBH2_DATA4		IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__AUD4_RXD		IOMUX_PAD(0x404, 0x070, 5, 0x8c4, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__EIM_D21		IOMUX_PAD(0x404, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__GPIO2_5		IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB	IOMUX_PAD(0x404, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__USBH2_DATA5		IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__AUD4_TXC		IOMUX_PAD(0x408, 0x074, 5, 0x8cc, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__EIM_D22		IOMUX_PAD(0x408, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__GPIO2_6		IOMUX_PAD(0x408, 0x074, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__USBH2_DATA6		IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__AUD4_TXFS		IOMUX_PAD(0x40c, 0x078, 5, 0x8d0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__EIM_D23		IOMUX_PAD(0x40c, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__GPIO2_7		IOMUX_PAD(0x40c, 0x078, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__SPDIF_OUT1		IOMUX_PAD(0x40c, 0x078, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__USBH2_DATA7		IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__AUD6_RXFS		IOMUX_PAD(0x410, 0x07c, 5, 0x8f8, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__EIM_D24		IOMUX_PAD(0x410, 0x07c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__GPIO2_8		IOMUX_PAD(0x410, 0x07c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__I2C2_SDA		IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D24__UART3_CTS		IOMUX_PAD(0x410, 0x07c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D24__USBOTG_DATA0		IOMUX_PAD(0x410, 0x07c, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D25__EIM_D25		IOMUX_PAD(0x414, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D25__KEY_COL6		IOMUX_PAD(0x414, 0x080, 1, 0x9c8, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART2_CTS		IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART3_RXD		IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D25__USBOTG_DATA1		IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D26__EIM_D26		IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D26__KEY_COL7		IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART2_RTS		IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART3_TXD		IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D26__USBOTG_DATA2		IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D27__AUD6_RXC		IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D27__EIM_D27		IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D27__GPIO2_9		IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D27__I2C2_SCL		IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D27__UART3_RTS		IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D27__USBOTG_DATA3		IOMUX_PAD(0x41c, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D28__AUD6_TXD		IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D28__EIM_D28		IOMUX_PAD(0x420, 0x08c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D28__KEY_ROW4		IOMUX_PAD(0x420, 0x08c, 1, 0x9d0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D28__USBOTG_DATA4		IOMUX_PAD(0x420, 0x08c, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__AUD6_RXD		IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__EIM_D29		IOMUX_PAD(0x424, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__KEY_ROW5		IOMUX_PAD(0x424, 0x090, 1, 0x9d4, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__USBOTG_DATA5		IOMUX_PAD(0x424, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__AUD6_TXC		IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__EIM_D30		IOMUX_PAD(0x428, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__KEY_ROW6		IOMUX_PAD(0x428, 0x094, 1, 0x9d8, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__USBOTG_DATA6		IOMUX_PAD(0x428, 0x094, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__AUD6_TXFS		IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__EIM_D31		IOMUX_PAD(0x42c, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__KEY_ROW7		IOMUX_PAD(0x42c, 0x098, 1, 0x9dc, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__USBOTG_DATA7		IOMUX_PAD(0x42c, 0x098, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A16__EIM_A16		IOMUX_PAD(0x430, 0x09c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A16__GPIO2_10		IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0		IOMUX_PAD(0x430, 0x09c, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A17__EIM_A17		IOMUX_PAD(0x434, 0x0a0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A17__GPIO2_11		IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1		IOMUX_PAD(0x434, 0x0a0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A18__BOOT_LPB0		IOMUX_PAD(0x438, 0x0a4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A18__EIM_A18		IOMUX_PAD(0x438, 0x0a4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A18__GPIO2_12		IOMUX_PAD(0x438, 0x0a4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A19__BOOT_LPB1		IOMUX_PAD(0x43c, 0x0a8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A19__EIM_A19		IOMUX_PAD(0x43c, 0x0a8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A19__GPIO2_13		IOMUX_PAD(0x43c, 0x0a8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A20__BOOT_UART_SRC0	IOMUX_PAD(0x440, 0x0ac, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A20__EIM_A20		IOMUX_PAD(0x440, 0x0ac, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A20__GPIO2_14		IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A21__BOOT_UART_SRC1	IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A21__EIM_A21		IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A21__GPIO2_15		IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A22__EIM_A22		IOMUX_PAD(0x448, 0x0b4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A22__GPIO2_16		IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A23__BOOT_HPN_EN		IOMUX_PAD(0x44c, 0x0b8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A23__EIM_A23		IOMUX_PAD(0x44c, 0x0b8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A23__GPIO2_17		IOMUX_PAD(0x44c, 0x0b8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A24__EIM_A24		IOMUX_PAD(0x450, 0x0bc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A24__GPIO2_18		IOMUX_PAD(0x450, 0x0bc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A24__USBH2_CLK		IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__DISP1_PIN4		IOMUX_PAD(0x454, 0x0c0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__EIM_A25		IOMUX_PAD(0x454, 0x0c0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__GPIO2_19		IOMUX_PAD(0x454, 0x0c0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__USBH2_DIR		IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__CSI1_DATA_EN		IOMUX_PAD(0x458, 0x0c4, 5, 0x9a0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__DISP2_EXT_CLK		IOMUX_PAD(0x458, 0x0c4, 6, 0x908, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__EIM_A26		IOMUX_PAD(0x458, 0x0c4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__GPIO2_20		IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__USBH2_STP		IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__CSI2_DATA_EN		IOMUX_PAD(0x45c, 0x0c8, 5, 0x99c, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__DISP1_PIN1		IOMUX_PAD(0x45c, 0x0c8, 6, 0x9a4, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__EIM_A27		IOMUX_PAD(0x45c, 0x0c8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__GPIO2_21		IOMUX_PAD(0x45c, 0x0c8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__USBH2_NXT		IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB0__EIM_EB0		IOMUX_PAD(0x460, 0x0cc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB1__EIM_EB1		IOMUX_PAD(0x464, 0x0d0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__AUD5_RXFS		IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__CSI1_D2		IOMUX_PAD(0x468, 0x0d4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__EIM_EB2		IOMUX_PAD(0x468, 0x0d4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__FEC_MDIO		(IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, 0) | \
+		MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
+		PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS))
+#define MX51_PAD_EIM_EB2__GPIO2_22		IOMUX_PAD(0x468, 0x0d4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__GPT_CMPOUT1		IOMUX_PAD(0x468, 0x0d4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__AUD5_RXC		IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__CSI1_D3		IOMUX_PAD(0x46c, 0x0d8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__EIM_EB3		IOMUX_PAD(0x46c, 0x0d8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__FEC_RDATA1		IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__GPIO2_23		IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__GPT_CMPOUT2		IOMUX_PAD(0x46c, 0x0d8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_OE__EIM_OE			IOMUX_PAD(0x470, 0x0dc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_OE__GPIO2_24		IOMUX_PAD(0x470, 0x0dc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS0__EIM_CS0		IOMUX_PAD(0x474, 0x0e0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS0__GPIO2_25		IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS1__EIM_CS1		IOMUX_PAD(0x478, 0x0e4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS1__GPIO2_26		IOMUX_PAD(0x478, 0x0e4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__AUD5_TXD		IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__CSI1_D4		IOMUX_PAD(0x47c, 0x0e8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__EIM_CS2		IOMUX_PAD(0x47c, 0x0e8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__FEC_RDATA2		IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__GPIO2_27		IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__USBOTG_STP		IOMUX_PAD(0x47c, 0x0e8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__AUD5_RXD		IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__CSI1_D5		IOMUX_PAD(0x480, 0x0ec, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__EIM_CS3		IOMUX_PAD(0x480, 0x0ec, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__FEC_RDATA3		IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__GPIO2_28		IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__USBOTG_NXT		IOMUX_PAD(0x480, 0x0ec, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__AUD5_TXC		IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__CSI1_D6		IOMUX_PAD(0x484, 0x0f0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__EIM_CS4		IOMUX_PAD(0x484, 0x0f0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__FEC_RX_ER		IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2)
+#define MX51_PAD_EIM_CS4__GPIO2_29		IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__USBOTG_CLK		IOMUX_PAD(0x484, 0x0f0, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__AUD5_TXFS		IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__CSI1_D7		IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK		IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__EIM_CS5		IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__FEC_CRS		IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2)
+#define MX51_PAD_EIM_CS5__GPIO2_30		IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__USBOTG_DIR		IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DTACK__EIM_DTACK		IOMUX_PAD(0x48c, 0x0f8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DTACK__GPIO2_31		IOMUX_PAD(0x48c, 0x0f8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_LBA__EIM_LBA		IOMUX_PAD(0x494, 0x0fc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_LBA__GPIO3_1		IOMUX_PAD(0x494, 0x0fc, 1, 0x978, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CRE__EIM_CRE		IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CRE__GPIO3_2		IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DRAM_CS1__DRAM_CS1		IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__GPIO3_3		IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__NANDF_WE_B		IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__PATA_DIOW		IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__SD3_DATA0		IOMUX_PAD(0x4e4, 0x108, 2, 0x93c, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__GPIO3_4		IOMUX_PAD(0x4e8, 0x10c, 3, 0x984, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__NANDF_RE_B		IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__PATA_DIOR		IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__SD3_DATA1		IOMUX_PAD(0x4e8, 0x10c, 2, 0x940, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_ALE__GPIO3_5		IOMUX_PAD(0x4ec, 0x110, 3, 0x988, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_ALE__NANDF_ALE		IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN	IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CLE__GPIO3_6		IOMUX_PAD(0x4f0, 0x114, 3, 0x98c, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CLE__NANDF_CLE		IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CLE__PATA_RESET_B	IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__GPIO3_7		IOMUX_PAD(0x4f4, 0x118, 3, 0x990, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__NANDF_WP_B		IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__PATA_DMACK		IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__SD3_DATA2		IOMUX_PAD(0x4f4, 0x118, 2, 0x944, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__ECSPI2_SS1		IOMUX_PAD(0x4f8, 0x11c, 5, 0x930, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__GPIO3_8		IOMUX_PAD(0x4f8, 0x11c, 3, 0x994, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__NANDF_RB0		IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__PATA_DMARQ		IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__SD3_DATA3		IOMUX_PAD(0x4f8, 0x11c, 2, 0x948, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__CSPI_MOSI		IOMUX_PAD(0x4fc, 0x120, 6, 0x91c, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__ECSPI2_RDY		IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__GPIO3_9		IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__NANDF_RB1		IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__PATA_IORDY		IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__SD4_CMD		IOMUX_PAD(0x4fc, 0x120, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__DISP2_WAIT		IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK		IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__FEC_COL		IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2)
+#define MX51_PAD_NANDF_RB2__GPIO3_10		IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__NANDF_RB2		IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__USBH3_H3_DP		IOMUX_PAD(0x500, 0x124, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__USBH3_NXT		IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__DISP1_WAIT		IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__ECSPI2_MISO		IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__FEC_RX_CLK		IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2)
+#define MX51_PAD_NANDF_RB3__GPIO3_11		IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__NANDF_RB3		IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__USBH3_CLK		IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__USBH3_H3_DM		IOMUX_PAD(0x504, 0x128, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_NAND__GPIO_NAND		IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_NAND__PATA_INTRQ		IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS0__GPIO3_16		IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS0__NANDF_CS0		IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS1__GPIO3_17		IOMUX_PAD(0x51c, 0x134, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS1__NANDF_CS1		IOMUX_PAD(0x51c, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__CSPI_SCLK		IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__FEC_TX_ER		IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_CS2__GPIO3_18		IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__NANDF_CS2		IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__PATA_CS_0		IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__SD4_CLK		IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
+#define MX51_PAD_NANDF_CS2__USBH3_H1_DP		IOMUX_PAD(0x520, 0x138, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__FEC_MDC		IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_CS3__GPIO3_19		IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__NANDF_CS3		IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__PATA_CS_1		IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__SD4_DAT0		IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__USBH3_H1_DM		IOMUX_PAD(0x524, 0x13c, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__FEC_TDATA1		IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_CS4__GPIO3_20		IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__NANDF_CS4		IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__PATA_DA_0		IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__SD4_DAT1		IOMUX_PAD(0x528, 0x140, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__USBH3_STP		IOMUX_PAD(0x528, 0x140, 7, 0xa24, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__FEC_TDATA2		IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_CS5__GPIO3_21		IOMUX_PAD(0x52c, 0x144, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__NANDF_CS5		IOMUX_PAD(0x52c, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__PATA_DA_1		IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__SD4_DAT2		IOMUX_PAD(0x52c, 0x144, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__USBH3_DIR		IOMUX_PAD(0x52c, 0x144, 7, 0xa1c, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__CSPI_SS3		IOMUX_PAD(0x530, 0x148, 7, 0x928, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__FEC_TDATA3		IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_CS6__GPIO3_22		IOMUX_PAD(0x530, 0x148, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__NANDF_CS6		IOMUX_PAD(0x530, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__PATA_DA_2		IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__SD4_DAT3		IOMUX_PAD(0x530, 0x148, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__FEC_TX_EN		IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_CS7__GPIO3_23		IOMUX_PAD(0x534, 0x14c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__NANDF_CS7		IOMUX_PAD(0x534, 0x14c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__SD3_CLK		IOMUX_PAD(0x534, 0x14c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
+#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0	IOMUX_PAD(0x538, 0x150, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK	IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4)
+#define MX51_PAD_NANDF_RDY_INT__GPIO3_24	IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT	IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__SD3_CMD		IOMUX_PAD(0x538, 0x150, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__ECSPI2_MOSI		IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__GPIO3_25		IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__NANDF_D15		IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__PATA_DATA15		IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__SD3_DAT7		IOMUX_PAD(0x53c, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__ECSPI2_SS3		IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__GPIO3_26		IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__NANDF_D14		IOMUX_PAD(0x540, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__PATA_DATA14		IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__SD3_DAT6		IOMUX_PAD(0x540, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__ECSPI2_SS2		IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__GPIO3_27		IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__NANDF_D13		IOMUX_PAD(0x544, 0x15c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__PATA_DATA13		IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__SD3_DAT5		IOMUX_PAD(0x544, 0x15c, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__ECSPI2_SS1		IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__GPIO3_28		IOMUX_PAD(0x548, 0x160, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__NANDF_D12		IOMUX_PAD(0x548, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__PATA_DATA12		IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__SD3_DAT4		IOMUX_PAD(0x548, 0x160, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__FEC_RX_DV		IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__GPIO3_29		IOMUX_PAD(0x54c, 0x164, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__NANDF_D11		IOMUX_PAD(0x54c, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__PATA_DATA11		IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__SD3_DATA3		IOMUX_PAD(0x54c, 0x164, 5, 0x948, 1, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__GPIO3_30		IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__NANDF_D10		IOMUX_PAD(0x550, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__PATA_DATA10		IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__SD3_DATA2		IOMUX_PAD(0x550, 0x168, 5, 0x944, 1, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__FEC_RDATA0		IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4)
+#define MX51_PAD_NANDF_D9__GPIO3_31		IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__NANDF_D9		IOMUX_PAD(0x554, 0x16c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__PATA_DATA9		IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__SD3_DATA1		IOMUX_PAD(0x554, 0x16c, 5, 0x940, 1, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__FEC_TDATA0		IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_D8__GPIO4_0		IOMUX_PAD(0x558, 0x170, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__NANDF_D8		IOMUX_PAD(0x558, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__PATA_DATA8		IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__SD3_DATA0		IOMUX_PAD(0x558, 0x170, 5, 0x93c, 1, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__GPIO4_1		IOMUX_PAD(0x55c, 0x174, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__NANDF_D7		IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__PATA_DATA7		IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__USBH3_DATA0		IOMUX_PAD(0x55c, 0x174, 5, 0x9fc, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__GPIO4_2		IOMUX_PAD(0x560, 0x178, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__NANDF_D6		IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__PATA_DATA6		IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__SD4_LCTL		IOMUX_PAD(0x560, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__USBH3_DATA1		IOMUX_PAD(0x560, 0x178, 5, 0xa00, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__GPIO4_3		IOMUX_PAD(0x564, 0x17c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__NANDF_D5		IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__PATA_DATA5		IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__SD4_WP		IOMUX_PAD(0x564, 0x17c, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__USBH3_DATA2		IOMUX_PAD(0x564, 0x17c, 5, 0xa04, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__GPIO4_4		IOMUX_PAD(0x568, 0x180, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__NANDF_D4		IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__PATA_DATA4		IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__SD4_CD		IOMUX_PAD(0x568, 0x180, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__USBH3_DATA3		IOMUX_PAD(0x568, 0x180, 5, 0xa08, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__GPIO4_5		IOMUX_PAD(0x56c, 0x184, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__NANDF_D3		IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__PATA_DATA3		IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__SD4_DAT4		IOMUX_PAD(0x56c, 0x184, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__USBH3_DATA4		IOMUX_PAD(0x56c, 0x184, 5, 0xa0c, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__GPIO4_6		IOMUX_PAD(0x570, 0x188, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__NANDF_D2		IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__PATA_DATA2		IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__SD4_DAT5		IOMUX_PAD(0x570, 0x188, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__USBH3_DATA5		IOMUX_PAD(0x570, 0x188, 5, 0xa10, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__GPIO4_7		IOMUX_PAD(0x574, 0x18c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__NANDF_D1		IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__PATA_DATA1		IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__SD4_DAT6		IOMUX_PAD(0x574, 0x18c, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__USBH3_DATA6		IOMUX_PAD(0x574, 0x18c, 5, 0xa14, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__GPIO4_8		IOMUX_PAD(0x578, 0x190, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__NANDF_D0		IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__PATA_DATA0		IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__SD4_DAT7		IOMUX_PAD(0x578, 0x190, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__USBH3_DATA7		IOMUX_PAD(0x578, 0x190, 5, 0xa18, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D8__CSI1_D8		IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D8__GPIO3_12		IOMUX_PAD(0x57c, 0x194, 3, 0x998, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI1_D9__CSI1_D9		IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D9__GPIO3_13		IOMUX_PAD(0x580, 0x198, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI1_D10__CSI1_D10		IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D11__CSI1_D11		IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D12__CSI1_D12		IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D13__CSI1_D13		IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D14__CSI1_D14		IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D15__CSI1_D15		IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D16__CSI1_D16		IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D17__CSI1_D17		IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D18__CSI1_D18		IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D19__CSI1_D19		IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC		IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_VSYNC__GPIO3_14		IOMUX_PAD(0x5ac, 0x1c4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC		IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_HSYNC__GPIO3_15		IOMUX_PAD(0x5b0, 0x1c8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK	IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_MCLK__CSI1_MCLK		IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D12__CSI2_D12		IOMUX_PAD(0x5bc, 0x1cc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D12__GPIO4_9		IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI2_D13__CSI2_D13		IOMUX_PAD(0x5c0, 0x1d0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D13__GPIO4_10		IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI2_D14__CSI2_D14		IOMUX_PAD(0x5c4, 0x1d4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D15__CSI2_D15		IOMUX_PAD(0x5c8, 0x1d8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D16__CSI2_D16		IOMUX_PAD(0x5cc, 0x1dc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D17__CSI2_D17		IOMUX_PAD(0x5d0, 0x1e0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D18__CSI2_D18		IOMUX_PAD(0x5d4, 0x1e4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D18__GPIO4_11		IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI2_D19__CSI2_D19		IOMUX_PAD(0x5d8, 0x1e8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D19__GPIO4_12		IOMUX_PAD(0x5d8, 0x1e8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC		IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_VSYNC__GPIO4_13		IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC		IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_HSYNC__GPIO4_14		IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK	IOMUX_PAD(0x5e4, 0x1f4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_PIXCLK__GPIO4_15		IOMUX_PAD(0x5e4, 0x1f4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__GPIO4_16		IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__I2C1_CLK		IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__GPIO4_17		IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__I2C1_DAT		IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD		IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_TXD__GPIO4_18		IOMUX_PAD(0x5f0, 0x200, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD		IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__GPIO4_19		IOMUX_PAD(0x5f4, 0x204, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__UART3_RXD		IOMUX_PAD(0x5f4, 0x204, 1, 0x9f4, 2, MX51_UART_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_CK__AUD3_TXC		IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_CK__GPIO4_20		IOMUX_PAD(0x5f8, 0x208, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS		IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__GPIO4_21		IOMUX_PAD(0x5fc, 0x20c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__UART3_TXD		IOMUX_PAD(0x5fc, 0x20c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI	IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__GPIO4_22		IOMUX_PAD(0x600, 0x210, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__I2C1_SDA		IOMUX_PAD(0x600, 0x210, 0x11, 0x9b4, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__AUD4_RXD		IOMUX_PAD(0x604, 0x214, 1, 0x8c4, 1, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO	IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__GPIO4_23		IOMUX_PAD(0x604, 0x214, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__AUD4_TXC		IOMUX_PAD(0x608, 0x218, 1, 0x8cc, 1, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0		IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__GPIO4_24		IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__AUD4_TXD		IOMUX_PAD(0x60c, 0x21c, 1, 0x8c8, 1, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1		IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__GPIO4_25		IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__AUD4_TXFS		IOMUX_PAD(0x610, 0x220, 1, 0x8d0, 1, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY		IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__GPIO4_26		IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK	IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__GPIO4_27		IOMUX_PAD(0x614, 0x224, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__I2C1_SCL		IOMUX_PAD(0x614, 0x224, 0x11, 0x9b0, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_UART1_RXD__GPIO4_28		IOMUX_PAD(0x618, 0x228, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART1_RXD__UART1_RXD		IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART1_TXD__GPIO4_29		IOMUX_PAD(0x61c, 0x22c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART1_TXD__PWM2_PWMO		IOMUX_PAD(0x61c, 0x22c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART1_TXD__UART1_TXD		IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART1_RTS__GPIO4_30		IOMUX_PAD(0x620, 0x230, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART1_RTS__UART1_RTS		IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART1_CTS__GPIO4_31		IOMUX_PAD(0x624, 0x234, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART1_CTS__UART1_CTS		IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART2_RXD__FIRI_TXD		IOMUX_PAD(0x628, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART2_RXD__GPIO1_20		IOMUX_PAD(0x628, 0x238, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART2_RXD__UART2_RXD		IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART2_TXD__FIRI_RXD		IOMUX_PAD(0x62c, 0x23c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART2_TXD__GPIO1_21		IOMUX_PAD(0x62c, 0x23c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART2_TXD__UART2_TXD		IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__CSI1_D0		IOMUX_PAD(0x630, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__GPIO1_22		IOMUX_PAD(0x630, 0x240, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__UART1_DTR		IOMUX_PAD(0x630, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__UART3_RXD		IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__CSI1_D1		IOMUX_PAD(0x634, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__GPIO1_23		IOMUX_PAD(0x634, 0x244, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__UART1_DSR		IOMUX_PAD(0x634, 0x244, 0, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__UART3_TXD		IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_OWIRE_LINE__GPIO1_24		IOMUX_PAD(0x638, 0x248, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_OWIRE_LINE__OWIRE_LINE		IOMUX_PAD(0x638, 0x248, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_OWIRE_LINE__SPDIF_OUT		IOMUX_PAD(0x638, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW0__KEY_ROW0		IOMUX_PAD(0x63c, 0x24c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW1__KEY_ROW1		IOMUX_PAD(0x640, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW2__KEY_ROW2		IOMUX_PAD(0x644, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW3__KEY_ROW3		IOMUX_PAD(0x648, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL0__KEY_COL0		IOMUX_PAD(0x64c, 0x25c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL0__PLL1_BYP		IOMUX_PAD(0x64c, 0x25c, 7, 0x90c, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL1__KEY_COL1		IOMUX_PAD(0x650, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL1__PLL2_BYP		IOMUX_PAD(0x650, 0x260, 7, 0x910, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL2__KEY_COL2		IOMUX_PAD(0x654, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL2__PLL3_BYP		IOMUX_PAD(0x654, 0x264, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL3__KEY_COL3		IOMUX_PAD(0x658, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__I2C2_SCL		IOMUX_PAD(0x65c, 0x26c, 0x13, 0x9b8, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__KEY_COL4		IOMUX_PAD(0x65c, 0x26c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__SPDIF_OUT1		IOMUX_PAD(0x65c, 0x26c, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__UART1_RI		IOMUX_PAD(0x65c, 0x26c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__UART3_RTS		IOMUX_PAD(0x65c, 0x26c, 2, 0x9f0, 4, MX51_UART_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__I2C2_SDA		IOMUX_PAD(0x660, 0x270, 0x13, 0x9bc, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__KEY_COL5		IOMUX_PAD(0x660, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__UART1_DCD		IOMUX_PAD(0x660, 0x270, 1, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__UART3_CTS		IOMUX_PAD(0x660, 0x270, 2, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__CSPI_SCLK		IOMUX_PAD(0x678, 0x278, 1, 0x914, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__GPIO1_25		IOMUX_PAD(0x678, 0x278, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__I2C2_SCL		IOMUX_PAD(0x678, 0x278, 0x15, 0x9b8, 2, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__USBH1_CLK		IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__CSPI_MOSI		IOMUX_PAD(0x67c, 0x27c, 1, 0x91c, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__GPIO1_26		IOMUX_PAD(0x67c, 0x27c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__I2C2_SDA		IOMUX_PAD(0x67c, 0x27c, 0x15, 0x9bc, 2, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__USBH1_DIR		IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__CSPI_RDY		IOMUX_PAD(0x680, 0x280, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__GPIO1_27		IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__UART3_RXD		IOMUX_PAD(0x680, 0x280, 5, 0x9f4, 6, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__USBH1_STP		IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__CSPI_MISO		IOMUX_PAD(0x684, 0x284, 1, 0x918, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__GPIO1_28		IOMUX_PAD(0x684, 0x284, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__UART3_TXD		IOMUX_PAD(0x684, 0x284, 5, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__USBH1_NXT		IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__GPIO1_11		IOMUX_PAD(0x688, 0x288, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__UART2_CTS		IOMUX_PAD(0x688, 0x288, 1, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__USBH1_DATA0	IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__GPIO1_12		IOMUX_PAD(0x68c, 0x28c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__UART2_RXD		IOMUX_PAD(0x68c, 0x28c, 1, 0x9ec, 4, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__USBH1_DATA1	IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__GPIO1_13		IOMUX_PAD(0x690, 0x290, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__UART2_TXD		IOMUX_PAD(0x690, 0x290, 1, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__USBH1_DATA2	IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__GPIO1_14		IOMUX_PAD(0x694, 0x294, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__UART2_RTS		IOMUX_PAD(0x694, 0x294, 1, 0x9e8, 5, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__USBH1_DATA3	IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__CSPI_SS0		IOMUX_PAD(0x698, 0x298, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__GPIO1_15		IOMUX_PAD(0x698, 0x298, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__USBH1_DATA4	IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__CSPI_SS1		IOMUX_PAD(0x69c, 0x29c, 1, 0x920, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__GPIO1_16		IOMUX_PAD(0x69c, 0x29c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__USBH1_DATA5	IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__CSPI_SS3		IOMUX_PAD(0x6a0, 0x2a0, 1, 0x928, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__GPIO1_17		IOMUX_PAD(0x6a0, 0x2a0, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__USBH1_DATA6	IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3	IOMUX_PAD(0x6a4, 0x2a4, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3	IOMUX_PAD(0x6a4, 0x2a4, 5, 0x934, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__GPIO1_18		IOMUX_PAD(0x6a4, 0x2a4, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__USBH1_DATA7	IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_DI1_PIN11__DI1_PIN11		IOMUX_PAD(0x6a8, 0x2a8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN11__ECSPI1_SS2		IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_DI1_PIN11__GPIO3_0		IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN12__DI1_PIN12		IOMUX_PAD(0x6ac, 0x2ac, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN12__GPIO3_1		IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN13__DI1_PIN13		IOMUX_PAD(0x6b0, 0x2b0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN13__GPIO3_2		IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DI1_D0_CS__DI1_D0_CS		IOMUX_PAD(0x6b4, 0x2b4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D0_CS__GPIO3_3		IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__DI1_D1_CS		IOMUX_PAD(0x6b8, 0x2b8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__DISP1_PIN14		IOMUX_PAD(0x6b8, 0x2b8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__DISP1_PIN5		IOMUX_PAD(0x6b8, 0x2b8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__GPIO3_4		IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1	IOMUX_PAD(0x6bc, 0x2bc, 2, 0x9a4, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN	IOMUX_PAD(0x6bc, 0x2bc, 0, 0x9c4, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5	IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6	IOMUX_PAD(0x6c0, 0x2c0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO	IOMUX_PAD(0x6c0, 0x2c0, 0, 0x9c4, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6	IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17	IOMUX_PAD(0x6c4, 0x2c4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7	IOMUX_PAD(0x6c4, 0x2c4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK	IOMUX_PAD(0x6c4, 0x2c4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7	IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK	IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16	IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8	IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS	IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS	IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__GPIO3_8		IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT0__DISP1_DAT0		IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT1__DISP1_DAT1		IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT2__DISP1_DAT2		IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT3__DISP1_DAT3		IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT4__DISP1_DAT4		IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT5__DISP1_DAT5		IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC	IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT6__DISP1_DAT6		IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG	IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT7__DISP1_DAT7		IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT8__BOOT_SRC0		IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT8__DISP1_DAT8		IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT9__BOOT_SRC1		IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT9__DISP1_DAT9		IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE	IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT10__DISP1_DAT10	IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2	IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT11__DISP1_DAT11	IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL	IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT12__DISP1_DAT12	IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0	IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT13__DISP1_DAT13	IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1	IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT14__DISP1_DAT14	IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH	IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT15__DISP1_DAT15	IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0	IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT16__DISP1_DAT16	IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1	IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT17__DISP1_DAT17	IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0	IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__DISP1_DAT18	IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__DISP2_PIN11	IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__DISP2_PIN5	IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1	IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__DISP1_DAT19	IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__DISP2_PIN12	IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__DISP2_PIN6	IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0	IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__DISP1_DAT20	IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__DISP2_PIN13	IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__DISP2_PIN7	IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1	IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__DISP1_DAT21	IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__DISP2_PIN14	IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__DISP2_PIN8	IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0	IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__DISP1_DAT22	IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS	IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__DISP2_DAT16	IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1	IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP1_DAT23	IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS	IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP2_DAT17	IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS	IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN3__DI1_PIN3		IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN2__DI1_PIN2		IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP2__DISP1_SER_CLK		IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP2__DISP2_WAIT		IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP3__CSI1_DATA_EN		IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP3__DISP1_SER_DIO		IOMUX_PAD(0x744, 0x33c, 0, 0x9c0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP3__FEC_TX_ER		IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN		IOMUX_PAD(0x748, 0x340, 3, 0x99c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN4__DI2_PIN4		IOMUX_PAD(0x748, 0x340, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN4__FEC_CRS		IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN2__DI2_PIN2		IOMUX_PAD(0x74c, 0x344, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN2__FEC_MDC		IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DI2_PIN3__DI2_PIN3		IOMUX_PAD(0x750, 0x348, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN3__FEC_MDIO		IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1	IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__DI2_PIN15		IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__DISP1_SER_DIN		IOMUX_PAD(0x758, 0x350, 0, 0x9c0, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__DISP2_PIN1		IOMUX_PAD(0x758, 0x350, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__FEC_RDATA2		IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__DISP2_DAT0		IOMUX_PAD(0x75c, 0x354, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__FEC_RDATA3		IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__KEY_COL6		IOMUX_PAD(0x75c, 0x354, 4, 0x9c8, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__UART3_RXD		IOMUX_PAD(0x75c, 0x354, 5, 0x9f4, 8, MX51_UART_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__USBH3_CLK		IOMUX_PAD(0x75c, 0x354, 3, 0x9f8, 1, MX51_UART_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__DISP2_DAT1		IOMUX_PAD(0x760, 0x358, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__FEC_RX_ER		IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__KEY_COL7		IOMUX_PAD(0x760, 0x358, 4, 0x9cc, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__UART3_TXD		IOMUX_PAD(0x760, 0x358, 5, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__USBH3_DIR		IOMUX_PAD(0x760, 0x358, 3, 0xa1c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT2__DISP2_DAT2		IOMUX_PAD(0x764, 0x35c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT3__DISP2_DAT3		IOMUX_PAD(0x768, 0x360, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT4__DISP2_DAT4		IOMUX_PAD(0x76c, 0x364, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT5__DISP2_DAT5		IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__DISP2_DAT6		IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__FEC_TDATA1		IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DISP2_DAT6__GPIO1_19		IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__KEY_ROW4		IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__USBH3_STP		IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__DISP2_DAT7		IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__FEC_TDATA2		IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DISP2_DAT7__GPIO1_29		IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__KEY_ROW5		IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__USBH3_NXT		IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__DISP2_DAT8		IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__FEC_TDATA3		IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DISP2_DAT8__GPIO1_30		IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__KEY_ROW6		IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__USBH3_DATA0	IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__AUD6_RXC		IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__DISP2_DAT9		IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__FEC_TX_EN		IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DISP2_DAT9__GPIO1_31		IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__USBH3_DATA1	IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__DISP2_DAT10	IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS	IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__FEC_COL		IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__KEY_ROW7		IOMUX_PAD(0x784, 0x37c, 4, 0x9dc, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__USBH3_DATA2	IOMUX_PAD(0x784, 0x37c, 3, 0xa04, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__AUD6_TXD		IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__DISP2_DAT11	IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK	IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__GPIO1_10		IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__USBH3_DATA3	IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__AUD6_RXD		IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__DISP2_DAT12	IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__FEC_RX_DV		IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__USBH3_DATA4	IOMUX_PAD(0x78c, 0x384, 3, 0xa0c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT13__AUD6_TXC		IOMUX_PAD(0x790, 0x388, 4, 0x8fc, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT13__DISP2_DAT13	IOMUX_PAD(0x790, 0x388, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK	IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4)
+#define MX51_PAD_DISP2_DAT13__USBH3_DATA5	IOMUX_PAD(0x790, 0x388, 3, 0xa10, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT14__AUD6_TXFS		IOMUX_PAD(0x794, 0x38c, 4, 0x900, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT14__DISP2_DAT14	IOMUX_PAD(0x794, 0x38c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT14__FEC_RDATA0	IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4)
+#define MX51_PAD_DISP2_DAT14__USBH3_DATA6	IOMUX_PAD(0x794, 0x38c, 3, 0xa14, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__AUD6_RXFS		IOMUX_PAD(0x798, 0x390, 4, 0x8f8, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS	IOMUX_PAD(0x798, 0x390, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__DISP2_DAT15	IOMUX_PAD(0x798, 0x390, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__FEC_TDATA0	IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DISP2_DAT15__USBH3_DATA7	IOMUX_PAD(0x798, 0x390, 3, 0xa18, 1, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__AUD5_RXFS		IOMUX_PAD(0x79c, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__CSPI_MOSI		IOMUX_PAD(0x79c, 0x394, 2, 0x91c, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__SD1_CMD		IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__AUD5_RXC		IOMUX_PAD(0x7a0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__CSPI_SCLK		IOMUX_PAD(0x7a0, 0x398, 2, 0x914, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__SD1_CLK		IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
+#define MX51_PAD_SD1_DATA0__AUD5_TXD		IOMUX_PAD(0x7a4, 0x39c, 1, 0x8d8, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA0__CSPI_MISO		IOMUX_PAD(0x7a4, 0x39c, 2, 0x918, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_SD1_DATA0__SD1_DATA0		IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_EIM_DA0__EIM_DA0		IOMUX_PAD(__NA_, 0x01c, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA1__EIM_DA1		IOMUX_PAD(__NA_, 0x020, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA2__EIM_DA2		IOMUX_PAD(__NA_, 0x024, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA3__EIM_DA3		IOMUX_PAD(__NA_, 0x028, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA1__AUD5_RXD		IOMUX_PAD(0x7a8, 0x3a0, 1, 0x8d4, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA1__SD1_DATA1		IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_EIM_DA4__EIM_DA4		IOMUX_PAD(__NA_, 0x02c, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA5__EIM_DA5		IOMUX_PAD(__NA_, 0x030, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA6__EIM_DA6		IOMUX_PAD(__NA_, 0x034, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA7__EIM_DA7		IOMUX_PAD(__NA_, 0x038, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA2__AUD5_TXC		IOMUX_PAD(0x7ac, 0x3a4, 1, 0x8e4, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA2__SD1_DATA2		IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_EIM_DA10__EIM_DA10		IOMUX_PAD(__NA_, 0x044, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA11__EIM_DA11		IOMUX_PAD(__NA_, 0x048, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA8__EIM_DA8		IOMUX_PAD(__NA_, 0x03c, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA9__EIM_DA9		IOMUX_PAD(__NA_, 0x040, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__AUD5_TXFS		IOMUX_PAD(0x7b0, 0x3a8, 1, 0x8e8, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__CSPI_SS1		IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__SD1_DATA3		IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_GPIO1_0__CSPI_SS2		IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_GPIO1_0__GPIO1_0		IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_0__SD1_CD		IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
+#define MX51_PAD_GPIO1_1__CSPI_MISO		IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_GPIO1_1__GPIO1_1		IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_1__SD1_WP		IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
+#define MX51_PAD_EIM_DA12__EIM_DA12		IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA13__EIM_DA13		IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA14__EIM_DA14		IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA15__EIM_DA15		IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__CSPI_MOSI		IOMUX_PAD(__NA_, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__I2C1_SCL		IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__SD2_CMD		IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__CSPI_SCLK		IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__I2C1_SDA		IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x9b4, 2, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__SD2_CLK		IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
+#define MX51_PAD_SD2_DATA0__CSPI_MISO		IOMUX_PAD(0x7c4, 0x3bc, 2, 0x918, 3, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_SD2_DATA0__SD1_DAT4		IOMUX_PAD(0x7c4, 0x3bc, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA0__SD2_DATA0		IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__SD1_DAT5		IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__SD2_DATA1		IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__USBH3_H2_DP		IOMUX_PAD(0x7c8, 0x3c0, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__SD1_DAT6		IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__SD2_DATA2		IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__USBH3_H2_DM		IOMUX_PAD(0x7cc, 0x3c4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA3__CSPI_SS2		IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_SD2_DATA3__SD1_DAT7		IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA3__SD2_DATA3		IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_GPIO1_2__CCM_OUT_2		IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_2__GPIO1_2		IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_2__I2C2_SCL		IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_GPIO1_2__PLL1_BYP		IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_2__PWM1_PWMO		IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__GPIO1_3		IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__I2C2_SDA		IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__PLL2_BYP		IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__PWM2_PWMO		IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B	IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK		IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_4__EIM_RDY		IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_4__GPIO1_4		IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B		IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_5__CSI2_MCLK		IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_5__DISP2_PIN16		IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_5__GPIO1_5		IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B		IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_6__DISP2_PIN17		IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_6__GPIO1_6		IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_6__REF_EN_B		IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_7__CCM_OUT_0		IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_7__GPIO1_7		IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_7__SD2_WP		IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
+#define MX51_PAD_GPIO1_7__SPDIF_OUT1		IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_8__CSI2_DATA_EN		IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_8__GPIO1_8		IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_8__SD2_CD		IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
+#define MX51_PAD_GPIO1_8__USBH3_PWR		IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__CCM_OUT_1		IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__DISP2_D1_CS		IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__DISP2_SER_CS		IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__GPIO1_9		IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__SD2_LCTL		IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__USBH3_OC		IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL)
 
-#define MX51_PAD_NANDF_RB4__NANDF_RB4			IOMUX_PAD(0x514, 0x12C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB5__NANDF_RB5			IOMUX_PAD(0x5D8, 0x130, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB6__FEC_RDATA0			IOMUX_PAD(0x5DC, 0x16C, 2, 0x958, 0, MX51_FEC_PAD_CTRL)
-
-#define MX51_PAD_NANDF_RB7__NANDF_RB7			IOMUX_PAD(0x5E0, 0x138, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB7__FEC_TX_ER			IOMUX_PAD(0x5E0, 0x138, 2, 0x0, 0, NO_PAD_CTRL)
-
-#define MX51_PAD_NANDF_CS0__NANDF_CS0			IOMUX_PAD(0x518, 0x130, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS1__NANDF_CS1			IOMUX_PAD(0x51C, 0x134, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__NANDF_CS2			IOMUX_PAD(0x520, 0x138, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX51_PAD_NANDF_CS3__NANDF_CS3			IOMUX_PAD(0x524, 0x13C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__FEC_MDC			IOMUX_PAD(0x524, 0x13C, 2, 0x0, 0,MX51_FEC_PAD_CTRL)
-
-#define MX51_PAD_NANDF_CS4__NANDF_CS4			IOMUX_PAD(0x528, 0x140, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__FEC_TDATA1			IOMUX_PAD(0x528, 0x140, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
-
-#define MX51_PAD_NANDF_CS5__NANDF_CS5			IOMUX_PAD(0x52C, 0x144, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__FEC_TDATA2			IOMUX_PAD(0x52C, 0x144, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
-
-#define MX51_PAD_NANDF_CS6__NANDF_CS6			IOMUX_PAD(0x530, 0x148, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__FEC_TDATA3			IOMUX_PAD(0x530, 0x148, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
-
-#define MX51_PAD_NANDF_CS7__NANDF_CS7			IOMUX_PAD(0x534, 0x14C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS7__FEC_TX_EN			IOMUX_PAD(0x534, 0x14C, 1, 0x0, 0, MX51_FEC_PAD_CTRL)
-
-#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT		IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK		IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_FEC_PAD_CTRL)
-
-#define MX51_PAD_NANDF_D15__NANDF_D15			IOMUX_PAD(0x53C, 0x154, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__NANDF_D14			IOMUX_PAD(0x540, 0x158, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__NANDF_D13			IOMUX_PAD(0x544, 0x15C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__NANDF_D12			IOMUX_PAD(0x548, 0x160, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX51_PAD_NANDF_D11__NANDF_D11			IOMUX_PAD(0x54C, 0x164, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__FEC_RX_DV			IOMUX_PAD(0x54C, 0x164, 2, 0x96c, 0, MX51_FEC_PAD_CTRL)
-
-#define MX51_PAD_NANDF_D10__NANDF_D10			IOMUX_PAD(0x550, 0x168, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX51_PAD_NANDF_D9__NANDF_D9			IOMUX_PAD(0x554, 0x16C, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX51_PAD_NANDF_D8__NANDF_D8			IOMUX_PAD(0x558, 0x170, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__FEC_TDATA0			IOMUX_PAD(0x558, 0x170, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
-
-#define MX51_PAD_NANDF_D7__NANDF_D7			IOMUX_PAD(0x55C, 0x174, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__NANDF_D6			IOMUX_PAD(0x560, 0x178, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__NANDF_D5			IOMUX_PAD(0x564, 0x17C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__NANDF_D4			IOMUX_PAD(0x568, 0x180, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__NANDF_D3			IOMUX_PAD(0x56C, 0x184, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__NANDF_D2			IOMUX_PAD(0x570, 0x188, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__NANDF_D1			IOMUX_PAD(0x574, 0x18C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__NANDF_D0			IOMUX_PAD(0x578, 0x190, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D8__CSI1_D8			IOMUX_PAD(0x57C, 0x194, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D9__CSI1_D9			IOMUX_PAD(0x580, 0x198, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D10__CSI1_D10			IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D11__CSI1_D11			IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D12__CSI1_D12			IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D13__CSI1_D13			IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D14__CSI1_D14			IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D15__CSI1_D15			IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D16__CSI1_D16			IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D17__CSI1_D17			IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D18__CSI1_D18			IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D19__CSI1_D19			IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC			IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC			IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK		IOMUX_PAD(0x5B4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_MCLK__CSI1_MCLK			IOMUX_PAD(0x5B8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PKE0__CSI1_PKE0			IOMUX_PAD(0x860, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D12__CSI2_D12			IOMUX_PAD(0x5BC, 0x1CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D13__CSI2_D13			IOMUX_PAD(0x5C0, 0x1D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D14__CSI2_D14			IOMUX_PAD(0x5C4, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D15__CSI2_D15			IOMUX_PAD(0x5C8, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D16__CSI2_D16			IOMUX_PAD(0x5CC, 0x1DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D17__CSI2_D17			IOMUX_PAD(0x5D0, 0x1E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D18__CSI2_D18			IOMUX_PAD(0x5D4, 0x1E4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D19__CSI2_D19			IOMUX_PAD(0x5D8, 0x1E8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC			IOMUX_PAD(0x5DC, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC			IOMUX_PAD(0x5E0, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK		IOMUX_PAD(0x5E4, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_PKE0__CSI2_PKE0			IOMUX_PAD(0x81C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_I2C1_CLK__I2C1_CLK			IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_I2C1_DAT__I2C1_DAT			IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD		IOMUX_PAD(0x5F0, 0x200, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD		IOMUX_PAD(0x5F4, 0x204, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK			IOMUX_PAD(0x5F8, 0x208, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS			IOMUX_PAD(0x5FC, 0x20C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_MOSI__CSPI1_MOSI			IOMUX_PAD(0x600, 0x210, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_MISO__CSPI1_MISO			IOMUX_PAD(0x604, 0x214, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS0__CSPI1_SS0			IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS1__CSPI1_SS1			IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_RDY__CSPI1_RDY			IOMUX_PAD(0x610, 0x220, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SCLK__CSPI1_SCLK			IOMUX_PAD(0x614, 0x224, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART1_RXD__UART1_RXD			IOMUX_PAD(0x618, 0x228, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART1_TXD__UART1_TXD			IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART1_RTS__UART1_RTS			IOMUX_PAD(0x620, 0x230, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__UART1_CTS			IOMUX_PAD(0x624, 0x234, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART2_RXD__UART2_RXD			IOMUX_PAD(0x628, 0x238, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__UART2_TXD			IOMUX_PAD(0x62C, 0x23C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__UART3_RXD			IOMUX_PAD(0x630, 0x240, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__UART3_TXD			IOMUX_PAD(0x634, 0x244, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_OWIRE_LINE__OWIRE_LINE			IOMUX_PAD(0x638, 0x248, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW0__KEY_ROW0			IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW1__KEY_ROW1			IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW2__KEY_ROW2			IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW3__KEY_ROW3			IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__KEY_COL0			IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__KEY_COL1			IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__KEY_COL2			IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL3__KEY_COL3			IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__KEY_COL4			IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__KEY_COL5			IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__USBH1_CLK			IOMUX_PAD(0x678, 0x278, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__USBH1_DIR			IOMUX_PAD(0x67C, 0x27C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__USBH1_STP			IOMUX_PAD(0x680, 0x280, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__USBH1_NXT			IOMUX_PAD(0x684, 0x284, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__USBH1_DATA0		IOMUX_PAD(0x688, 0x288, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__USBH1_DATA1		IOMUX_PAD(0x68C, 0x28C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__USBH1_DATA2		IOMUX_PAD(0x690, 0x290, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__USBH1_DATA3		IOMUX_PAD(0x694, 0x294, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__USBH1_DATA4		IOMUX_PAD(0x698, 0x298, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__USBH1_DATA5		IOMUX_PAD(0x69C, 0x29C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__USBH1_DATA6		IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__USBH1_DATA7		IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN11__DI1_PIN11			IOMUX_PAD(0x6A8, 0x2A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN12__DI1_PIN12			IOMUX_PAD(0x6AC, 0x2AC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN13__DI1_PIN13			IOMUX_PAD(0x6B0, 0x2B0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D0_CS__DI1_D0_CS			IOMUX_PAD(0x6B4, 0x2B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__DI1_D1_CS			IOMUX_PAD(0x6B8, 0x2B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__GPIO3_4			IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0984, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN		IOMUX_PAD(0x6BC, 0x2BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO		IOMUX_PAD(0x6C0, 0x2C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK		IOMUX_PAD(0x6C4, 0x2C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS		IOMUX_PAD(0x6C8, 0x2C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT0__DISP1_DAT0			IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT1__DISP1_DAT1			IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT2__DISP1_DAT2			IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT3__DISP1_DAT3			IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT4__DISP1_DAT4			IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT5__DISP1_DAT5			IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__DISP1_DAT6			IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__DISP1_DAT7			IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__DISP1_DAT8			IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__DISP1_DAT9			IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__DISP1_DAT10		IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__DISP1_DAT11		IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__DISP1_DAT12		IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__DISP1_DAT13		IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__DISP1_DAT14		IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__DISP1_DAT15		IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__DISP1_DAT16		IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__DISP1_DAT17		IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP1_DAT18		IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP1_DAT19		IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP1_DAT20		IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP1_DAT21		IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP1_DAT22		IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP1_DAT23		IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN3__DI1_PIN3			IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN2__DI1_PIN2			IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP1__DI_GP1				IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DI_GP2				IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__DI_GP3				IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__DI2_PIN4			IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__FEC_TX_ER			IOMUX_PAD(0x744, 0x33c, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__DI2_PIN2			IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__FEC_MDC			IOMUX_PAD(0x74c, 0x344, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
-#define MX51_PAD_DI2_PIN3__DI2_PIN3			IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN3__FEC_MDIO			IOMUX_PAD(0x750, 0x348, 2, 0x0954, 1, MX51_FEC_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK		IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DI_GP4				IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__FEC_RDATA2			IOMUX_PAD(0x758, 0x350, 2, 0x0960, 1, MX51_FEC_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__FEC_CRS			IOMUX_PAD(0x748, 0x340, 2, 0x0950, 1, MX51_FEC_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1		IOMUX_PAD(0x754, 0x34c, 2, 0x095c, 1, MX51_FEC_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__DISP2_DAT0			IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__FEC_RDATA3			IOMUX_PAD(0x75c, 0x354, 2, 0x0964, 1, MX51_FEC_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__DISP2_DAT1			IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__FEC_RX_ER			IOMUX_PAD(0x760, 0x358, 2, 0x0970, 1, MX51_FEC_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT2__DISP2_DAT2			IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT3__DISP2_DAT3			IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT4__DISP2_DAT4			IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT5__DISP2_DAT5			IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__DISP2_DAT6			IOMUX_PAD(0x774, 0x36C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__FEC_TDATA1			IOMUX_PAD(0x774, 0x36c, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__DISP2_DAT7			IOMUX_PAD(0x778, 0x370, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__FEC_TDATA2			IOMUX_PAD(0x778, 0x370, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__DISP2_DAT8			IOMUX_PAD(0x77C, 0x374, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__FEC_TDATA3			IOMUX_PAD(0x77c, 0x374, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__DISP2_DAT9			IOMUX_PAD(0x780, 0x378, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__FEC_TX_EN			IOMUX_PAD(0x780, 0x378, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_DAT10		IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__FEC_COL			IOMUX_PAD(0x784, 0x37c, 2, 0x094c, 1, MX51_FEC_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__DISP2_DAT11		IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK		IOMUX_PAD(0x788, 0x380, 2, 0x0968, 1, MX51_FEC_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__DISP2_DAT12		IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__FEC_RX_DV			IOMUX_PAD(0x78c, 0x384, 2, 0x096c, 1, MX51_FEC_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__DISP2_DAT13		IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK		IOMUX_PAD(0x790, 0x388, 2, 0x0974, 1, MX51_FEC_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__DISP2_DAT14		IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__FEC_RDATA0		IOMUX_PAD(0x794, 0x38c, 2, 0x0958, 1, MX51_FEC_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP2_DAT15		IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__FEC_TDATA0		IOMUX_PAD(0x798, 0x390, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__SD1_CMD			IOMUX_PAD(0x79C, 0x394, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__SD1_CLK			IOMUX_PAD(0x7A0, 0x398, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__SD1_DATA0			IOMUX_PAD(0x7A4, 0x39C, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__SD1_DATA1			IOMUX_PAD(0x7A8, 0x3A0, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__SD1_DATA2			IOMUX_PAD(0x7AC, 0x3A4, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__SD1_DATA3			IOMUX_PAD(0x7B0, 0x3A8, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_GPIO1_0__GPIO1_0			IOMUX_PAD(0x7B4, 0x3AC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_1__GPIO1_1			IOMUX_PAD(0x7B8, 0x3B0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__SD2_CMD			IOMUX_PAD(0x7BC, 0x3B4, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__SD2_CLK			IOMUX_PAD(0x7C0, 0x3B8, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD2_DATA0			IOMUX_PAD(0x7C4, 0x3BC, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD2_DATA1			IOMUX_PAD(0x7C8, 0x3C0, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD2_DATA2			IOMUX_PAD(0x7CC, 0x3C4, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD2_DATA3			IOMUX_PAD(0x7D0, 0x3C8, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__GPIO1_2			IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__GPIO1_3			IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ		IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__GPIO1_4			IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__GPIO1_5			IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__GPIO1_6			IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__GPIO1_7			IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__GPIO1_8			IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__GPIO1_9			IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
 #endif /* __MACH_IOMUX_MX51_H__ */
-
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx53.h b/arch/arm/mach-imx/include/mach/iomux-mx53.h
index ac94debd86..527f8fe3e3 100644
--- a/arch/arm/mach-imx/include/mach/iomux-mx53.h
+++ b/arch/arm/mach-imx/include/mach/iomux-mx53.h
@@ -30,9 +30,7 @@
 #define MX53_SDHC_PAD_CTRL 	(PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
 				PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \
 				PAD_CTL_SRE_FAST)
-#define MX53_I2C_PAD_CTRL 	(PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
-				PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_HIGH | \
-				PAD_CTL_SRE_FAST)
+
 
 #define MX53_PAD_GPIO_19__KPP_COL_5			IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL)
 #define MX53_PAD_GPIO_19__GPIO4_5			IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL)
@@ -379,7 +377,7 @@
 #define MX53_PAD_CSI0_DAT8__KPP_COL_7			IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL)
 #define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK			IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL)
 #define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC		IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__I2C1_SDA			IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, MX53_I2C_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__I2C1_SDA			IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL)
 #define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37		IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL)
 #define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5		IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL)
 #define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9		IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL)
@@ -387,7 +385,7 @@
 #define MX53_PAD_CSI0_DAT9__KPP_ROW_7			IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL)
 #define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI			IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL)
 #define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR		IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__I2C1_SCL			IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, MX53_I2C_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__I2C1_SCL			IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL)
 #define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38		IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL)
 #define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6		IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL)
 #define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10		IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL)
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx6.h b/arch/arm/mach-imx/include/mach/iomux-mx6.h
new file mode 100644
index 0000000000..f50fd8af16
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/iomux-mx6.h
@@ -0,0 +1,5630 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Auto Generate file, please don't edit it
+ *
+ */
+#define MUX_PAD_CTRL(x)                ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
+
+#ifndef __MACH_IOMUX_MX6Q_H__
+#define __MACH_IOMUX_MX6Q_H__
+
+#include <mach/iomux-v3.h>
+
+#define NON_MUX_I       0x3FF
+#define NON_PAD_I       0x7FF
+
+/*
+ * Use to set PAD control
+ */
+#define MX6_PAD_CTL_HYS		(1 << 16)
+
+#define MX6_PAD_CTL_PUS_100K_DOWN	(0 << 14)
+#define MX6_PAD_CTL_PUS_47K_UP	(1 << 14)
+#define MX6_PAD_CTL_PUS_100K_UP	(2 << 14)
+#define MX6_PAD_CTL_PUS_22K_UP	(3 << 14)
+
+#define MX6_PAD_CTL_PUE		(1 << 13)
+#define MX6_PAD_CTL_PKE		(1 << 12)
+#define MX6_PAD_CTL_ODE		(1 << 11)
+
+#define MX6_PAD_CTL_SPEED_LOW	(1 << 6)
+#define MX6_PAD_CTL_SPEED_MED	(2 << 6)
+#define MX6_PAD_CTL_SPEED_HIGH	(3 << 6)
+
+#define MX6_PAD_CTL_DSE_DISABLE	(0 << 3)
+#define MX6_PAD_CTL_DSE_240ohm	(1 << 3)
+#define MX6_PAD_CTL_DSE_120ohm	(2 << 3)
+#define MX6_PAD_CTL_DSE_80ohm	(3 << 3)
+#define MX6_PAD_CTL_DSE_60ohm	(4 << 3)
+#define MX6_PAD_CTL_DSE_48ohm	(5 << 3)
+#define MX6_PAD_CTL_DSE_40ohm	(6 << 3)
+#define MX6_PAD_CTL_DSE_34ohm	(7 << 3)
+
+#define MX6_PAD_CTL_SRE_FAST	(1 << 0)
+#define MX6_PAD_CTL_SRE_SLOW	(0 << 0)
+
+#define MX6Q_UART_PAD_CTRL	(MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE |	\
+		MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
+		MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS)
+
+#define MX6Q_ECSPI_PAD_CTRL	(MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_PUS_100K_DOWN | MX6_PAD_CTL_SPEED_MED | \
+		MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS)
+
+#define MX6Q_USDHC_PAD_CTRL	(MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE |	\
+		MX6_PAD_CTL_PUS_47K_UP | MX6_PAD_CTL_SPEED_HIGH | \
+		MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS)
+
+#define MX6Q_ENET_PAD_CTRL	(MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE |	\
+		MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
+		MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS)
+
+#define MX6Q_I2C_PAD_CTRL	(MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE |	\
+		MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
+		MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS | \
+		MX6_PAD_CTL_ODE | MX6_PAD_CTL_SRE_FAST)
+
+#define MX6Q_PWM_PAD_CTRL	(MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE |	\
+		MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED| \
+		MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS | \
+		MX6_PAD_CTL_ODE | MX6_PAD_CTL_SRE_FAST)
+
+#define MX6Q_HIGH_DRV (MX6_PAD_CTL_DSE_120ohm)
+
+#define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1                                        \
+		IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__ECSPI5_SS0                                         \
+		IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2                                     \
+		IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS                                   \
+		IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__KPP_COL_7                                          \
+		IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__GPIO_1_14                                          \
+		IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__CCM_WAIT                                           \
+		IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0                              \
+		IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_DAT2__USDHC2_DAT2                                        \
+		IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__ECSPI5_SS1                                         \
+		IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3                                     \
+		IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD                                    \
+		IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__KPP_ROW_6                                          \
+		IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__GPIO_1_13                                          \
+		IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__CCM_STOP                                           \
+		IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1                              \
+		IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_DAT0__USDHC2_DAT0                                        \
+		IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__ECSPI5_MISO                                        \
+		IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD                                    \
+		IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__KPP_ROW_7                                          \
+		IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__GPIO_1_15                                          \
+		IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT                                     \
+		IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2                              \
+		IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA                                    \
+		IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC                                    \
+		IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK                                \
+		IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__GPIO_6_19                                         \
+		IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0                          \
+		IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT                             \
+		IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY                            \
+		IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0                                    \
+		IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD0__GPIO_6_20                                         \
+		IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1                          \
+		IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG                             \
+		IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1                                    \
+		IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD1__GPIO_6_21                                         \
+		IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2                          \
+		IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP                                      \
+		IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA                             \
+		IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2                                    \
+		IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD2__GPIO_6_22                                         \
+		IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3                          \
+		IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP                                      \
+		IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE                             \
+		IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3                                    \
+		IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD3__GPIO_6_23                                         \
+		IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4                          \
+		IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA                                 \
+		IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL                              \
+		IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0)
+#define _MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24                                      \
+		IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5                       \
+		IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY                            \
+		IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0                                    \
+		IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0)
+#define _MX6Q_PAD_RGMII_RD0__GPIO_6_25                                         \
+		IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6                          \
+		IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE                               \
+		IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL                              \
+		IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26                                      \
+		IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7                       \
+		IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT                   \
+		IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG                             \
+		IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1                                    \
+		IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0)
+#define _MX6Q_PAD_RGMII_RD1__GPIO_6_27                                         \
+		IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8                          \
+		IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD1__SJC_FAIL                                          \
+		IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA                             \
+		IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2                                    \
+		IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0)
+#define _MX6Q_PAD_RGMII_RD2__GPIO_6_28                                         \
+		IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9                          \
+		IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE                             \
+		IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3                                    \
+		IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0)
+#define _MX6Q_PAD_RGMII_RD3__GPIO_6_29                                         \
+		IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10                         \
+		IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE                                  \
+		IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC                                    \
+		IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0)
+#define _MX6Q_PAD_RGMII_RXC__GPIO_6_30                                         \
+		IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11                         \
+		IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25                                      \
+		IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__ECSPI4_SS1                                          \
+		IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__ECSPI2_RDY                                          \
+		IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12                                      \
+		IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS                                      \
+		IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__GPIO_5_2                                            \
+		IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE                                    \
+		IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0)
+#define _MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0                             \
+		IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2                                      \
+		IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__ECSPI1_SS0                                          \
+		IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK                                     \
+		IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19                                      \
+		IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL                                     \
+		IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__GPIO_2_30                                           \
+		IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__I2C2_SCL                                            \
+		IOMUX_PAD(0x03A0, 0x008C, 6 | IOMUX_CONFIG_SION, 0x08A0, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30                                       \
+		IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16                                      \
+		IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D16__ECSPI1_SCLK                                         \
+		IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0)
+#define _MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5                                       \
+		IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18                                      \
+		IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0)
+#define _MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA                                     \
+		IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0)
+#define _MX6Q_PAD_EIM_D16__GPIO_3_16                                           \
+		IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D16__I2C2_SDA                                            \
+		IOMUX_PAD(0x03A4, 0x0090, 6 | IOMUX_CONFIG_SION, 0x08A4, 0, 0)
+
+#define _MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17                                      \
+		IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D17__ECSPI1_MISO                                         \
+		IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0)
+#define _MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6                                       \
+		IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK                                    \
+		IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0)
+#define _MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT                                      \
+		IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D17__GPIO_3_17                                           \
+		IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D17__I2C3_SCL                                            \
+		IOMUX_PAD(0x03A8, 0x0094, 6 | IOMUX_CONFIG_SION, 0x08A8, 0, 0)
+#define _MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1                             \
+		IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18                                      \
+		IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D18__ECSPI1_MOSI                                         \
+		IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0)
+#define _MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7                                       \
+		IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17                                      \
+		IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0)
+#define _MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS                                      \
+		IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D18__GPIO_3_18                                           \
+		IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D18__I2C3_SDA                                            \
+		IOMUX_PAD(0x03AC, 0x0098, 6 | IOMUX_CONFIG_SION, 0x08AC, 0, 0)
+#define _MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2                             \
+		IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19                                      \
+		IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D19__ECSPI1_SS1                                          \
+		IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0)
+#define _MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8                                       \
+		IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16                                      \
+		IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0)
+#define _MX6Q_PAD_EIM_D19__UART1_CTS                                           \
+		IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0)
+#define _MX6Q_PAD_EIM_D19__GPIO_3_19                                           \
+		IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D19__EPIT1_EPITO                                         \
+		IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP                                \
+		IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20                                      \
+		IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D20__ECSPI4_SS0                                          \
+		IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0)
+#define _MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16                                      \
+		IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15                                      \
+		IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0)
+#define _MX6Q_PAD_EIM_D20__UART1_CTS                                           \
+		IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D20__UART1_RTS                                           \
+		IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0)
+#define _MX6Q_PAD_EIM_D20__GPIO_3_20                                           \
+		IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D20__EPIT2_EPITO                                         \
+		IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21                                      \
+		IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D21__ECSPI4_SCLK                                         \
+		IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17                                      \
+		IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11                                      \
+		IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0)
+#define _MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC                                    \
+		IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0)
+#define _MX6Q_PAD_EIM_D21__GPIO_3_21                                           \
+		IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D21__I2C1_SCL                                            \
+		IOMUX_PAD(0x03B8, 0x00A4, 6 | IOMUX_CONFIG_SION, 0x0898, 0, 0)
+#define _MX6Q_PAD_EIM_D21__SPDIF_IN1                                           \
+		IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0)
+
+#define _MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22                                      \
+		IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__ECSPI4_MISO                                         \
+		IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1                                       \
+		IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10                                      \
+		IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0)
+#define _MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR                                   \
+		IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__GPIO_3_22                                           \
+		IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__SPDIF_OUT1                                          \
+		IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE                               \
+		IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23                                      \
+		IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS                                      \
+		IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__UART3_CTS                                           \
+		IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0)
+#define _MX6Q_PAD_EIM_D23__UART1_DCD                                           \
+		IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN                                   \
+		IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0)
+#define _MX6Q_PAD_EIM_D23__GPIO_3_23                                           \
+		IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2                                       \
+		IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14                                      \
+		IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3                                      \
+		IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__ECSPI4_RDY                                          \
+		IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__UART3_CTS                                           \
+		IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__UART3_RTS                                           \
+		IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0)
+#define _MX6Q_PAD_EIM_EB3__UART1_RI                                            \
+		IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC                                     \
+		IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__GPIO_2_31                                           \
+		IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3                                       \
+		IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31                                       \
+		IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24                                      \
+		IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__ECSPI4_SS2                                          \
+		IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__UART3_TXD                                           \
+		IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__UART3_RXD                                           \
+		IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0)
+#define _MX6Q_PAD_EIM_D24__ECSPI1_SS2                                          \
+		IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0)
+#define _MX6Q_PAD_EIM_D24__ECSPI2_SS2                                          \
+		IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__GPIO_3_24                                           \
+		IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS                                    \
+		IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0)
+#define _MX6Q_PAD_EIM_D24__UART1_DTR                                           \
+		IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25                                      \
+		IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__ECSPI4_SS3                                          \
+		IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__UART3_TXD                                           \
+		IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__UART3_RXD                                           \
+		IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0)
+#define _MX6Q_PAD_EIM_D25__ECSPI1_SS3                                          \
+		IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0)
+#define _MX6Q_PAD_EIM_D25__ECSPI2_SS3                                          \
+		IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__GPIO_3_25                                           \
+		IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC                                     \
+		IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0)
+#define _MX6Q_PAD_EIM_D25__UART1_DSR                                           \
+		IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26                                      \
+		IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11                                      \
+		IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1                                       \
+		IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14                                      \
+		IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0)
+#define _MX6Q_PAD_EIM_D26__UART2_TXD                                           \
+		IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__UART2_RXD                                           \
+		IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0)
+#define _MX6Q_PAD_EIM_D26__GPIO_3_26                                           \
+		IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU1_SISG_2                                         \
+		IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22                                   \
+		IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27                                      \
+		IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13                                      \
+		IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0                                       \
+		IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13                                      \
+		IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0)
+#define _MX6Q_PAD_EIM_D27__UART2_TXD                                           \
+		IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__UART2_RXD                                           \
+		IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0)
+#define _MX6Q_PAD_EIM_D27__GPIO_3_27                                           \
+		IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU1_SISG_3                                         \
+		IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23                                   \
+		IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28                                      \
+		IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D28__I2C1_SDA                                            \
+		IOMUX_PAD(0x03D8, 0x00C4, 1 | IOMUX_CONFIG_SION, 0x089C, 0, 0)
+#define _MX6Q_PAD_EIM_D28__ECSPI4_MOSI                                         \
+		IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12                                      \
+		IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0)
+#define _MX6Q_PAD_EIM_D28__UART2_CTS                                           \
+		IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0)
+#define _MX6Q_PAD_EIM_D28__GPIO_3_28                                           \
+		IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG                                       \
+		IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13                                      \
+		IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29                                      \
+		IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15                                      \
+		IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D29__ECSPI4_SS0                                          \
+		IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0)
+#define _MX6Q_PAD_EIM_D29__UART2_CTS                                           \
+		IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D29__UART2_RTS                                           \
+		IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0)
+#define _MX6Q_PAD_EIM_D29__GPIO_3_29                                           \
+		IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC                                     \
+		IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0)
+#define _MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14                                      \
+		IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30                                      \
+		IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21                                   \
+		IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11                                      \
+		IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3                                       \
+		IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__UART3_CTS                                           \
+		IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0)
+#define _MX6Q_PAD_EIM_D30__GPIO_3_30                                           \
+		IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC                                     \
+		IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0)
+#define _MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0                              \
+		IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31                                      \
+		IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20                                   \
+		IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12                                      \
+		IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2                                       \
+		IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__UART3_CTS                                           \
+		IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__UART3_RTS                                           \
+		IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0)
+#define _MX6Q_PAD_EIM_D31__GPIO_3_31                                           \
+		IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR                                    \
+		IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1                              \
+		IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24                                      \
+		IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19                                   \
+		IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19                                      \
+		IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0)
+#define _MX6Q_PAD_EIM_A24__IPU2_SISG_2                                         \
+		IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__IPU1_SISG_2                                         \
+		IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__GPIO_5_4                                            \
+		IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2                              \
+		IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__SRC_BT_CFG_24                                       \
+		IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23                                      \
+		IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18                                   \
+		IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18                                      \
+		IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0)
+#define _MX6Q_PAD_EIM_A23__IPU2_SISG_3                                         \
+		IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__IPU1_SISG_3                                         \
+		IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__GPIO_6_6                                            \
+		IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3                              \
+		IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__SRC_BT_CFG_23                                       \
+		IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22                                      \
+		IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17                                   \
+		IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17                                      \
+		IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0)
+#define _MX6Q_PAD_EIM_A22__GPIO_2_16                                           \
+		IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A22__TPSMP_HDATA_0                                       \
+		IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A22__SRC_BT_CFG_22                                       \
+		IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21                                      \
+		IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16                                   \
+		IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16                                      \
+		IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0)
+#define _MX6Q_PAD_EIM_A21__RESERVED_RESERVED                                   \
+		IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18                          \
+		IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__GPIO_2_17                                           \
+		IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__TPSMP_HDATA_1                                       \
+		IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__SRC_BT_CFG_21                                       \
+		IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20                                      \
+		IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15                                   \
+		IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15                                      \
+		IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0)
+#define _MX6Q_PAD_EIM_A20__RESERVED_RESERVED                                   \
+		IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19                          \
+		IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__GPIO_2_18                                           \
+		IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__TPSMP_HDATA_2                                       \
+		IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__SRC_BT_CFG_20                                       \
+		IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19                                      \
+		IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14                                   \
+		IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14                                      \
+		IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0)
+#define _MX6Q_PAD_EIM_A19__RESERVED_RESERVED                                   \
+		IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20                          \
+		IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__GPIO_2_19                                           \
+		IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__TPSMP_HDATA_3                                       \
+		IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__SRC_BT_CFG_19                                       \
+		IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18                                      \
+		IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13                                   \
+		IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13                                      \
+		IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0)
+#define _MX6Q_PAD_EIM_A18__RESERVED_RESERVED                                   \
+		IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21                          \
+		IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__GPIO_2_20                                           \
+		IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__TPSMP_HDATA_4                                       \
+		IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__SRC_BT_CFG_18                                       \
+		IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17                                      \
+		IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12                                   \
+		IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12                                      \
+		IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0)
+#define _MX6Q_PAD_EIM_A17__RESERVED_RESERVED                                   \
+		IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22                          \
+		IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__GPIO_2_21                                           \
+		IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__TPSMP_HDATA_5                                       \
+		IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__SRC_BT_CFG_17                                       \
+		IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16                                      \
+		IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK                                   \
+		IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK                                    \
+		IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0)
+#define _MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23                          \
+		IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__GPIO_2_22                                           \
+		IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__TPSMP_HDATA_6                                       \
+		IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__SRC_BT_CFG_16                                       \
+		IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0                                      \
+		IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5                                       \
+		IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__ECSPI2_SCLK                                         \
+		IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24                          \
+		IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__GPIO_2_23                                           \
+		IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7                                       \
+		IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1                                      \
+		IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6                                       \
+		IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__ECSPI2_MOSI                                         \
+		IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25                          \
+		IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__GPIO_2_24                                           \
+		IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8                                       \
+		IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_OE__WEIM_WEIM_OE                                         \
+		IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7                                        \
+		IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_OE__ECSPI2_MISO                                          \
+		IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0)
+#define _MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26                           \
+		IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_OE__GPIO_2_25                                            \
+		IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_OE__TPSMP_HDATA_9                                        \
+		IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_RW__WEIM_WEIM_RW                                         \
+		IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8                                        \
+		IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__ECSPI2_SS0                                           \
+		IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0)
+#define _MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27                           \
+		IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__GPIO_2_26                                            \
+		IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__TPSMP_HDATA_10                                       \
+		IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__SRC_BT_CFG_29                                        \
+		IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA                                       \
+		IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17                                      \
+		IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__ECSPI2_SS1                                          \
+		IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__GPIO_2_27                                           \
+		IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11                                      \
+		IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26                                       \
+		IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0                                      \
+		IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11                                   \
+		IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11                                      \
+		IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0)
+#define _MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0                           \
+		IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY                                        \
+		IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__GPIO_2_28                                           \
+		IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12                                      \
+		IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27                                       \
+		IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1                                      \
+		IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10                                   \
+		IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10                                      \
+		IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0)
+#define _MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1                           \
+		IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__GPIO_2_29                                           \
+		IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13                                      \
+		IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28                                       \
+		IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0                                    \
+		IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9                                    \
+		IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9                                       \
+		IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2                           \
+		IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__GPIO_3_0                                            \
+		IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14                                      \
+		IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0                                        \
+		IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1                                    \
+		IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8                                    \
+		IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8                                       \
+		IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3                           \
+		IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE                      \
+		IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__GPIO_3_1                                            \
+		IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15                                      \
+		IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1                                        \
+		IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2                                    \
+		IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7                                    \
+		IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7                                       \
+		IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4                           \
+		IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE                      \
+		IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__GPIO_3_2                                            \
+		IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16                                      \
+		IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2                                        \
+		IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3                                    \
+		IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6                                    \
+		IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6                                       \
+		IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5                           \
+		IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ                          \
+		IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__GPIO_3_3                                            \
+		IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17                                      \
+		IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3                                        \
+		IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4                                    \
+		IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5                                    \
+		IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5                                       \
+		IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6                           \
+		IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN                           \
+		IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__GPIO_3_4                                            \
+		IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18                                      \
+		IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4                                        \
+		IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5                                    \
+		IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4                                    \
+		IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4                                       \
+		IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7                           \
+		IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP                           \
+		IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__GPIO_3_5                                            \
+		IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19                                      \
+		IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5                                        \
+		IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6                                    \
+		IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3                                    \
+		IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3                                       \
+		IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8                           \
+		IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN                           \
+		IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__GPIO_3_6                                            \
+		IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20                                      \
+		IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6                                        \
+		IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7                                    \
+		IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2                                    \
+		IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2                                       \
+		IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9                           \
+		IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__GPIO_3_7                                            \
+		IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21                                      \
+		IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7                                        \
+		IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8                                    \
+		IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1                                    \
+		IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1                                       \
+		IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10                          \
+		IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__GPIO_3_8                                            \
+		IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22                                      \
+		IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8                                        \
+		IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9                                    \
+		IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0                                    \
+		IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0                                       \
+		IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11                          \
+		IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__GPIO_3_9                                            \
+		IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23                                      \
+		IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9                                        \
+		IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10                                  \
+		IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15                                     \
+		IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN                                  \
+		IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0)
+#define _MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12                         \
+		IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__GPIO_3_10                                          \
+		IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24                                     \
+		IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10                                      \
+		IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11                                  \
+		IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2                                      \
+		IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC                                    \
+		IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0)
+#define _MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13                         \
+		IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6                         \
+		IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__GPIO_3_11                                          \
+		IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25                                     \
+		IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11                                      \
+		IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12                                  \
+		IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3                                      \
+		IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC                                    \
+		IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0)
+#define _MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14                         \
+		IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3                         \
+		IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__GPIO_3_12                                          \
+		IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26                                     \
+		IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12                                      \
+		IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13                                  \
+		IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS                                     \
+		IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK                                    \
+		IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0)
+#define _MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15                         \
+		IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4                         \
+		IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__GPIO_3_13                                          \
+		IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27                                     \
+		IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13                                      \
+		IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14                                  \
+		IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS                                     \
+		IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK                                    \
+		IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16                         \
+		IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5                         \
+		IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__GPIO_3_14                                          \
+		IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28                                     \
+		IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14                                      \
+		IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15                                  \
+		IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1                                      \
+		IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4                                      \
+		IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17                         \
+		IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__GPIO_3_15                                          \
+		IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29                                     \
+		IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15                                      \
+		IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT                                     \
+		IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B                                  \
+		IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_WAIT__GPIO_5_0                                           \
+		IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30                                     \
+		IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25                                      \
+		IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK                                     \
+		IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16                                     \
+		IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_BCLK__GPIO_6_31                                          \
+		IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31                                     \
+		IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK                              \
+		IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK                              \
+		IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28                     \
+		IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0                        \
+		IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16                                      \
+		IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0                              \
+		IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15                                    \
+		IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15                                    \
+		IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC                                   \
+		IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29                        \
+		IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1                           \
+		IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__GPIO_4_17                                         \
+		IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1                                 \
+		IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2                                      \
+		IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2                                      \
+		IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD                                    \
+		IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30                         \
+		IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2                            \
+		IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__GPIO_4_18                                          \
+		IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2                                  \
+		IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9                             \
+		IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3                                      \
+		IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3                                      \
+		IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS                                   \
+		IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31                         \
+		IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3                            \
+		IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__GPIO_4_19                                          \
+		IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3                                  \
+		IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10                            \
+		IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4                                      \
+		IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4                                      \
+		IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD                                    \
+		IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__USDHC1_WP                                          \
+		IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD                                   \
+		IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__GPIO_4_20                                          \
+		IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4                                  \
+		IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11                            \
+		IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0                                 \
+		IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0                                 \
+		IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK                                      \
+		IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0                             \
+		IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN                              \
+		IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__GPIO_4_21                                        \
+		IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5                                \
+		IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1                                 \
+		IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1                                 \
+		IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI                                      \
+		IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1                             \
+		IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL                     \
+		IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__GPIO_4_22                                        \
+		IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6                                \
+		IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12                          \
+		IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2                                 \
+		IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2                                 \
+		IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO                                      \
+		IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2                             \
+		IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE                                  \
+		IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__GPIO_4_23                                        \
+		IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7                                \
+		IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13                          \
+		IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3                                 \
+		IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3                                 \
+		IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0                                       \
+		IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3                             \
+		IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR                             \
+		IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__GPIO_4_24                                        \
+		IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8                                \
+		IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14                          \
+		IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4                                 \
+		IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4                                 \
+		IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1                                       \
+		IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4                             \
+		IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB                               \
+		IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__GPIO_4_25                                        \
+		IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9                                \
+		IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15                          \
+		IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5                                 \
+		IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5                                 \
+		IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2                                       \
+		IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS                                 \
+		IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS                         \
+		IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__GPIO_4_26                                        \
+		IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10                               \
+		IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16                          \
+		IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6                                 \
+		IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6                                 \
+		IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3                                       \
+		IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC                                  \
+		IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE                        \
+		IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__GPIO_4_27                                        \
+		IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11                               \
+		IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17                          \
+		IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7                                 \
+		IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7                                 \
+		IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY                                       \
+		IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5                             \
+		IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0                       \
+		IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__GPIO_4_28                                        \
+		IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12                               \
+		IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18                          \
+		IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8                                 \
+		IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8                                 \
+		IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__PWM1_PWMO                                        \
+		IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B                                     \
+		IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1                       \
+		IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__GPIO_4_29                                        \
+		IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13                               \
+		IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19                          \
+		IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9                                 \
+		IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9                                 \
+		IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__PWM2_PWMO                                        \
+		IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B                                     \
+		IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2                       \
+		IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__GPIO_4_30                                        \
+		IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14                               \
+		IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20                          \
+		IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10                               \
+		IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10                               \
+		IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6                            \
+		IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3                      \
+		IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__GPIO_4_31                                       \
+		IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15                              \
+		IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21                         \
+		IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11                               \
+		IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11                               \
+		IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7                            \
+		IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4                      \
+		IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__GPIO_5_5                                        \
+		IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16                              \
+		IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22                         \
+		IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12                               \
+		IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12                               \
+		IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED                               \
+		IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5                      \
+		IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__GPIO_5_6                                        \
+		IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17                              \
+		IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23                         \
+		IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13                               \
+		IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13                               \
+		IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS                                \
+		IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0                      \
+		IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__GPIO_5_7                                        \
+		IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18                              \
+		IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24                         \
+		IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14                               \
+		IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14                               \
+		IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC                                 \
+		IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1                      \
+		IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT14__GPIO_5_8                                        \
+		IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19                              \
+		IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15                               \
+		IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15                               \
+		IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1                                      \
+		IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1                                      \
+		IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2                      \
+		IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__GPIO_5_9                                        \
+		IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20                              \
+		IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25                         \
+		IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16                               \
+		IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16                               \
+		IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI                                     \
+		IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC                                 \
+		IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0                           \
+		IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__GPIO_5_10                                       \
+		IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21                              \
+		IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26                         \
+		IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17                               \
+		IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17                               \
+		IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO                                     \
+		IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD                                 \
+		IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1                           \
+		IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__GPIO_5_11                                       \
+		IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22                              \
+		IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27                         \
+		IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18                               \
+		IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18                               \
+		IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0                                      \
+		IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS                                \
+		IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS                                \
+		IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__GPIO_5_12                                       \
+		IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23                              \
+		IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2                                  \
+		IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19                               \
+		IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19                               \
+		IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK                                     \
+		IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD                                 \
+		IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC                                 \
+		IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__GPIO_5_13                                       \
+		IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24                              \
+		IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3                                  \
+		IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20                               \
+		IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20                               \
+		IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK                                     \
+		IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC                                 \
+		IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7                      \
+		IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__GPIO_5_14                                       \
+		IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25                              \
+		IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28                         \
+		IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21                               \
+		IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21                               \
+		IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI                                     \
+		IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD                                 \
+		IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0                         \
+		IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__GPIO_5_15                                       \
+		IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26                              \
+		IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29                         \
+		IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22                               \
+		IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22                               \
+		IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO                                     \
+		IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS                                \
+		IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1                         \
+		IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__GPIO_5_16                                       \
+		IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27                              \
+		IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30                         \
+		IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23                               \
+		IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23                               \
+		IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0                                      \
+		IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD                                 \
+		IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2                         \
+		IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__GPIO_5_17                                       \
+		IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28                              \
+		IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31                         \
+		IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED                                 \
+		IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__ENET_MDIO                                         \
+		IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__ESAI1_SCKR                                        \
+		IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3                           \
+		IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT                              \
+		IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__GPIO_1_22                                         \
+		IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK                                       \
+		IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED                              \
+		IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK                                    \
+		IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR                                      \
+		IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4                        \
+		IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__GPIO_1_23                                      \
+		IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK                                    \
+		IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH                 \
+		IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_RX_ER__ENET_RX_ER                                       \
+		IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR                                       \
+		IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__SPDIF_IN1                                        \
+		IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0)
+#define _MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT                             \
+		IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__GPIO_1_24                                        \
+		IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__PHY_TDI                                          \
+		IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD                    \
+		IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED                               \
+		IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN                                      \
+		IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT                                      \
+		IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK                              \
+		IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__GPIO_1_25                                       \
+		IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__PHY_TDO                                         \
+		IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD                   \
+		IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_RXD1__MLB_MLBSIG                                        \
+		IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__ENET_RDATA_1                                      \
+		IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0)
+#define _MX6Q_PAD_ENET_RXD1__ESAI1_FST                                         \
+		IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT                              \
+		IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__GPIO_1_26                                         \
+		IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__PHY_TCK                                           \
+		IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET                 \
+		IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT                                    \
+		IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__ENET_RDATA_0                                      \
+		IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0)
+#define _MX6Q_PAD_ENET_RXD0__ESAI1_HCKT                                        \
+		IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__SPDIF_OUT1                                        \
+		IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__GPIO_1_27                                         \
+		IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__PHY_TMS                                           \
+		IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV                  \
+		IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED                                \
+		IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TX_EN__ENET_TX_EN                                       \
+		IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2                                    \
+		IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0)
+#define _MX6Q_PAD_ENET_TX_EN__GPIO_1_28                                        \
+		IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI                                     \
+		IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH                   \
+		IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_TXD1__MLB_MLBCLK                                        \
+		IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__ENET_TDATA_1                                      \
+		IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3                                     \
+		IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN                               \
+		IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__GPIO_1_29                                         \
+		IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO                                      \
+		IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD                     \
+		IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED                                 \
+		IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD0__ENET_TDATA_0                                      \
+		IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1                                     \
+		IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0)
+#define _MX6Q_PAD_ENET_TXD0__GPIO_1_30                                         \
+		IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK                                      \
+		IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD                     \
+		IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_MDC__MLB_MLBDAT                                         \
+		IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__ENET_MDC                                           \
+		IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0                                      \
+		IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN                                \
+		IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__GPIO_1_31                                          \
+		IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__SATA_PHY_TMS                                       \
+		IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET                  \
+		IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5                                 \
+		IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5                                   \
+		IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4                                   \
+		IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4                                 \
+		IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3                                 \
+		IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3                                   \
+		IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2                                 \
+		IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2                                   \
+		IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0                                       \
+		IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1                                       \
+		IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2                                       \
+		IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3                                       \
+		IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4                                       \
+		IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5                                       \
+		IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6                                       \
+		IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7                                       \
+		IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8                                       \
+		IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9                                       \
+		IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10                                     \
+		IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11                                     \
+		IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12                                     \
+		IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13                                     \
+		IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14                                     \
+		IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15                                     \
+		IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS                                      \
+		IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0                                     \
+		IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1                                     \
+		IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS                                      \
+		IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET                                  \
+		IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0                                 \
+		IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1                                 \
+		IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0                               \
+		IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2                                 \
+		IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0                               \
+		IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1                               \
+		IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1                               \
+		IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0                                 \
+		IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1                                 \
+		IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE                                    \
+		IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0                                       \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1                                       \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2                                       \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3                                       \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4                                       \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5                                       \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0                                 \
+		IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6                                       \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7                                       \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0                                   \
+		IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8                                       \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9                                       \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1                                 \
+		IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1                                   \
+		IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6                                 \
+		IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6                                   \
+		IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7                                 \
+		IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7                                   \
+		IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL0__ECSPI1_SCLK                                        \
+		IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0)
+#define _MX6Q_PAD_KEY_COL0__ENET_RDATA_3                                       \
+		IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0)
+#define _MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC                                    \
+		IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0)
+#define _MX6Q_PAD_KEY_COL0__KPP_COL_0                                          \
+		IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__UART4_TXD                                          \
+		IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__UART4_RXD                                          \
+		IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__GPIO_4_6                                           \
+		IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT                                     \
+		IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST                                     \
+		IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI                                        \
+		IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0)
+#define _MX6Q_PAD_KEY_ROW0__ENET_TDATA_3                                       \
+		IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD                                    \
+		IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0)
+#define _MX6Q_PAD_KEY_ROW0__KPP_ROW_0                                          \
+		IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__UART4_TXD                                          \
+		IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__UART4_RXD                                          \
+		IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0)
+#define _MX6Q_PAD_KEY_ROW0__GPIO_4_7                                           \
+		IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT                                     \
+		IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0                             \
+		IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL1__ECSPI1_MISO                                        \
+		IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0)
+#define _MX6Q_PAD_KEY_COL1__ENET_MDIO                                          \
+		IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0)
+#define _MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS                                   \
+		IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0)
+#define _MX6Q_PAD_KEY_COL1__KPP_COL_1                                          \
+		IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__UART5_TXD                                          \
+		IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__UART5_RXD                                          \
+		IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__GPIO_4_8                                           \
+		IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__USDHC1_VSELECT                                     \
+		IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1                             \
+		IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW1__ECSPI1_SS0                                         \
+		IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0)
+#define _MX6Q_PAD_KEY_ROW1__ENET_COL                                           \
+		IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD                                    \
+		IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0)
+#define _MX6Q_PAD_KEY_ROW1__KPP_ROW_1                                          \
+		IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__UART5_TXD                                          \
+		IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__UART5_RXD                                          \
+		IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0)
+#define _MX6Q_PAD_KEY_ROW1__GPIO_4_9                                           \
+		IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT                                     \
+		IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2                             \
+		IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL2__ECSPI1_SS1                                         \
+		IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0)
+#define _MX6Q_PAD_KEY_COL2__ENET_RDATA_2                                       \
+		IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0)
+#define _MX6Q_PAD_KEY_COL2__CAN1_TXCAN                                         \
+		IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__KPP_COL_2                                          \
+		IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__ENET_MDC                                           \
+		IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__GPIO_4_10                                          \
+		IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP                         \
+		IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3                             \
+		IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW2__ECSPI1_SS2                                         \
+		IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0)
+#define _MX6Q_PAD_KEY_ROW2__ENET_TDATA_2                                       \
+		IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__CAN1_RXCAN                                         \
+		IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__KPP_ROW_2                                          \
+		IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT                                     \
+		IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__GPIO_4_11                                          \
+		IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE                                   \
+		IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0)
+#define _MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4                             \
+		IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL3__ECSPI1_SS3                                         \
+		IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0)
+#define _MX6Q_PAD_KEY_COL3__ENET_CRS                                           \
+		IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL                                    \
+		IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0)
+#define _MX6Q_PAD_KEY_COL3__KPP_COL_3                                          \
+		IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL3__I2C2_SCL                                           \
+		IOMUX_PAD(0x05E0, 0x0210, 4 | IOMUX_CONFIG_SION, 0x08A0, 1, 0)
+#define _MX6Q_PAD_KEY_COL3__GPIO_4_12                                          \
+		IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL3__SPDIF_IN1                                          \
+		IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0)
+#define _MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5                             \
+		IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT                                     \
+		IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK                                  \
+		IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA                                    \
+		IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0)
+#define _MX6Q_PAD_KEY_ROW3__KPP_ROW_3                                          \
+		IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__I2C2_SDA                                           \
+		IOMUX_PAD(0x05E4, 0x0214, 4 | IOMUX_CONFIG_SION, 0x08A4, 1, 0)
+#define _MX6Q_PAD_KEY_ROW3__GPIO_4_13                                          \
+		IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT                                     \
+		IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6                             \
+		IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL4__CAN2_TXCAN                                         \
+		IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__IPU1_SISG_4                                        \
+		IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC                                   \
+		IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0)
+#define _MX6Q_PAD_KEY_COL4__KPP_COL_4                                          \
+		IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__UART5_CTS                                          \
+		IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__UART5_RTS                                          \
+		IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__GPIO_4_14                                          \
+		IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49                                 \
+		IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7                             \
+		IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW4__CAN2_RXCAN                                         \
+		IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__IPU1_SISG_5                                        \
+		IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR                                  \
+		IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__KPP_ROW_4                                          \
+		IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__UART5_CTS                                          \
+		IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0)
+#define _MX6Q_PAD_KEY_ROW4__GPIO_4_15                                          \
+		IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50                                 \
+		IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8                             \
+		IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_0__CCM_CLKO                                             \
+		IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_0__KPP_COL_5                                            \
+		IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0)
+#define _MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK                                    \
+		IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0)
+#define _MX6Q_PAD_GPIO_0__EPIT1_EPITO                                          \
+		IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_0__GPIO_1_0                                             \
+		IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR                                     \
+		IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5                           \
+		IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_1__ESAI1_SCKR                                           \
+		IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0)
+#define _MX6Q_PAD_GPIO_1__WDOG2_WDOG_B                                         \
+		IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_1__KPP_ROW_5                                            \
+		IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0)
+#define _MX6Q_PAD_GPIO_1__PWM2_PWMO                                            \
+		IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_1__GPIO_1_1                                             \
+		IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_1__USDHC1_CD                                            \
+		IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_1__SRC_TESTER_ACK                                       \
+		IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_9__ESAI1_FSR                                            \
+		IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0)
+#define _MX6Q_PAD_GPIO_9__WDOG1_WDOG_B                                         \
+		IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_9__KPP_COL_6                                            \
+		IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0)
+#define _MX6Q_PAD_GPIO_9__CCM_REF_EN_B                                         \
+		IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_9__PWM1_PWMO                                            \
+		IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_9__GPIO_1_9                                             \
+		IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_9__USDHC1_WP                                            \
+		IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0)
+#define _MX6Q_PAD_GPIO_9__SRC_EARLY_RST                                        \
+		IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_3__ESAI1_HCKR                                           \
+		IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0)
+#define _MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0                           \
+		IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_3__I2C3_SCL                                             \
+		IOMUX_PAD(0x05FC, 0x022C, 2 | IOMUX_CONFIG_SION, 0x08A8, 1, 0)
+#define _MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT                                \
+		IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_3__CCM_CLKO2                                            \
+		IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_3__GPIO_1_3                                             \
+		IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC                                      \
+		IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0)
+#define _MX6Q_PAD_GPIO_3__MLB_MLBCLK                                           \
+		IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0)
+
+#define _MX6Q_PAD_GPIO_6__ESAI1_SCKT                                           \
+		IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0)
+#define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1                           \
+		IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_6__I2C3_SDA                                             \
+		IOMUX_PAD(0x0600, 0x0230, 2 | IOMUX_CONFIG_SION, 0x08AC, 1, 0)
+#define _MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0                                        \
+		IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB                                      \
+		IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_6__GPIO_1_6                                             \
+		IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_6__USDHC2_LCTL                                          \
+		IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_6__MLB_MLBSIG                                           \
+		IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0)
+
+#define _MX6Q_PAD_GPIO_2__ESAI1_FST                                            \
+		IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0)
+#define _MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2                           \
+		IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__KPP_ROW_6                                            \
+		IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0)
+#define _MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1                                        \
+		IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0                                  \
+		IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__GPIO_1_2                                             \
+		IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__USDHC2_WP                                            \
+		IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__MLB_MLBDAT                                           \
+		IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0)
+
+#define _MX6Q_PAD_GPIO_4__ESAI1_HCKT                                           \
+		IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0)
+#define _MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3                           \
+		IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__KPP_COL_7                                            \
+		IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0)
+#define _MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2                                        \
+		IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1                                  \
+		IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__GPIO_1_4                                             \
+		IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__USDHC2_CD                                            \
+		IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED                      \
+		IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3                                        \
+		IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0)
+#define _MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4                           \
+		IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_5__KPP_ROW_7                                            \
+		IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0)
+#define _MX6Q_PAD_GPIO_5__CCM_CLKO                                             \
+		IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2                                  \
+		IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_5__GPIO_1_5                                             \
+		IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_5__I2C3_SCL                                             \
+		IOMUX_PAD(0x060C, 0x023C, 6 | IOMUX_CONFIG_SION, 0x08A8, 2, 0)
+#define _MX6Q_PAD_GPIO_5__CHEETAH_EVENTI                                       \
+		IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1                                        \
+		IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0)
+#define _MX6Q_PAD_GPIO_7__ECSPI5_RDY                                           \
+		IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__EPIT1_EPITO                                          \
+		IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__CAN1_TXCAN                                           \
+		IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__UART2_TXD                                            \
+		IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__UART2_RXD                                            \
+		IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0)
+#define _MX6Q_PAD_GPIO_7__GPIO_1_7                                             \
+		IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__SPDIF_PLOCK                                          \
+		IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE                              \
+		IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0                                        \
+		IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0)
+#define _MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT                                \
+		IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__EPIT2_EPITO                                          \
+		IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__CAN1_RXCAN                                           \
+		IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0)
+#define _MX6Q_PAD_GPIO_8__UART2_TXD                                            \
+		IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__UART2_RXD                                            \
+		IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0)
+#define _MX6Q_PAD_GPIO_8__GPIO_1_8                                             \
+		IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__SPDIF_SRCLK                                          \
+		IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP                          \
+		IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2                                       \
+		IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0)
+#define _MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN                                 \
+		IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT                        \
+		IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0)
+#define _MX6Q_PAD_GPIO_16__USDHC1_LCTL                                         \
+		IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_16__SPDIF_IN1                                           \
+		IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0)
+#define _MX6Q_PAD_GPIO_16__GPIO_7_11                                           \
+		IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_16__I2C3_SDA                                            \
+		IOMUX_PAD(0x0618, 0x0248, 6 | IOMUX_CONFIG_SION, 0x08AC, 2, 0)
+#define _MX6Q_PAD_GPIO_16__SJC_DE_B                                            \
+		IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_17__ESAI1_TX0                                           \
+		IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0)
+#define _MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN                                 \
+		IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_17__CCM_PMIC_RDY                                        \
+		IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0)
+#define _MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0                               \
+		IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0)
+#define _MX6Q_PAD_GPIO_17__SPDIF_OUT1                                          \
+		IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_17__GPIO_7_12                                           \
+		IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_17__SJC_JTAG_ACT                                        \
+		IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_18__ESAI1_TX1                                           \
+		IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0)
+#define _MX6Q_PAD_GPIO_18__ENET_RX_CLK                                         \
+		IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0)
+#define _MX6Q_PAD_GPIO_18__USDHC3_VSELECT                                      \
+		IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1                               \
+		IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0)
+#define _MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK                                   \
+		IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0)
+#define _MX6Q_PAD_GPIO_18__GPIO_7_13                                           \
+		IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL                      \
+		IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST                                      \
+		IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_19__KPP_COL_5                                           \
+		IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0)
+#define _MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT                                \
+		IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__SPDIF_OUT1                                          \
+		IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__CCM_CLKO                                            \
+		IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__ECSPI1_RDY                                          \
+		IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__GPIO_4_5                                            \
+		IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__ENET_TX_ER                                          \
+		IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__SRC_INT_BOOT                                        \
+		IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK                                \
+		IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12                \
+		IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0                                 \
+		IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18                                       \
+		IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29                              \
+		IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO                                  \
+		IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC                                   \
+		IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13                  \
+		IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__CCM_CLKO                                          \
+		IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1                                   \
+		IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__GPIO_5_19                                         \
+		IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30                                \
+		IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL                                     \
+		IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN                              \
+		IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0                                  \
+		IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14               \
+		IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2                                \
+		IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20                                      \
+		IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31                             \
+		IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK                                  \
+		IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC                                  \
+		IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1                                    \
+		IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15                 \
+		IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3                                  \
+		IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__GPIO_5_21                                        \
+		IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32                               \
+		IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0                                  \
+		IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4                                     \
+		IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2                                     \
+		IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK                                       \
+		IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT4__KPP_COL_5                                         \
+		IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC                                   \
+		IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__GPIO_5_22                                         \
+		IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43                                \
+		IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1                                   \
+		IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5                                     \
+		IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3                                     \
+		IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI                                       \
+		IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT5__KPP_ROW_5                                         \
+		IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD                                   \
+		IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__GPIO_5_23                                         \
+		IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44                                \
+		IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2                                   \
+		IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6                                     \
+		IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4                                     \
+		IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO                                       \
+		IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT6__KPP_COL_6                                         \
+		IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS                                  \
+		IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__GPIO_5_24                                         \
+		IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45                                \
+		IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3                                   \
+		IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7                                     \
+		IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5                                     \
+		IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0                                        \
+		IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT7__KPP_ROW_6                                         \
+		IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD                                   \
+		IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__GPIO_5_25                                         \
+		IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46                                \
+		IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4                                   \
+		IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8                                     \
+		IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6                                     \
+		IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK                                       \
+		IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT8__KPP_COL_7                                         \
+		IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT8__I2C1_SDA                                          \
+		IOMUX_PAD(0x0648, 0x0278, 4 | IOMUX_CONFIG_SION, 0x089C, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT8__GPIO_5_26                                         \
+		IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47                                \
+		IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5                                   \
+		IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9                                     \
+		IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7                                     \
+		IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI                                       \
+		IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT9__KPP_ROW_7                                         \
+		IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT9__I2C1_SCL                                          \
+		IOMUX_PAD(0x064C, 0x027C, 4 | IOMUX_CONFIG_SION, 0x0898, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT9__GPIO_5_27                                         \
+		IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48                                \
+		IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6                                   \
+		IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10                                   \
+		IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC                                  \
+		IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO                                      \
+		IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT10__UART1_TXD                                        \
+		IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__UART1_RXD                                        \
+		IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4                                  \
+		IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__GPIO_5_28                                        \
+		IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33                               \
+		IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7                                  \
+		IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11                                   \
+		IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS                                 \
+		IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0                                       \
+		IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT11__UART1_TXD                                        \
+		IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__UART1_RXD                                        \
+		IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5                                  \
+		IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__GPIO_5_29                                        \
+		IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34                               \
+		IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8                                  \
+		IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12                                   \
+		IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8                                    \
+		IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16                 \
+		IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__UART4_TXD                                        \
+		IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__UART4_RXD                                        \
+		IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6                                  \
+		IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__GPIO_5_30                                        \
+		IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35                               \
+		IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9                                  \
+		IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13                                   \
+		IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9                                    \
+		IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17                 \
+		IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__UART4_TXD                                        \
+		IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__UART4_RXD                                        \
+		IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7                                  \
+		IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__GPIO_5_31                                        \
+		IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36                               \
+		IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10                                 \
+		IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14                                   \
+		IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10                                   \
+		IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18                 \
+		IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__UART5_TXD                                        \
+		IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__UART5_RXD                                        \
+		IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8                                  \
+		IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__GPIO_6_0                                         \
+		IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37                               \
+		IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11                                 \
+		IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15                                   \
+		IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11                                   \
+		IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19                 \
+		IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__UART5_TXD                                        \
+		IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__UART5_RXD                                        \
+		IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9                                  \
+		IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__GPIO_6_1                                         \
+		IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38                               \
+		IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12                                 \
+		IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16                                   \
+		IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12                                   \
+		IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20                 \
+		IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__UART4_CTS                                        \
+		IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__UART4_RTS                                        \
+		IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10                                 \
+		IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__GPIO_6_2                                         \
+		IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39                               \
+		IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13                                 \
+		IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17                                   \
+		IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13                                   \
+		IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21                 \
+		IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__UART4_CTS                                        \
+		IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11                                 \
+		IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__GPIO_6_3                                         \
+		IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40                               \
+		IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14                                 \
+		IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18                                   \
+		IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14                                   \
+		IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22                 \
+		IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__UART5_CTS                                        \
+		IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__UART5_RTS                                        \
+		IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12                                 \
+		IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__GPIO_6_4                                         \
+		IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41                               \
+		IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15                                 \
+		IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19                                   \
+		IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15                                   \
+		IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23                 \
+		IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__UART5_CTS                                        \
+		IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13                                 \
+		IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__GPIO_6_5                                         \
+		IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42                               \
+		IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9                            \
+		IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TMS__SJC_TMS                                            \
+		IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_MOD__SJC_MOD                                            \
+		IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB                                        \
+		IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TDI__SJC_TDI                                            \
+		IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TCK__SJC_TCK                                            \
+		IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TDO__SJC_TDO                                            \
+		IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3                                   \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2                                   \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK                                   \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1                                   \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0                                   \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3                                   \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK                                   \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2                                   \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1                                   \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0                                   \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1                             \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM               \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ                            \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_POR_B__SRC_POR_B                                             \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1                                  \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RESET_IN_B__SRC_RESET_B                                      \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0                                  \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_TEST_MODE__TCU_TEST_MODE                                     \
+		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT7__USDHC3_DAT7                                        \
+		IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__UART1_TXD                                          \
+		IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__UART1_RXD                                          \
+		IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0)
+#define _MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24                   \
+		IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0                               \
+		IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0                               \
+		IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__GPIO_6_17                                          \
+		IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12                          \
+		IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV                   \
+		IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT6__USDHC3_DAT6                                        \
+		IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__UART1_TXD                                          \
+		IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__UART1_RXD                                          \
+		IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0)
+#define _MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25                   \
+		IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1                               \
+		IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1                               \
+		IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__GPIO_6_18                                          \
+		IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13                          \
+		IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10                             \
+		IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT5__USDHC3_DAT5                                        \
+		IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__UART2_TXD                                          \
+		IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__UART2_RXD                                          \
+		IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0)
+#define _MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26                   \
+		IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2                               \
+		IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2                               \
+		IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__GPIO_7_0                                           \
+		IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14                          \
+		IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11                             \
+		IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT4__USDHC3_DAT4                                        \
+		IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__UART2_TXD                                          \
+		IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__UART2_RXD                                          \
+		IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0)
+#define _MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27                   \
+		IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3                               \
+		IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3                               \
+		IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__GPIO_7_1                                           \
+		IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15                          \
+		IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12                             \
+		IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_CMD__USDHC3_CMD                                          \
+		IOMUX_PAD(0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__UART2_CTS                                           \
+		IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0)
+#define _MX6Q_PAD_SD3_CMD__CAN1_TXCAN                                          \
+		IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4                                \
+		IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4                                \
+		IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__GPIO_7_2                                            \
+		IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16                           \
+		IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13                              \
+		IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_CLK__USDHC3_CLK                                          \
+		IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__UART2_CTS                                           \
+		IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__UART2_RTS                                           \
+		IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0)
+#define _MX6Q_PAD_SD3_CLK__CAN1_RXCAN                                          \
+		IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0)
+#define _MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5                                \
+		IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5                                \
+		IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__GPIO_7_3                                            \
+		IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17                           \
+		IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14                              \
+		IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT0__USDHC3_DAT0                                        \
+		IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__UART1_CTS                                          \
+		IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0)
+#define _MX6Q_PAD_SD3_DAT0__CAN2_TXCAN                                         \
+		IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6                               \
+		IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6                               \
+		IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__GPIO_7_4                                           \
+		IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18                          \
+		IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15                             \
+		IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT1__USDHC3_DAT1                                        \
+		IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__UART1_CTS                                          \
+		IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__UART1_RTS                                          \
+		IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0)
+#define _MX6Q_PAD_SD3_DAT1__CAN2_RXCAN                                         \
+		IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0)
+#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7                               \
+		IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7                               \
+		IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__GPIO_7_5                                           \
+		IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19                          \
+		IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0                              \
+		IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT2__USDHC3_DAT2                                        \
+		IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28                   \
+		IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8                               \
+		IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8                               \
+		IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__GPIO_7_6                                           \
+		IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20                          \
+		IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1                              \
+		IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT3__USDHC3_DAT3                                        \
+		IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__UART3_CTS                                          \
+		IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0)
+#define _MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29                   \
+		IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9                               \
+		IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9                               \
+		IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__GPIO_7_7                                           \
+		IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21                          \
+		IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2                              \
+		IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_RST__USDHC3_RST                                          \
+		IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__UART3_CTS                                           \
+		IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__UART3_RTS                                           \
+		IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0)
+#define _MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30                    \
+		IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10                               \
+		IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10                               \
+		IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__GPIO_7_8                                            \
+		IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22                           \
+		IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3                               \
+		IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CLE__RAWNAND_CLE                                       \
+		IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__IPU2_SISG_4                                       \
+		IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31                  \
+		IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11                             \
+		IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11                             \
+		IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__GPIO_6_7                                          \
+		IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23                         \
+		IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0                                    \
+		IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_ALE__RAWNAND_ALE                                       \
+		IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__USDHC4_RST                                        \
+		IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0                   \
+		IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12                             \
+		IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12                             \
+		IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__GPIO_6_8                                          \
+		IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24                         \
+		IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1                                    \
+		IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN                                   \
+		IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5                                      \
+		IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1                  \
+		IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13                            \
+		IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13                            \
+		IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__GPIO_6_9                                         \
+		IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32                       \
+		IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0                           \
+		IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_RB0__RAWNAND_READY0                                    \
+		IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1                                     \
+		IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2                   \
+		IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14                             \
+		IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14                             \
+		IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__GPIO_6_10                                         \
+		IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33                        \
+		IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1                            \
+		IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N                                      \
+		IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15                             \
+		IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15                             \
+		IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS0__GPIO_6_11                                         \
+		IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2                            \
+		IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N                                      \
+		IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT                                    \
+		IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT                                    \
+		IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3                   \
+		IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__GPIO_6_14                                         \
+		IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT                          \
+		IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N                                      \
+		IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__IPU1_SISG_0                                       \
+		IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__ESAI1_TX0                                         \
+		IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0)
+#define _MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE                                     \
+		IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__CCM_CLKO2                                         \
+		IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__GPIO_6_15                                         \
+		IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__IPU2_SISG_0                                       \
+		IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N                                      \
+		IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__IPU1_SISG_1                                       \
+		IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__ESAI1_TX1                                         \
+		IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0)
+#define _MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26                                    \
+		IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4                   \
+		IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__GPIO_6_16                                         \
+		IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__IPU2_SISG_1                                       \
+		IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__TPSMP_CLK                                         \
+		IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_CMD__USDHC4_CMD                                          \
+		IOMUX_PAD(0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__RAWNAND_RDN                                         \
+		IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__UART3_TXD                                           \
+		IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__UART3_RXD                                           \
+		IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0)
+#define _MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5                     \
+		IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__GPIO_7_9                                            \
+		IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR                                     \
+		IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_CLK__USDHC4_CLK                                          \
+		IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CLK__RAWNAND_WRN                                         \
+		IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CLK__UART3_TXD                                           \
+		IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CLK__UART3_RXD                                           \
+		IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0)
+#define _MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6                     \
+		IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CLK__GPIO_7_10                                           \
+		IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D0__RAWNAND_D0                                         \
+		IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__USDHC1_DAT4                                        \
+		IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0                              \
+		IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16                              \
+		IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16                              \
+		IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__GPIO_2_0                                           \
+		IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0                                \
+		IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0                                \
+		IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D1__RAWNAND_D1                                         \
+		IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__USDHC1_DAT5                                        \
+		IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1                              \
+		IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17                              \
+		IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17                              \
+		IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__GPIO_2_1                                           \
+		IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1                                \
+		IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1                                \
+		IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D2__RAWNAND_D2                                         \
+		IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__USDHC1_DAT6                                        \
+		IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2                              \
+		IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18                              \
+		IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18                              \
+		IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__GPIO_2_2                                           \
+		IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2                                \
+		IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2                                \
+		IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D3__RAWNAND_D3                                         \
+		IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__USDHC1_DAT7                                        \
+		IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3                              \
+		IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19                              \
+		IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19                              \
+		IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__GPIO_2_3                                           \
+		IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3                                \
+		IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3                                \
+		IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D4__RAWNAND_D4                                         \
+		IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__USDHC2_DAT4                                        \
+		IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4                              \
+		IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20                              \
+		IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20                              \
+		IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__GPIO_2_4                                           \
+		IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4                                \
+		IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4                                \
+		IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D5__RAWNAND_D5                                         \
+		IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__USDHC2_DAT5                                        \
+		IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5                              \
+		IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21                              \
+		IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21                              \
+		IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__GPIO_2_5                                           \
+		IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5                                \
+		IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5                                \
+		IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D6__RAWNAND_D6                                         \
+		IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__USDHC2_DAT6                                        \
+		IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6                              \
+		IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22                              \
+		IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22                              \
+		IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__GPIO_2_6                                           \
+		IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6                                \
+		IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6                                \
+		IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D7__RAWNAND_D7                                         \
+		IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__USDHC2_DAT7                                        \
+		IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7                              \
+		IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23                              \
+		IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23                              \
+		IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__GPIO_2_7                                           \
+		IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7                                \
+		IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7                                \
+		IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT0__RAWNAND_D8                                         \
+		IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__USDHC4_DAT0                                        \
+		IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__RAWNAND_DQS                                        \
+		IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24                              \
+		IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24                              \
+		IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__GPIO_2_8                                           \
+		IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8                                \
+		IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8                                \
+		IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT1__RAWNAND_D9                                         \
+		IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__USDHC4_DAT1                                        \
+		IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__PWM3_PWMO                                          \
+		IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25                              \
+		IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25                              \
+		IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__GPIO_2_9                                           \
+		IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9                                \
+		IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9                                \
+		IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT2__RAWNAND_D10                                        \
+		IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__USDHC4_DAT2                                        \
+		IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__PWM4_PWMO                                          \
+		IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26                              \
+		IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26                              \
+		IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__GPIO_2_10                                          \
+		IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10                               \
+		IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10                               \
+		IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT3__RAWNAND_D11                                        \
+		IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__USDHC4_DAT3                                        \
+		IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27                              \
+		IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27                              \
+		IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__GPIO_2_11                                          \
+		IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11                               \
+		IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11                               \
+		IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT4__RAWNAND_D12                                        \
+		IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__USDHC4_DAT4                                        \
+		IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__UART2_TXD                                          \
+		IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__UART2_RXD                                          \
+		IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0)
+#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28                              \
+		IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28                              \
+		IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__GPIO_2_12                                          \
+		IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12                               \
+		IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12                               \
+		IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT5__RAWNAND_D13                                        \
+		IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__USDHC4_DAT5                                        \
+		IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__UART2_CTS                                          \
+		IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__UART2_RTS                                          \
+		IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0)
+#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29                              \
+		IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29                              \
+		IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__GPIO_2_13                                          \
+		IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13                               \
+		IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13                               \
+		IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT6__RAWNAND_D14                                        \
+		IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__USDHC4_DAT6                                        \
+		IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__UART2_CTS                                          \
+		IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0)
+#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30                              \
+		IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30                              \
+		IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__GPIO_2_14                                          \
+		IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14                               \
+		IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14                               \
+		IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT7__RAWNAND_D15                                        \
+		IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__USDHC4_DAT7                                        \
+		IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__UART2_TXD                                          \
+		IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__UART2_RXD                                          \
+		IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0)
+#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31                              \
+		IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31                              \
+		IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__GPIO_2_15                                          \
+		IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15                               \
+		IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15                               \
+		IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_DAT1__USDHC1_DAT1                                        \
+		IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__ECSPI5_SS0                                         \
+		IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0)
+#define _MX6Q_PAD_SD1_DAT1__PWM3_PWMO                                          \
+		IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__GPT_CAPIN2                                         \
+		IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7                    \
+		IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__GPIO_1_17                                          \
+		IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0                                  \
+		IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8                              \
+		IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_DAT0__USDHC1_DAT0                                        \
+		IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__ECSPI5_MISO                                        \
+		IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0)
+#define _MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS                           \
+		IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__GPT_CAPIN1                                         \
+		IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8                    \
+		IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__GPIO_1_16                                          \
+		IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1                                  \
+		IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7                              \
+		IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_DAT3__USDHC1_DAT3                                        \
+		IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__ECSPI5_SS2                                         \
+		IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3                                        \
+		IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__PWM1_PWMO                                          \
+		IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B                                       \
+		IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__GPIO_1_21                                          \
+		IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB                               \
+		IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6                              \
+		IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_CMD__USDHC1_CMD                                          \
+		IOMUX_PAD(0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__ECSPI5_MOSI                                         \
+		IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__PWM4_PWMO                                           \
+		IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__GPT_CMPOUT1                                         \
+		IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__GPIO_1_18                                           \
+		IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5                               \
+		IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_DAT2__USDHC1_DAT2                                        \
+		IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__ECSPI5_SS1                                         \
+		IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0)
+#define _MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2                                        \
+		IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__PWM2_PWMO                                          \
+		IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B                                       \
+		IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__GPIO_1_19                                          \
+		IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB                               \
+		IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4                              \
+		IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_CLK__USDHC1_CLK                                          \
+		IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__ECSPI5_SCLK                                         \
+		IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT                                      \
+		IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__GPT_CLKIN                                           \
+		IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__GPIO_1_20                                           \
+		IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__PHY_DTB_0                                           \
+		IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0                                      \
+		IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_CLK__USDHC2_CLK                                          \
+		IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CLK__ECSPI5_SCLK                                         \
+		IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0)
+#define _MX6Q_PAD_SD2_CLK__KPP_COL_5                                           \
+		IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0)
+#define _MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS                                    \
+		IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0)
+#define _MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9                     \
+		IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CLK__GPIO_1_10                                           \
+		IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CLK__PHY_DTB_1                                           \
+		IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1                                      \
+		IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_CMD__USDHC2_CMD                                          \
+		IOMUX_PAD(0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CMD__ECSPI5_MOSI                                         \
+		IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0)
+#define _MX6Q_PAD_SD2_CMD__KPP_ROW_5                                           \
+		IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0)
+#define _MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC                                     \
+		IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0)
+#define _MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10                    \
+		IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CMD__GPIO_1_11                                           \
+		IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_DAT3__USDHC2_DAT3                                        \
+		IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__ECSPI5_SS3                                         \
+		IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__KPP_COL_6                                          \
+		IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0)
+#define _MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC                                    \
+		IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0)
+#define _MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11                   \
+		IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__GPIO_1_12                                          \
+		IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__SJC_DONE                                           \
+		IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3                              \
+		IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0)
+
+#define  MX6Q_PAD_SD2_DAT1__USDHC2_DAT1                          (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT1__ECSPI5_SS0                           (_MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2                       (_MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS                     (_MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT1__KPP_COL_7                            (_MX6Q_PAD_SD2_DAT1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT1__GPIO_1_14                            (_MX6Q_PAD_SD2_DAT1__GPIO_1_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT1__CCM_WAIT                             (_MX6Q_PAD_SD2_DAT1__CCM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0                (_MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD2_DAT2__USDHC2_DAT2                          (_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT2__ECSPI5_SS1                           (_MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3                       (_MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD                      (_MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT2__KPP_ROW_6                            (_MX6Q_PAD_SD2_DAT2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT2__GPIO_1_13                            (_MX6Q_PAD_SD2_DAT2__GPIO_1_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT2__CCM_STOP                             (_MX6Q_PAD_SD2_DAT2__CCM_STOP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1                (_MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD2_DAT0__USDHC2_DAT0                          (_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT0__ECSPI5_MISO                          (_MX6Q_PAD_SD2_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD                      (_MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT0__KPP_ROW_7                            (_MX6Q_PAD_SD2_DAT0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT0__GPIO_1_15                            (_MX6Q_PAD_SD2_DAT0__GPIO_1_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT                       (_MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2                (_MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA                      (_MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC                      (_MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK                  (_MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TXC__GPIO_6_19                           (_MX6Q_PAD_RGMII_TXC__GPIO_6_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0            (_MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT               (_MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY              (_MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0                      (_MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TD0__GPIO_6_20                           (_MX6Q_PAD_RGMII_TD0__GPIO_6_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1            (_MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG               (_MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1                      (_MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TD1__GPIO_6_21                           (_MX6Q_PAD_RGMII_TD1__GPIO_6_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2            (_MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP                        (_MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA               (_MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2                      (_MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TD2__GPIO_6_22                           (_MX6Q_PAD_RGMII_TD2__GPIO_6_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3            (_MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP                        (_MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE               (_MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3                      (_MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TD3__GPIO_6_23                           (_MX6Q_PAD_RGMII_TD3__GPIO_6_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4            (_MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA                   (_MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL                (_MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24                        (_MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5         (_MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY              (_MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0                      (_MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_RD0__GPIO_6_25                           (_MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6            (_MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE                 (_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL                (_MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26                        (_MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7         (_MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT     (_MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG               (_MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1                      (_MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_RD1__GPIO_6_27                           (_MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8            (_MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_RD1__SJC_FAIL                            (_MX6Q_PAD_RGMII_RD1__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA               (_MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2                      (_MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_RD2__GPIO_6_28                           (_MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9            (_MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE               (_MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3                      (_MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_RD3__GPIO_6_29                           (_MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10           (_MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE                    (_MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC                      (_MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_RXC__GPIO_6_30                           (_MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11           (_MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25                        (_MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A25__ECSPI4_SS1                            (_MX6Q_PAD_EIM_A25__ECSPI4_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A25__ECSPI2_RDY                            (_MX6Q_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12                        (_MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS                        (_MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A25__GPIO_5_2                              (_MX6Q_PAD_EIM_A25__GPIO_5_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE                      (_MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0               (_MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2                        (_MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB2__ECSPI1_SS0                            (_MX6Q_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK                       (_MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19                        (_MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL                       (_MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB2__GPIO_2_30                             (_MX6Q_PAD_EIM_EB2__GPIO_2_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB2__I2C2_SCL                              (_MX6Q_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30                         (_MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16                        (_MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D16__ECSPI1_SCLK                           (_MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5                         (_MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18                        (_MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA                       (_MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D16__GPIO_3_16                             (_MX6Q_PAD_EIM_D16__GPIO_3_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D16__I2C2_SDA                              (_MX6Q_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17                        (_MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D17__ECSPI1_MISO                           (_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6                         (_MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK                      (_MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT                        (_MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D17__GPIO_3_17                             (_MX6Q_PAD_EIM_D17__GPIO_3_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D17__I2C3_SCL                              (_MX6Q_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1               (_MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18                        (_MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D18__ECSPI1_MOSI                           (_MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7                         (_MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17                        (_MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS                        (_MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D18__GPIO_3_18                             (_MX6Q_PAD_EIM_D18__GPIO_3_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D18__I2C3_SDA                              (_MX6Q_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2               (_MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19                        (_MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D19__ECSPI1_SS1                            (_MX6Q_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8                         (_MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16                        (_MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D19__UART1_CTS                             (_MX6Q_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D19__GPIO_3_19                             (_MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D19__EPIT1_EPITO                           (_MX6Q_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP                  (_MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20                        (_MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D20__ECSPI4_SS0                            (_MX6Q_PAD_EIM_D20__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16                        (_MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15                        (_MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D20__UART1_CTS                             (_MX6Q_PAD_EIM_D20__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D20__UART1_RTS                             (_MX6Q_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D20__GPIO_3_20                             (_MX6Q_PAD_EIM_D20__GPIO_3_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D20__EPIT2_EPITO                           (_MX6Q_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21                        (_MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D21__ECSPI4_SCLK                           (_MX6Q_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17                        (_MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11                        (_MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC                      (_MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D21__GPIO_3_21                             (_MX6Q_PAD_EIM_D21__GPIO_3_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D21__I2C1_SCL                              (_MX6Q_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D21__SPDIF_IN1                             (_MX6Q_PAD_EIM_D21__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22                        (_MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D22__ECSPI4_MISO                           (_MX6Q_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1                         (_MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10                        (_MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR                     (_MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D22__GPIO_3_22                             (_MX6Q_PAD_EIM_D22__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D22__SPDIF_OUT1                            (_MX6Q_PAD_EIM_D22__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE                 (_MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23                        (_MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS                        (_MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D23__UART3_CTS                             (_MX6Q_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D23__UART1_DCD                             (_MX6Q_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN                     (_MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D23__GPIO_3_23                             (_MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2                         (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14                        (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3                        (_MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB3__ECSPI4_RDY                            (_MX6Q_PAD_EIM_EB3__ECSPI4_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB3__UART3_CTS                             (_MX6Q_PAD_EIM_EB3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB3__UART3_RTS                             (_MX6Q_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB3__UART1_RI                              (_MX6Q_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC                       (_MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB3__GPIO_2_31                             (_MX6Q_PAD_EIM_EB3__GPIO_2_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3                         (_MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31                         (_MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24                        (_MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D24__ECSPI4_SS2                            (_MX6Q_PAD_EIM_D24__ECSPI4_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D24__UART3_TXD                             (_MX6Q_PAD_EIM_D24__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D24__UART3_RXD                             (_MX6Q_PAD_EIM_D24__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D24__ECSPI1_SS2                            (_MX6Q_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D24__ECSPI2_SS2                            (_MX6Q_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D24__GPIO_3_24                             (_MX6Q_PAD_EIM_D24__GPIO_3_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS                      (_MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D24__UART1_DTR                             (_MX6Q_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25                        (_MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D25__ECSPI4_SS3                            (_MX6Q_PAD_EIM_D25__ECSPI4_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D25__UART3_TXD                             (_MX6Q_PAD_EIM_D25__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D25__UART3_RXD                             (_MX6Q_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D25__ECSPI1_SS3                            (_MX6Q_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D25__ECSPI2_SS3                            (_MX6Q_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D25__GPIO_3_25                             (_MX6Q_PAD_EIM_D25__GPIO_3_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC                       (_MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D25__UART1_DSR                             (_MX6Q_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26                        (_MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11                        (_MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1                         (_MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14                        (_MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D26__UART2_TXD                             (_MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D26__UART2_RXD                             (_MX6Q_PAD_EIM_D26__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D26__GPIO_3_26                             (_MX6Q_PAD_EIM_D26__GPIO_3_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D26__IPU1_SISG_2                           (_MX6Q_PAD_EIM_D26__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22                     (_MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27                        (_MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13                        (_MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0                         (_MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13                        (_MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D27__UART2_TXD                             (_MX6Q_PAD_EIM_D27__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D27__UART2_RXD                             (_MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D27__GPIO_3_27                             (_MX6Q_PAD_EIM_D27__GPIO_3_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D27__IPU1_SISG_3                           (_MX6Q_PAD_EIM_D27__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23                     (_MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28                        (_MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D28__I2C1_SDA                              (_MX6Q_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D28__ECSPI4_MOSI                           (_MX6Q_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12                        (_MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D28__UART2_CTS                             (_MX6Q_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D28__GPIO_3_28                             (_MX6Q_PAD_EIM_D28__GPIO_3_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG                         (_MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13                        (_MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29                        (_MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15                        (_MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D29__ECSPI4_SS0                            (_MX6Q_PAD_EIM_D29__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D29__UART2_CTS                             (_MX6Q_PAD_EIM_D29__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D29__UART2_RTS                             (_MX6Q_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D29__GPIO_3_29                             (_MX6Q_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC                       (_MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14                        (_MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30                        (_MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21                     (_MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11                        (_MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3                         (_MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D30__UART3_CTS                             (_MX6Q_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D30__GPIO_3_30                             (_MX6Q_PAD_EIM_D30__GPIO_3_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC                       (_MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0                (_MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31                        (_MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20                     (_MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12                        (_MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2                         (_MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D31__UART3_CTS                             (_MX6Q_PAD_EIM_D31__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D31__UART3_RTS                             (_MX6Q_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D31__GPIO_3_31                             (_MX6Q_PAD_EIM_D31__GPIO_3_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR                      (_MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1                (_MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24                        (_MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19                     (_MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19                        (_MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A24__IPU2_SISG_2                           (_MX6Q_PAD_EIM_A24__IPU2_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A24__IPU1_SISG_2                           (_MX6Q_PAD_EIM_A24__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A24__GPIO_5_4                              (_MX6Q_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2                (_MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A24__SRC_BT_CFG_24                         (_MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23                        (_MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18                     (_MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18                        (_MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A23__IPU2_SISG_3                           (_MX6Q_PAD_EIM_A23__IPU2_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A23__IPU1_SISG_3                           (_MX6Q_PAD_EIM_A23__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A23__GPIO_6_6                              (_MX6Q_PAD_EIM_A23__GPIO_6_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3                (_MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A23__SRC_BT_CFG_23                         (_MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22                        (_MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17                     (_MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17                        (_MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A22__GPIO_2_16                             (_MX6Q_PAD_EIM_A22__GPIO_2_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A22__TPSMP_HDATA_0                         (_MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A22__SRC_BT_CFG_22                         (_MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21                        (_MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16                     (_MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16                        (_MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A21__RESERVED_RESERVED                     (_MX6Q_PAD_EIM_A21__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18            (_MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A21__GPIO_2_17                             (_MX6Q_PAD_EIM_A21__GPIO_2_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A21__TPSMP_HDATA_1                         (_MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A21__SRC_BT_CFG_21                         (_MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20                        (_MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15                     (_MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15                        (_MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A20__RESERVED_RESERVED                     (_MX6Q_PAD_EIM_A20__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19            (_MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A20__GPIO_2_18                             (_MX6Q_PAD_EIM_A20__GPIO_2_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A20__TPSMP_HDATA_2                         (_MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A20__SRC_BT_CFG_20                         (_MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19                        (_MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14                     (_MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14                        (_MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A19__RESERVED_RESERVED                     (_MX6Q_PAD_EIM_A19__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20            (_MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A19__GPIO_2_19                             (_MX6Q_PAD_EIM_A19__GPIO_2_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A19__TPSMP_HDATA_3                         (_MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A19__SRC_BT_CFG_19                         (_MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18                        (_MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13                     (_MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13                        (_MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A18__RESERVED_RESERVED                     (_MX6Q_PAD_EIM_A18__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21            (_MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A18__GPIO_2_20                             (_MX6Q_PAD_EIM_A18__GPIO_2_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A18__TPSMP_HDATA_4                         (_MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A18__SRC_BT_CFG_18                         (_MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17                        (_MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12                     (_MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12                        (_MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A17__RESERVED_RESERVED                     (_MX6Q_PAD_EIM_A17__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22            (_MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A17__GPIO_2_21                             (_MX6Q_PAD_EIM_A17__GPIO_2_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A17__TPSMP_HDATA_5                         (_MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A17__SRC_BT_CFG_17                         (_MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16                        (_MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK                     (_MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK                      (_MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23            (_MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A16__GPIO_2_22                             (_MX6Q_PAD_EIM_A16__GPIO_2_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A16__TPSMP_HDATA_6                         (_MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_A16__SRC_BT_CFG_16                         (_MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0                        (_MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5                         (_MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_CS0__ECSPI2_SCLK                           (_MX6Q_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24            (_MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_CS0__GPIO_2_23                             (_MX6Q_PAD_EIM_CS0__GPIO_2_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7                         (_MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1                        (_MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6                         (_MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_CS1__ECSPI2_MOSI                           (_MX6Q_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25            (_MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_CS1__GPIO_2_24                             (_MX6Q_PAD_EIM_CS1__GPIO_2_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8                         (_MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_OE__WEIM_WEIM_OE                           (_MX6Q_PAD_EIM_OE__WEIM_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7                          (_MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_OE__ECSPI2_MISO                            (_MX6Q_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26             (_MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_OE__GPIO_2_25                              (_MX6Q_PAD_EIM_OE__GPIO_2_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_OE__TPSMP_HDATA_9                          (_MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_RW__WEIM_WEIM_RW                           (_MX6Q_PAD_EIM_RW__WEIM_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8                          (_MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_RW__ECSPI2_SS0                             (_MX6Q_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27             (_MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_RW__GPIO_2_26                              (_MX6Q_PAD_EIM_RW__GPIO_2_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_RW__TPSMP_HDATA_10                         (_MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_RW__SRC_BT_CFG_29                          (_MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA                         (_MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17                        (_MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_LBA__ECSPI2_SS1                            (_MX6Q_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_LBA__GPIO_2_27                             (_MX6Q_PAD_EIM_LBA__GPIO_2_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11                        (_MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26                         (_MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0                        (_MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11                     (_MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11                        (_MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0             (_MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY                          (_MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB0__GPIO_2_28                             (_MX6Q_PAD_EIM_EB0__GPIO_2_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12                        (_MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27                         (_MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1                        (_MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10                     (_MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10                        (_MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1             (_MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB1__GPIO_2_29                             (_MX6Q_PAD_EIM_EB1__GPIO_2_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13                        (_MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28                         (_MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0                      (_MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9                      (_MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9                         (_MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2             (_MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA0__GPIO_3_0                              (_MX6Q_PAD_EIM_DA0__GPIO_3_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14                        (_MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0                          (_MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1                      (_MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8                      (_MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8                         (_MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3             (_MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE        (_MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA1__GPIO_3_1                              (_MX6Q_PAD_EIM_DA1__GPIO_3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15                        (_MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1                          (_MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2                      (_MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7                      (_MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7                         (_MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4             (_MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE        (_MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA2__GPIO_3_2                              (_MX6Q_PAD_EIM_DA2__GPIO_3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16                        (_MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2                          (_MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3                      (_MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6                      (_MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6                         (_MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5             (_MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ            (_MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA3__GPIO_3_3                              (_MX6Q_PAD_EIM_DA3__GPIO_3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17                        (_MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3                          (_MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4                      (_MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5                      (_MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5                         (_MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6             (_MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN             (_MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA4__GPIO_3_4                              (_MX6Q_PAD_EIM_DA4__GPIO_3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18                        (_MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4                          (_MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5                      (_MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4                      (_MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4                         (_MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7             (_MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP             (_MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA5__GPIO_3_5                              (_MX6Q_PAD_EIM_DA5__GPIO_3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19                        (_MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5                          (_MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6                      (_MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3                      (_MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3                         (_MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8             (_MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN             (_MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA6__GPIO_3_6                              (_MX6Q_PAD_EIM_DA6__GPIO_3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20                        (_MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6                          (_MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7                      (_MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2                      (_MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2                         (_MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9             (_MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA7__GPIO_3_7                              (_MX6Q_PAD_EIM_DA7__GPIO_3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21                        (_MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7                          (_MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8                      (_MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1                      (_MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1                         (_MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10            (_MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA8__GPIO_3_8                              (_MX6Q_PAD_EIM_DA8__GPIO_3_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22                        (_MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8                          (_MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9                      (_MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0                      (_MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0                         (_MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11            (_MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA9__GPIO_3_9                              (_MX6Q_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23                        (_MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9                          (_MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10                    (_MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15                       (_MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN                    (_MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12           (_MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA10__GPIO_3_10                            (_MX6Q_PAD_EIM_DA10__GPIO_3_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24                       (_MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10                        (_MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11                    (_MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2                        (_MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC                      (_MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13           (_MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6           (_MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA11__GPIO_3_11                            (_MX6Q_PAD_EIM_DA11__GPIO_3_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25                       (_MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11                        (_MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12                    (_MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3                        (_MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC                      (_MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14           (_MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3           (_MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA12__GPIO_3_12                            (_MX6Q_PAD_EIM_DA12__GPIO_3_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26                       (_MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12                        (_MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13                    (_MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS                       (_MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK                      (_MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15           (_MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4           (_MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA13__GPIO_3_13                            (_MX6Q_PAD_EIM_DA13__GPIO_3_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27                       (_MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13                        (_MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14                    (_MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS                       (_MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK                      (_MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16           (_MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5           (_MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA14__GPIO_3_14                            (_MX6Q_PAD_EIM_DA14__GPIO_3_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28                       (_MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14                        (_MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15                    (_MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1                        (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4                        (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17           (_MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA15__GPIO_3_15                            (_MX6Q_PAD_EIM_DA15__GPIO_3_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29                       (_MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15                        (_MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT                       (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B                    (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_WAIT__GPIO_5_0                             (_MX6Q_PAD_EIM_WAIT__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30                       (_MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25                        (_MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK                       (_MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16                       (_MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_BCLK__GPIO_6_31                            (_MX6Q_PAD_EIM_BCLK__GPIO_6_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31                       (_MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK                (_MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK                (_MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28       (_MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0          (_MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16                        (_MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0                (_MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15                      (_MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15                      (_MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC                     (_MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29          (_MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1             (_MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN15__GPIO_4_17                           (_MX6Q_PAD_DI0_PIN15__GPIO_4_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1                   (_MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2                        (_MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2                        (_MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD                      (_MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30           (_MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2              (_MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN2__GPIO_4_18                            (_MX6Q_PAD_DI0_PIN2__GPIO_4_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2                    (_MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9               (_MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3                        (_MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3                        (_MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS                     (_MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31           (_MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3              (_MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN3__GPIO_4_19                            (_MX6Q_PAD_DI0_PIN3__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3                    (_MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10              (_MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4                        (_MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4                        (_MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD                      (_MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN4__USDHC1_WP                            (_MX6Q_PAD_DI0_PIN4__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD                     (_MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN4__GPIO_4_20                            (_MX6Q_PAD_DI0_PIN4__GPIO_4_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4                    (_MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11              (_MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0                   (_MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0                   (_MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK                        (_MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0               (_MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN                (_MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT0__GPIO_4_21                          (_MX6Q_PAD_DISP0_DAT0__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5                  (_MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1                   (_MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1                   (_MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI                        (_MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1               (_MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL       (_MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT1__GPIO_4_22                          (_MX6Q_PAD_DISP0_DAT1__GPIO_4_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6                  (_MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12            (_MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2                   (_MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2                   (_MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO                        (_MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2               (_MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE                    (_MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT2__GPIO_4_23                          (_MX6Q_PAD_DISP0_DAT2__GPIO_4_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7                  (_MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13            (_MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3                   (_MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3                   (_MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0                         (_MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3               (_MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR               (_MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT3__GPIO_4_24                          (_MX6Q_PAD_DISP0_DAT3__GPIO_4_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8                  (_MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14            (_MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4                   (_MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4                   (_MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1                         (_MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4               (_MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB                 (_MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT4__GPIO_4_25                          (_MX6Q_PAD_DISP0_DAT4__GPIO_4_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9                  (_MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15            (_MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5                   (_MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5                   (_MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2                         (_MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS                   (_MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS           (_MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT5__GPIO_4_26                          (_MX6Q_PAD_DISP0_DAT5__GPIO_4_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10                 (_MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16            (_MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6                   (_MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6                   (_MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3                         (_MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC                    (_MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE          (_MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT6__GPIO_4_27                          (_MX6Q_PAD_DISP0_DAT6__GPIO_4_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11                 (_MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17            (_MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7                   (_MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7                   (_MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY                         (_MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5               (_MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0         (_MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT7__GPIO_4_28                          (_MX6Q_PAD_DISP0_DAT7__GPIO_4_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12                 (_MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18            (_MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8                   (_MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8                   (_MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT8__PWM1_PWMO                          (_MX6Q_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B                       (_MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1         (_MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT8__GPIO_4_29                          (_MX6Q_PAD_DISP0_DAT8__GPIO_4_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13                 (_MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19            (_MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9                   (_MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9                   (_MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT9__PWM2_PWMO                          (_MX6Q_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B                       (_MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2         (_MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT9__GPIO_4_30                          (_MX6Q_PAD_DISP0_DAT9__GPIO_4_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14                 (_MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20            (_MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10                 (_MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10                 (_MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6              (_MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3        (_MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT10__GPIO_4_31                         (_MX6Q_PAD_DISP0_DAT10__GPIO_4_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15                (_MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21           (_MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11                 (_MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11                 (_MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7              (_MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4        (_MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT11__GPIO_5_5                          (_MX6Q_PAD_DISP0_DAT11__GPIO_5_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16                (_MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22           (_MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12                 (_MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12                 (_MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED                 (_MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5        (_MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT12__GPIO_5_6                          (_MX6Q_PAD_DISP0_DAT12__GPIO_5_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17                (_MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23           (_MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13                 (_MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13                 (_MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS                  (_MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0        (_MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT13__GPIO_5_7                          (_MX6Q_PAD_DISP0_DAT13__GPIO_5_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18                (_MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24           (_MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14                 (_MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14                 (_MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC                   (_MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1        (_MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT14__GPIO_5_8                          (_MX6Q_PAD_DISP0_DAT14__GPIO_5_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19                (_MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15                 (_MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15                 (_MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1                        (_MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1                        (_MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2        (_MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT15__GPIO_5_9                          (_MX6Q_PAD_DISP0_DAT15__GPIO_5_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20                (_MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25           (_MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16                 (_MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16                 (_MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI                       (_MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC                   (_MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0             (_MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT16__GPIO_5_10                         (_MX6Q_PAD_DISP0_DAT16__GPIO_5_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21                (_MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26           (_MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17                 (_MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17                 (_MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO                       (_MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD                   (_MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1             (_MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT17__GPIO_5_11                         (_MX6Q_PAD_DISP0_DAT17__GPIO_5_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22                (_MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27           (_MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18                 (_MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18                 (_MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0                        (_MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS                  (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS                  (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT18__GPIO_5_12                         (_MX6Q_PAD_DISP0_DAT18__GPIO_5_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23                (_MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2                    (_MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19                 (_MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19                 (_MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK                       (_MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD                   (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC                   (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT19__GPIO_5_13                         (_MX6Q_PAD_DISP0_DAT19__GPIO_5_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24                (_MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3                    (_MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20                 (_MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20                 (_MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK                       (_MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC                   (_MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7        (_MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT20__GPIO_5_14                         (_MX6Q_PAD_DISP0_DAT20__GPIO_5_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25                (_MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28           (_MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21                 (_MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21                 (_MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI                       (_MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD                   (_MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0           (_MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT21__GPIO_5_15                         (_MX6Q_PAD_DISP0_DAT21__GPIO_5_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26                (_MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29           (_MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22                 (_MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22                 (_MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO                       (_MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS                  (_MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1           (_MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT22__GPIO_5_16                         (_MX6Q_PAD_DISP0_DAT22__GPIO_5_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27                (_MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30           (_MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23                 (_MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23                 (_MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0                        (_MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD                   (_MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2           (_MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT23__GPIO_5_17                         (_MX6Q_PAD_DISP0_DAT23__GPIO_5_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28                (_MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31           (_MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED                   (_MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_MDIO__ENET_MDIO                           (_MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define  MX6Q_PAD_ENET_MDIO__ESAI1_SCKR                          (_MX6Q_PAD_ENET_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3             (_MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT                (_MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_MDIO__GPIO_1_22                           (_MX6Q_PAD_ENET_MDIO__GPIO_1_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK                         (_MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED                (_MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK                      (_MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define  MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR                        (_MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4          (_MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_REF_CLK__GPIO_1_23                        (_MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK                      (_MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH   (_MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_ENET_RX_ER__ENET_RX_ER                         (_MX6Q_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR                         (_MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_RX_ER__SPDIF_IN1                          (_MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT               (_MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_RX_ER__GPIO_1_24                          (_MX6Q_PAD_ENET_RX_ER__GPIO_1_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_RX_ER__PHY_TDI                            (_MX6Q_PAD_ENET_RX_ER__PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD      (_MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED                 (_MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN                        (_MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT                        (_MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK                (_MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_CRS_DV__GPIO_1_25                         (_MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_CRS_DV__PHY_TDO                           (_MX6Q_PAD_ENET_CRS_DV__PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD     (_MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_ENET_RXD1__MLB_MLBSIG                          (_MX6Q_PAD_ENET_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_RXD1__ENET_RDATA_1                        (_MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_RXD1__ESAI1_FST                           (_MX6Q_PAD_ENET_RXD1__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT                (_MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_RXD1__GPIO_1_26                           (_MX6Q_PAD_ENET_RXD1__GPIO_1_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_RXD1__PHY_TCK                             (_MX6Q_PAD_ENET_RXD1__PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET   (_MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT                      (_MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_RXD0__ENET_RDATA_0                        (_MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_RXD0__ESAI1_HCKT                          (_MX6Q_PAD_ENET_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_RXD0__SPDIF_OUT1                          (_MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_RXD0__GPIO_1_27                           (_MX6Q_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_RXD0__PHY_TMS                             (_MX6Q_PAD_ENET_RXD0__PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV    (_MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED                  (_MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_TX_EN__ENET_TX_EN                         (_MX6Q_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2                      (_MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_TX_EN__GPIO_1_28                          (_MX6Q_PAD_ENET_TX_EN__GPIO_1_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI                       (_MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH     (_MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_ENET_TXD1__MLB_MLBCLK                          (_MX6Q_PAD_ENET_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_TXD1__ENET_TDATA_1                        (_MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3                       (_MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN                 (_MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_TXD1__GPIO_1_29                           (_MX6Q_PAD_ENET_TXD1__GPIO_1_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO                        (_MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD       (_MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED                   (_MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_TXD0__ENET_TDATA_0                        (_MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1                       (_MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_TXD0__GPIO_1_30                           (_MX6Q_PAD_ENET_TXD0__GPIO_1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK                        (_MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD       (_MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_ENET_MDC__MLB_MLBDAT                           (_MX6Q_PAD_ENET_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_MDC__ENET_MDC                             (_MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define  MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0                        (_MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN                  (_MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_MDC__GPIO_1_31                            (_MX6Q_PAD_ENET_MDC__GPIO_1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_MDC__SATA_PHY_TMS                         (_MX6Q_PAD_ENET_MDC__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET    (_MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40                       (_MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41                       (_MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42                       (_MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43                       (_MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44                       (_MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45                       (_MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46                       (_MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47                       (_MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5                   (_MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5                     (_MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32                       (_MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33                       (_MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34                       (_MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35                       (_MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36                       (_MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37                       (_MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38                       (_MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39                       (_MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4                     (_MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4                   (_MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24                       (_MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25                       (_MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26                       (_MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27                       (_MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28                       (_MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29                       (_MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3                   (_MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30                       (_MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31                       (_MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3                     (_MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16                       (_MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17                       (_MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18                       (_MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19                       (_MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20                       (_MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21                       (_MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22                       (_MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2                   (_MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23                       (_MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2                     (_MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0                         (_MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1                         (_MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2                         (_MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3                         (_MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4                         (_MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5                         (_MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6                         (_MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7                         (_MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8                         (_MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9                         (_MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10                       (_MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11                       (_MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12                       (_MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13                       (_MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14                       (_MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15                       (_MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS                        (_MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0                       (_MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1                       (_MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS                        (_MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET                    (_MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0                   (_MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1                   (_MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0                 (_MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2                   (_MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0                 (_MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1                 (_MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1                 (_MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0                   (_MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1                   (_MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE                      (_MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0                         (_MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1                         (_MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2                         (_MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3                         (_MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4                         (_MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5                         (_MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0                   (_MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6                         (_MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7                         (_MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0                     (_MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8                         (_MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9                         (_MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10                       (_MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11                       (_MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12                       (_MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13                       (_MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14                       (_MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1                   (_MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15                       (_MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1                     (_MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48                       (_MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49                       (_MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50                       (_MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51                       (_MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52                       (_MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53                       (_MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54                       (_MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55                       (_MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6                   (_MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6                     (_MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56                       (_MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7                   (_MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57                       (_MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58                       (_MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59                       (_MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60                       (_MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7                     (_MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61                       (_MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62                       (_MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63                       (_MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_KEY_COL0__ECSPI1_SCLK                          (_MX6Q_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL0__ENET_RDATA_3                         (_MX6Q_PAD_KEY_COL0__ENET_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC                      (_MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL0__KPP_COL_0                            (_MX6Q_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL0__UART4_TXD                            (_MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL0__UART4_RXD                            (_MX6Q_PAD_KEY_COL0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL0__GPIO_4_6                             (_MX6Q_PAD_KEY_COL0__GPIO_4_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT                       (_MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST                       (_MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI                          (_MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW0__ENET_TDATA_3                         (_MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD                      (_MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW0__KPP_ROW_0                            (_MX6Q_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW0__UART4_TXD                            (_MX6Q_PAD_KEY_ROW0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW0__UART4_RXD                            (_MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW0__GPIO_4_7                             (_MX6Q_PAD_KEY_ROW0__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT                       (_MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0               (_MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_KEY_COL1__ECSPI1_MISO                          (_MX6Q_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL1__ENET_MDIO                            (_MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS                     (_MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL1__KPP_COL_1                            (_MX6Q_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL1__UART5_TXD                            (_MX6Q_PAD_KEY_COL1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL1__UART5_RXD                            (_MX6Q_PAD_KEY_COL1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL1__GPIO_4_8                             (_MX6Q_PAD_KEY_COL1__GPIO_4_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL1__USDHC1_VSELECT                       (_MX6Q_PAD_KEY_COL1__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1               (_MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_KEY_ROW1__ECSPI1_SS0                           (_MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW1__ENET_COL                             (_MX6Q_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD                      (_MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW1__KPP_ROW_1                            (_MX6Q_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW1__UART5_TXD                            (_MX6Q_PAD_KEY_ROW1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW1__UART5_RXD                            (_MX6Q_PAD_KEY_ROW1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW1__GPIO_4_9                             (_MX6Q_PAD_KEY_ROW1__GPIO_4_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT                       (_MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2               (_MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_KEY_COL2__ECSPI1_SS1                           (_MX6Q_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL2__ENET_RDATA_2                         (_MX6Q_PAD_KEY_COL2__ENET_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL2__CAN1_TXCAN                           (_MX6Q_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL2__KPP_COL_2                            (_MX6Q_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL2__ENET_MDC                             (_MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL2__GPIO_4_10                            (_MX6Q_PAD_KEY_COL2__GPIO_4_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP           (_MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3      (_MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_KEY_ROW2__ECSPI1_SS2                           (_MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW2__ENET_TDATA_2                         (_MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW2__CAN1_RXCAN                           (_MX6Q_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW2__KPP_ROW_2                            (_MX6Q_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT                       (_MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW2__GPIO_4_11                            (_MX6Q_PAD_KEY_ROW2__GPIO_4_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE                     (_MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4               (_MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_KEY_COL3__ECSPI1_SS3                           (_MX6Q_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL3__ENET_CRS                             (_MX6Q_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL                      (_MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL3__KPP_COL_3                            (_MX6Q_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL3__I2C2_SCL                             (_MX6Q_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL3__GPIO_4_12                            (_MX6Q_PAD_KEY_COL3__GPIO_4_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL3__SPDIF_IN1                            (_MX6Q_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5               (_MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT                       (_MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK                    (_MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA                      (_MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW3__KPP_ROW_3                            (_MX6Q_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW3__I2C2_SDA                             (_MX6Q_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW3__GPIO_4_13                            (_MX6Q_PAD_KEY_ROW3__GPIO_4_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT                       (_MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6      (_MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_KEY_COL4__CAN2_TXCAN                           (_MX6Q_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL4__IPU1_SISG_4                          (_MX6Q_PAD_KEY_COL4__IPU1_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC                     (_MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL4__KPP_COL_4                            (_MX6Q_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL4__UART5_CTS                            (_MX6Q_PAD_KEY_COL4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL4__UART5_RTS                            (_MX6Q_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL4__GPIO_4_14                            (_MX6Q_PAD_KEY_COL4__GPIO_4_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49                   (_MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7      (_MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_KEY_ROW4__CAN2_RXCAN                           (_MX6Q_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW4__IPU1_SISG_5                          (_MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR                    (_MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW4__KPP_ROW_4                            (_MX6Q_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW4__UART5_CTS                            (_MX6Q_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW4__GPIO_4_15                            (_MX6Q_PAD_KEY_ROW4__GPIO_4_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50                   (_MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8      (_MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_GPIO_0__CCM_CLKO                               (_MX6Q_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_0__KPP_COL_5                              (_MX6Q_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK                      (_MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_0__EPIT1_EPITO                            (_MX6Q_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_0__GPIO_1_0                               (_MX6Q_PAD_GPIO_0__GPIO_1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR                       (_MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5             (_MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_GPIO_1__ESAI1_SCKR                             (_MX6Q_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_1__WDOG2_WDOG_B                           (_MX6Q_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_1__KPP_ROW_5                              (_MX6Q_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_1__PWM2_PWMO                              (_MX6Q_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_1__GPIO_1_1                               (_MX6Q_PAD_GPIO_1__GPIO_1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_1__USDHC1_CD                              (_MX6Q_PAD_GPIO_1__USDHC1_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_1__SRC_TESTER_ACK                         (_MX6Q_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_GPIO_9__ESAI1_FSR                              (_MX6Q_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_9__WDOG1_WDOG_B                           (_MX6Q_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_9__KPP_COL_6                              (_MX6Q_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_9__CCM_REF_EN_B                           (_MX6Q_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_9__PWM1_PWMO                              (_MX6Q_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(MX6Q_PWM_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_9__GPIO_1_9                               (_MX6Q_PAD_GPIO_9__GPIO_1_9 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
+#define  MX6Q_PAD_GPIO_9__USDHC1_WP                              (_MX6Q_PAD_GPIO_9__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_9__SRC_EARLY_RST                          (_MX6Q_PAD_GPIO_9__SRC_EARLY_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_GPIO_3__ESAI1_HCKR                             (_MX6Q_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0             (_MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_3__I2C3_SCL                               (_MX6Q_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT                  (_MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_3__CCM_CLKO2                              (_MX6Q_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_3__GPIO_1_3                               (_MX6Q_PAD_GPIO_3__GPIO_1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC                        (_MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_3__MLB_MLBCLK                             (_MX6Q_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_GPIO_6__ESAI1_SCKT                             (_MX6Q_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1             (_MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_6__I2C3_SDA                               (_MX6Q_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0                          (_MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB                        (_MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_6__GPIO_1_6                               (_MX6Q_PAD_GPIO_6__GPIO_1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_6__USDHC2_LCTL                            (_MX6Q_PAD_GPIO_6__USDHC2_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_6__MLB_MLBSIG                             (_MX6Q_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_GPIO_2__ESAI1_FST                              (_MX6Q_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2             (_MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_2__KPP_ROW_6                              (_MX6Q_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1                          (_MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0                    (_MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_2__GPIO_1_2                               (_MX6Q_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_2__USDHC2_WP                              (_MX6Q_PAD_GPIO_2__USDHC2_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_2__MLB_MLBDAT                             (_MX6Q_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_GPIO_4__ESAI1_HCKT                             (_MX6Q_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3             (_MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_4__KPP_COL_7                              (_MX6Q_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2                          (_MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1                    (_MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_4__GPIO_1_4                               (_MX6Q_PAD_GPIO_4__GPIO_1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_4__USDHC2_CD                              (_MX6Q_PAD_GPIO_4__USDHC2_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED        (_MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3                          (_MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4             (_MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_5__KPP_ROW_7                              (_MX6Q_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_5__CCM_CLKO                               (_MX6Q_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2                    (_MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_5__GPIO_1_5                               (_MX6Q_PAD_GPIO_5__GPIO_1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_5__I2C3_SCL                               (_MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_5__CHEETAH_EVENTI                         (_MX6Q_PAD_GPIO_5__CHEETAH_EVENTI | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1                          (_MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_7__ECSPI5_RDY                             (_MX6Q_PAD_GPIO_7__ECSPI5_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_7__EPIT1_EPITO                            (_MX6Q_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_7__CAN1_TXCAN                             (_MX6Q_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_7__UART2_TXD                              (_MX6Q_PAD_GPIO_7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_7__UART2_RXD                              (_MX6Q_PAD_GPIO_7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_7__GPIO_1_7                               (_MX6Q_PAD_GPIO_7__GPIO_1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_7__SPDIF_PLOCK                            (_MX6Q_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE                (_MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0                          (_MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT                  (_MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_8__EPIT2_EPITO                            (_MX6Q_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_8__CAN1_RXCAN                             (_MX6Q_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_8__UART2_TXD                              (_MX6Q_PAD_GPIO_8__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_8__UART2_RXD                              (_MX6Q_PAD_GPIO_8__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_8__GPIO_1_8                               (_MX6Q_PAD_GPIO_8__GPIO_1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_8__SPDIF_SRCLK                            (_MX6Q_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP            (_MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2                         (_MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN                   (_MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT          (_MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_16__USDHC1_LCTL                           (_MX6Q_PAD_GPIO_16__USDHC1_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_16__SPDIF_IN1                             (_MX6Q_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_16__GPIO_7_11                             (_MX6Q_PAD_GPIO_16__GPIO_7_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_16__I2C3_SDA                              (_MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_16__SJC_DE_B                              (_MX6Q_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_GPIO_17__ESAI1_TX0                             (_MX6Q_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN                   (_MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_17__CCM_PMIC_RDY                          (_MX6Q_PAD_GPIO_17__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0                 (_MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_17__SPDIF_OUT1                            (_MX6Q_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_17__GPIO_7_12                             (_MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_17__SJC_JTAG_ACT                          (_MX6Q_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_GPIO_18__ESAI1_TX1                             (_MX6Q_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_18__ENET_RX_CLK                           (_MX6Q_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_18__USDHC3_VSELECT                        (_MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1                 (_MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK                     (_MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_18__GPIO_7_13                             (_MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL        (_MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST                        (_MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_GPIO_19__KPP_COL_5                             (_MX6Q_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT                  (_MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_19__SPDIF_OUT1                            (_MX6Q_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_19__CCM_CLKO                              (_MX6Q_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_19__ECSPI1_RDY                            (_MX6Q_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_19__GPIO_4_5                              (_MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_19__ENET_TX_ER                            (_MX6Q_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_GPIO_19__SRC_INT_BOOT                          (_MX6Q_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK                  (_MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12  (_MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0                   (_MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18                         (_MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29                (_MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO                    (_MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC                     (_MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13    (_MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_MCLK__CCM_CLKO                            (_MX6Q_PAD_CSI0_MCLK__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1                     (_MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_MCLK__GPIO_5_19                           (_MX6Q_PAD_CSI0_MCLK__GPIO_5_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30                  (_MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL                       (_MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN                (_MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0                    (_MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 (_MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2                  (_MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20                        (_MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31               (_MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK                    (_MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC                    (_MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1                      (_MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15   (_MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3                    (_MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_VSYNC__GPIO_5_21                          (_MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32                 (_MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0                    (_MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4                       (_MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2                       (_MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK                         (_MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT4__KPP_COL_5                           (_MX6Q_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC                     (_MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT4__GPIO_5_22                           (_MX6Q_PAD_CSI0_DAT4__GPIO_5_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43                  (_MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1                     (_MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5                       (_MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3                       (_MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI                         (_MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT5__KPP_ROW_5                           (_MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD                     (_MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT5__GPIO_5_23                           (_MX6Q_PAD_CSI0_DAT5__GPIO_5_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44                  (_MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2                     (_MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6                       (_MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4                       (_MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO                         (_MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT6__KPP_COL_6                           (_MX6Q_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS                    (_MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT6__GPIO_5_24                           (_MX6Q_PAD_CSI0_DAT6__GPIO_5_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45                  (_MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3                     (_MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7                       (_MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5                       (_MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0                          (_MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT7__KPP_ROW_6                           (_MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD                     (_MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT7__GPIO_5_25                           (_MX6Q_PAD_CSI0_DAT7__GPIO_5_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46                  (_MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4                     (_MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8                       (_MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6                       (_MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK                         (_MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT8__KPP_COL_7                           (_MX6Q_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT8__I2C1_SDA                            (_MX6Q_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT8__GPIO_5_26                           (_MX6Q_PAD_CSI0_DAT8__GPIO_5_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47                  (_MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5                     (_MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9                       (_MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7                       (_MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI                         (_MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT9__KPP_ROW_7                           (_MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT9__I2C1_SCL                            (_MX6Q_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT9__GPIO_5_27                           (_MX6Q_PAD_CSI0_DAT9__GPIO_5_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48                  (_MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6                     (_MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10                     (_MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC                    (_MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO                        (_MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT10__UART1_TXD                          (_MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT10__UART1_RXD                          (_MX6Q_PAD_CSI0_DAT10__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4                    (_MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT10__GPIO_5_28                          (_MX6Q_PAD_CSI0_DAT10__GPIO_5_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33                 (_MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7                    (_MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11                     (_MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS                   (_MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0                         (_MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT11__UART1_TXD                          (_MX6Q_PAD_CSI0_DAT11__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT11__UART1_RXD                          (_MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5                    (_MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT11__GPIO_5_29                          (_MX6Q_PAD_CSI0_DAT11__GPIO_5_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34                 (_MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8                    (_MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12                     (_MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8                      (_MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16   (_MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT12__UART4_TXD                          (_MX6Q_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT12__UART4_RXD                          (_MX6Q_PAD_CSI0_DAT12__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6                    (_MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT12__GPIO_5_30                          (_MX6Q_PAD_CSI0_DAT12__GPIO_5_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35                 (_MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9                    (_MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13                     (_MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9                      (_MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17   (_MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT13__UART4_TXD                          (_MX6Q_PAD_CSI0_DAT13__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT13__UART4_RXD                          (_MX6Q_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7                    (_MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT13__GPIO_5_31                          (_MX6Q_PAD_CSI0_DAT13__GPIO_5_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36                 (_MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10                   (_MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14                     (_MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10                     (_MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18   (_MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT14__UART5_TXD                          (_MX6Q_PAD_CSI0_DAT14__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT14__UART5_RXD                          (_MX6Q_PAD_CSI0_DAT14__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8                    (_MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT14__GPIO_6_0                           (_MX6Q_PAD_CSI0_DAT14__GPIO_6_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37                 (_MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11                   (_MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15                     (_MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11                     (_MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19   (_MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT15__UART5_TXD                          (_MX6Q_PAD_CSI0_DAT15__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT15__UART5_RXD                          (_MX6Q_PAD_CSI0_DAT15__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9                    (_MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT15__GPIO_6_1                           (_MX6Q_PAD_CSI0_DAT15__GPIO_6_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38                 (_MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12                   (_MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16                     (_MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12                     (_MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20   (_MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT16__UART4_CTS                          (_MX6Q_PAD_CSI0_DAT16__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT16__UART4_RTS                          (_MX6Q_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10                   (_MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT16__GPIO_6_2                           (_MX6Q_PAD_CSI0_DAT16__GPIO_6_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39                 (_MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13                   (_MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17                     (_MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13                     (_MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21   (_MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT17__UART4_CTS                          (_MX6Q_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11                   (_MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT17__GPIO_6_3                           (_MX6Q_PAD_CSI0_DAT17__GPIO_6_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40                 (_MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14                   (_MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18                     (_MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14                     (_MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22   (_MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT18__UART5_CTS                          (_MX6Q_PAD_CSI0_DAT18__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT18__UART5_RTS                          (_MX6Q_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12                   (_MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT18__GPIO_6_4                           (_MX6Q_PAD_CSI0_DAT18__GPIO_6_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41                 (_MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15                   (_MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19                     (_MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15                     (_MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23   (_MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT19__UART5_CTS                          (_MX6Q_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13                   (_MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT19__GPIO_6_5                           (_MX6Q_PAD_CSI0_DAT19__GPIO_6_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42                 (_MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9              (_MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_JTAG_TMS__SJC_TMS                              (_MX6Q_PAD_JTAG_TMS__SJC_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_JTAG_MOD__SJC_MOD                              (_MX6Q_PAD_JTAG_MOD__SJC_MOD | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB                          (_MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_JTAG_TDI__SJC_TDI                              (_MX6Q_PAD_JTAG_TDI__SJC_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_JTAG_TCK__SJC_TCK                              (_MX6Q_PAD_JTAG_TCK__SJC_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_JTAG_TDO__SJC_TDO                              (_MX6Q_PAD_JTAG_TDO__SJC_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3                     (_MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2                     (_MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK                     (_MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1                     (_MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0                     (_MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3                     (_MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK                     (_MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2                     (_MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1                     (_MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0                     (_MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1               (_MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM (_MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ              (_MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_POR_B__SRC_POR_B                               (_MX6Q_PAD_POR_B__SRC_POR_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1                    (_MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_RESET_IN_B__SRC_RESET_B                        (_MX6Q_PAD_RESET_IN_B__SRC_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0                    (_MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_TEST_MODE__TCU_TEST_MODE                       (_MX6Q_PAD_TEST_MODE__TCU_TEST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD3_DAT7__USDHC3_DAT7                          (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT7__UART1_TXD                            (_MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT7__UART1_RXD                            (_MX6Q_PAD_SD3_DAT7__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24     (_MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0                 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0                 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT7__GPIO_6_17                            (_MX6Q_PAD_SD3_DAT7__GPIO_6_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12            (_MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV     (_MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD3_DAT6__USDHC3_DAT6                          (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT6__UART1_TXD                            (_MX6Q_PAD_SD3_DAT6__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT6__UART1_RXD                            (_MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25     (_MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1                 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1                 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT6__GPIO_6_18                            (_MX6Q_PAD_SD3_DAT6__GPIO_6_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13            (_MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10               (_MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD3_DAT5__USDHC3_DAT5                          (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT5__UART2_TXD                            (_MX6Q_PAD_SD3_DAT5__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT5__UART2_RXD                            (_MX6Q_PAD_SD3_DAT5__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26     (_MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2                 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2                 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT5__GPIO_7_0                             (_MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14            (_MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11               (_MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD3_DAT4__USDHC3_DAT4                          (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT4__UART2_TXD                            (_MX6Q_PAD_SD3_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT4__UART2_RXD                            (_MX6Q_PAD_SD3_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27     (_MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3                 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3                 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT4__GPIO_7_1                             (_MX6Q_PAD_SD3_DAT4__GPIO_7_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15            (_MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12               (_MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD3_CMD__USDHC3_CMD                            (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_CMD__UART2_CTS                             (_MX6Q_PAD_SD3_CMD__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD3_CMD__CAN1_TXCAN                            (_MX6Q_PAD_SD3_CMD__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4                  (_MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4                  (_MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_CMD__GPIO_7_2                              (_MX6Q_PAD_SD3_CMD__GPIO_7_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16             (_MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13                (_MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD3_CLK__USDHC3_CLK                            (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_CLK__UART2_CTS                             (_MX6Q_PAD_SD3_CLK__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD3_CLK__UART2_RTS                             (_MX6Q_PAD_SD3_CLK__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD3_CLK__CAN1_RXCAN                            (_MX6Q_PAD_SD3_CLK__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5                  (_MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5                  (_MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_CLK__GPIO_7_3                              (_MX6Q_PAD_SD3_CLK__GPIO_7_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17             (_MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14                (_MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD3_DAT0__USDHC3_DAT0                          (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT0__UART1_CTS                            (_MX6Q_PAD_SD3_DAT0__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT0__CAN2_TXCAN                           (_MX6Q_PAD_SD3_DAT0__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6                 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6                 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT0__GPIO_7_4                             (_MX6Q_PAD_SD3_DAT0__GPIO_7_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18            (_MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15               (_MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD3_DAT1__USDHC3_DAT1                          (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT1__UART1_CTS                            (_MX6Q_PAD_SD3_DAT1__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT1__UART1_RTS                            (_MX6Q_PAD_SD3_DAT1__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT1__CAN2_RXCAN                           (_MX6Q_PAD_SD3_DAT1__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7                 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7                 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT1__GPIO_7_5                             (_MX6Q_PAD_SD3_DAT1__GPIO_7_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19            (_MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0                (_MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD3_DAT2__USDHC3_DAT2                          (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28     (_MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8                 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8                 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT2__GPIO_7_6                             (_MX6Q_PAD_SD3_DAT2__GPIO_7_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20            (_MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1                (_MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD3_DAT3__USDHC3_DAT3                          (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT3__UART3_CTS                            (_MX6Q_PAD_SD3_DAT3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29     (_MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9                 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9                 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT3__GPIO_7_7                             (_MX6Q_PAD_SD3_DAT3__GPIO_7_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21            (_MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2                (_MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD3_RST__USDHC3_RST                            (_MX6Q_PAD_SD3_RST__USDHC3_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_RST__UART3_CTS                             (_MX6Q_PAD_SD3_RST__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD3_RST__UART3_RTS                             (_MX6Q_PAD_SD3_RST__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30      (_MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10                 (_MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10                 (_MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_RST__GPIO_7_8                              (_MX6Q_PAD_SD3_RST__GPIO_7_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22             (_MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3                 (_MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_NANDF_CLE__RAWNAND_CLE                         (_MX6Q_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CLE__IPU2_SISG_4                         (_MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31    (_MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11               (_MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11               (_MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CLE__GPIO_6_7                            (_MX6Q_PAD_NANDF_CLE__GPIO_6_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23           (_MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0                      (_MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_NANDF_ALE__RAWNAND_ALE                         (_MX6Q_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_ALE__USDHC4_RST                          (_MX6Q_PAD_NANDF_ALE__USDHC4_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0     (_MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12               (_MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12               (_MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_ALE__GPIO_6_8                            (_MX6Q_PAD_NANDF_ALE__GPIO_6_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24           (_MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1                      (_MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN                     (_MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5                        (_MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1    (_MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13              (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13              (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_WP_B__GPIO_6_9                           (_MX6Q_PAD_NANDF_WP_B__GPIO_6_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32         (_MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0    (_MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_NANDF_RB0__RAWNAND_READY0                      (_MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1                       (_MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2     (_MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14               (_MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14               (_MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_RB0__GPIO_6_10                           (_MX6Q_PAD_NANDF_RB0__GPIO_6_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33          (_MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1     (_MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N                        (_MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15               (_MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15               (_MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS0__GPIO_6_11                           (_MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2     (_MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N                        (_MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT                      (_MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT                      (_MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3     (_MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS1__GPIO_6_14                           (_MX6Q_PAD_NANDF_CS1__GPIO_6_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT   (_MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N                        (_MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS2__IPU1_SISG_0                         (_MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS2__ESAI1_TX0                           (_MX6Q_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE                       (_MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS2__CCM_CLKO2                           (_MX6Q_PAD_NANDF_CS2__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS2__GPIO_6_15                           (_MX6Q_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS2__IPU2_SISG_0                         (_MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N                        (_MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS3__IPU1_SISG_1                         (_MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS3__ESAI1_TX1                           (_MX6Q_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26                      (_MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4     (_MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS3__GPIO_6_16                           (_MX6Q_PAD_NANDF_CS3__GPIO_6_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS3__IPU2_SISG_1                         (_MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_CS3__TPSMP_CLK                           (_MX6Q_PAD_NANDF_CS3__TPSMP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD4_CMD__USDHC4_CMD                            (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_CMD__RAWNAND_RDN                           (_MX6Q_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_CMD__UART3_TXD                             (_MX6Q_PAD_SD4_CMD__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD4_CMD__UART3_RXD                             (_MX6Q_PAD_SD4_CMD__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5       (_MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_CMD__GPIO_7_9                              (_MX6Q_PAD_SD4_CMD__GPIO_7_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR                       (_MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD4_CLK__USDHC4_CLK                            (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_CLK__RAWNAND_WRN                           (_MX6Q_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_CLK__UART3_TXD                             (_MX6Q_PAD_SD4_CLK__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD4_CLK__UART3_RXD                             (_MX6Q_PAD_SD4_CLK__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6       (_MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_CLK__GPIO_7_10                             (_MX6Q_PAD_SD4_CLK__GPIO_7_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_NANDF_D0__RAWNAND_D0                           (_MX6Q_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D0__USDHC1_DAT4                          (_MX6Q_PAD_NANDF_D0__USDHC1_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0                (_MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16                (_MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16                (_MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D0__GPIO_2_0                             (_MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0                  (_MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0                  (_MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_NANDF_D1__RAWNAND_D1                           (_MX6Q_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D1__USDHC1_DAT5                          (_MX6Q_PAD_NANDF_D1__USDHC1_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1                (_MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17                (_MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17                (_MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D1__GPIO_2_1                             (_MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1                  (_MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1                  (_MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_NANDF_D2__RAWNAND_D2                           (_MX6Q_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D2__USDHC1_DAT6                          (_MX6Q_PAD_NANDF_D2__USDHC1_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2                (_MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18                (_MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18                (_MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D2__GPIO_2_2                             (_MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2                  (_MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2                  (_MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_NANDF_D3__RAWNAND_D3                           (_MX6Q_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D3__USDHC1_DAT7                          (_MX6Q_PAD_NANDF_D3__USDHC1_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3                (_MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19                (_MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19                (_MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D3__GPIO_2_3                             (_MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3                  (_MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3                  (_MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_NANDF_D4__RAWNAND_D4                           (_MX6Q_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D4__USDHC2_DAT4                          (_MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4                (_MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20                (_MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20                (_MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D4__GPIO_2_4                             (_MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4                  (_MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4                  (_MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_NANDF_D5__RAWNAND_D5                           (_MX6Q_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D5__USDHC2_DAT5                          (_MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5                (_MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21                (_MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21                (_MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D5__GPIO_2_5                             (_MX6Q_PAD_NANDF_D5__GPIO_2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5                  (_MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5                  (_MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_NANDF_D6__RAWNAND_D6                           (_MX6Q_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D6__USDHC2_DAT6                          (_MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6                (_MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22                (_MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22                (_MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D6__GPIO_2_6                             (_MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6                  (_MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6                  (_MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_NANDF_D7__RAWNAND_D7                           (_MX6Q_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D7__USDHC2_DAT7                          (_MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7                (_MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23                (_MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23                (_MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D7__GPIO_2_7                             (_MX6Q_PAD_NANDF_D7__GPIO_2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7                  (_MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7                  (_MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD4_DAT0__RAWNAND_D8                           (_MX6Q_PAD_SD4_DAT0__RAWNAND_D8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT0__USDHC4_DAT0                          (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT0__RAWNAND_DQS                          (_MX6Q_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24                (_MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24                (_MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT0__GPIO_2_8                             (_MX6Q_PAD_SD4_DAT0__GPIO_2_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8                  (_MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8                  (_MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD4_DAT1__RAWNAND_D9                           (_MX6Q_PAD_SD4_DAT1__RAWNAND_D9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT1__USDHC4_DAT1                          (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT1__PWM3_PWMO                            (_MX6Q_PAD_SD4_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25                (_MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25                (_MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT1__GPIO_2_9                             (_MX6Q_PAD_SD4_DAT1__GPIO_2_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9                  (_MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9                  (_MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD4_DAT2__RAWNAND_D10                          (_MX6Q_PAD_SD4_DAT2__RAWNAND_D10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT2__USDHC4_DAT2                          (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT2__PWM4_PWMO                            (_MX6Q_PAD_SD4_DAT2__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26                (_MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26                (_MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT2__GPIO_2_10                            (_MX6Q_PAD_SD4_DAT2__GPIO_2_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10                 (_MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10                 (_MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD4_DAT3__RAWNAND_D11                          (_MX6Q_PAD_SD4_DAT3__RAWNAND_D11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT3__USDHC4_DAT3                          (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27                (_MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27                (_MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT3__GPIO_2_11                            (_MX6Q_PAD_SD4_DAT3__GPIO_2_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11                 (_MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11                 (_MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD4_DAT4__RAWNAND_D12                          (_MX6Q_PAD_SD4_DAT4__RAWNAND_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT4__USDHC4_DAT4                          (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT4__UART2_TXD                            (_MX6Q_PAD_SD4_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT4__UART2_RXD                            (_MX6Q_PAD_SD4_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28                (_MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28                (_MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT4__GPIO_2_12                            (_MX6Q_PAD_SD4_DAT4__GPIO_2_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12                 (_MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12                 (_MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD4_DAT5__RAWNAND_D13                          (_MX6Q_PAD_SD4_DAT5__RAWNAND_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT5__USDHC4_DAT5                          (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT5__UART2_CTS                            (_MX6Q_PAD_SD4_DAT5__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT5__UART2_RTS                            (_MX6Q_PAD_SD4_DAT5__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29                (_MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29                (_MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT5__GPIO_2_13                            (_MX6Q_PAD_SD4_DAT5__GPIO_2_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13                 (_MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13                 (_MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD4_DAT6__RAWNAND_D14                          (_MX6Q_PAD_SD4_DAT6__RAWNAND_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT6__USDHC4_DAT6                          (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT6__UART2_CTS                            (_MX6Q_PAD_SD4_DAT6__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30                (_MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30                (_MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT6__GPIO_2_14                            (_MX6Q_PAD_SD4_DAT6__GPIO_2_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14                 (_MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14                 (_MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD4_DAT7__RAWNAND_D15                          (_MX6Q_PAD_SD4_DAT7__RAWNAND_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT7__USDHC4_DAT7                          (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT7__UART2_TXD                            (_MX6Q_PAD_SD4_DAT7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT7__UART2_RXD                            (_MX6Q_PAD_SD4_DAT7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31                (_MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31                (_MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT7__GPIO_2_15                            (_MX6Q_PAD_SD4_DAT7__GPIO_2_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15                 (_MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15                 (_MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD1_DAT1__USDHC1_DAT1                          (_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT1__ECSPI5_SS0                           (_MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT1__PWM3_PWMO                            (_MX6Q_PAD_SD1_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT1__GPT_CAPIN2                           (_MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7      (_MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT1__GPIO_1_17                            (_MX6Q_PAD_SD1_DAT1__GPIO_1_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0                    (_MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8                (_MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD1_DAT0__USDHC1_DAT0                          (_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT0__ECSPI5_MISO                          (_MX6Q_PAD_SD1_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS             (_MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT0__GPT_CAPIN1                           (_MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8      (_MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT0__GPIO_1_16                            (_MX6Q_PAD_SD1_DAT0__GPIO_1_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1                    (_MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7                (_MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD1_DAT3__USDHC1_DAT3                          (_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT3__ECSPI5_SS2                           (_MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3                          (_MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT3__PWM1_PWMO                            (_MX6Q_PAD_SD1_DAT3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B                         (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT3__GPIO_1_21                            (_MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB                 (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6                (_MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD1_CMD__USDHC1_CMD                            (_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD1_CMD__ECSPI5_MOSI                           (_MX6Q_PAD_SD1_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_CMD__PWM4_PWMO                             (_MX6Q_PAD_SD1_CMD__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_CMD__GPT_CMPOUT1                           (_MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_CMD__GPIO_1_18                             (_MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5                 (_MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD1_DAT2__USDHC1_DAT2                          (_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT2__ECSPI5_SS1                           (_MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2                          (_MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT2__PWM2_PWMO                            (_MX6Q_PAD_SD1_DAT2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B                         (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT2__GPIO_1_19                            (_MX6Q_PAD_SD1_DAT2__GPIO_1_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB                 (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4                (_MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD1_CLK__USDHC1_CLK                            (_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD1_CLK__ECSPI5_SCLK                           (_MX6Q_PAD_SD1_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT                        (_MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_CLK__GPT_CLKIN                             (_MX6Q_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_CLK__GPIO_1_20                             (_MX6Q_PAD_SD1_CLK__GPIO_1_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_CLK__PHY_DTB_0                             (_MX6Q_PAD_SD1_CLK__PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0                        (_MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD2_CLK__USDHC2_CLK                            (_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD2_CLK__ECSPI5_SCLK                           (_MX6Q_PAD_SD2_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_CLK__KPP_COL_5                             (_MX6Q_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS                      (_MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9       (_MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_CLK__GPIO_1_10                             (_MX6Q_PAD_SD2_CLK__GPIO_1_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_CLK__PHY_DTB_1                             (_MX6Q_PAD_SD2_CLK__PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1                        (_MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD2_CMD__USDHC2_CMD                            (_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD2_CMD__ECSPI5_MOSI                           (_MX6Q_PAD_SD2_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_CMD__KPP_ROW_5                             (_MX6Q_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC                       (_MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10      (_MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_CMD__GPIO_1_11                             (_MX6Q_PAD_SD2_CMD__GPIO_1_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define  MX6Q_PAD_SD2_DAT3__USDHC2_DAT3                          (_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT3__ECSPI5_SS3                           (_MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT3__KPP_COL_6                            (_MX6Q_PAD_SD2_DAT3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC                      (_MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11     (_MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT3__GPIO_1_12                            (_MX6Q_PAD_SD2_DAT3__GPIO_1_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT3__SJC_DONE                             (_MX6Q_PAD_SD2_DAT3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3                (_MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#endif
diff --git a/arch/arm/mach-imx/include/mach/iomux-v3.h b/arch/arm/mach-imx/include/mach/iomux-v3.h
index 8a1adc2ed0..2c92342085 100644
--- a/arch/arm/mach-imx/include/mach/iomux-v3.h
+++ b/arch/arm/mach-imx/include/mach/iomux-v3.h
@@ -42,41 +42,59 @@
  * If <padname> or <padmode> refers to a GPIO, it is named
  * GPIO_<unit>_<num>
  *
- */
+ * IOMUX/PAD Bit field definitions
+ *
+ * MUX_CTRL_OFS:	    0..11 (12)
+ * PAD_CTRL_OFS:	   12..23 (12)
+ * SEL_INPUT_OFS:	   24..35 (12)
+ * MUX_MODE + SION:	   36..40  (5)
+ * PAD_CTRL + NO_PAD_CTRL: 41..58 (18)
+ * SEL_INP:		   59..62  (4)
+ * reserved:		     63    (1)
+*/
+
+typedef u64 iomux_v3_cfg_t;
+
+#define MUX_CTRL_OFS_SHIFT	0
+#define MUX_CTRL_OFS_MASK	((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
+#define MUX_PAD_CTRL_OFS_SHIFT	12
+#define MUX_PAD_CTRL_OFS_MASK	((iomux_v3_cfg_t)0xfff << MUX_PAD_CTRL_OFS_SHIFT)
+#define MUX_SEL_INPUT_OFS_SHIFT	24
+#define MUX_SEL_INPUT_OFS_MASK	((iomux_v3_cfg_t)0xfff << MUX_SEL_INPUT_OFS_SHIFT)
 
-struct pad_desc {
-	unsigned mux_ctrl_ofs:12; /* IOMUXC_SW_MUX_CTL_PAD offset */
-	unsigned mux_mode:8;
-	unsigned pad_ctrl_ofs:12; /* IOMUXC_SW_PAD_CTRL offset */
-#define	NO_PAD_CTRL	(1 << 16)
-	unsigned pad_ctrl:17;
-	unsigned select_input_ofs:12; /* IOMUXC_SELECT_INPUT offset */
-	unsigned select_input:3;
-};
-
-#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _select_input_ofs, \
-		_select_input, _pad_ctrl)				\
-		{							\
-			.mux_ctrl_ofs     = _mux_ctrl_ofs,		\
-			.mux_mode         = _mux_mode,			\
-			.pad_ctrl_ofs     = _pad_ctrl_ofs,		\
-			.pad_ctrl         = _pad_ctrl,			\
-			.select_input_ofs = _select_input_ofs,		\
-			.select_input     = _select_input,		\
-		}
+#define MUX_MODE_SHIFT		36
+#define MUX_MODE_MASK		((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
+#define MUX_PAD_CTRL_SHIFT	41
+#define MUX_PAD_CTRL_MASK	((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
+#define MUX_SEL_INPUT_SHIFT	59
+#define MUX_SEL_INPUT_MASK	((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
 
+#define MUX_PAD_CTRL(x)		((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
+
+#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \
+		_sel_input, _pad_ctrl)					\
+	(((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) |	\
+		((iomux_v3_cfg_t)(_mux_mode) << MUX_MODE_SHIFT) |	\
+		((iomux_v3_cfg_t)(_pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
+		((iomux_v3_cfg_t)(_pad_ctrl) << MUX_PAD_CTRL_SHIFT) |	\
+		((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \
+		((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT))
+
+#define NEW_PAD_CTRL(cfg, pad)	(((cfg) & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(pad))
 /*
  * Use to set PAD control
  */
+
+#define NO_PAD_CTRL			(1 << 17)
 #define PAD_CTL_DVS			(1 << 13)
 #define PAD_CTL_HYS			(1 << 8)
 
 #define PAD_CTL_PKE			(1 << 7)
-#define PAD_CTL_PUE			(1 << 6)
-#define PAD_CTL_PUS_100K_DOWN		(0 << 4)
-#define PAD_CTL_PUS_47K_UP		(1 << 4)
-#define PAD_CTL_PUS_100K_UP		(2 << 4)
-#define PAD_CTL_PUS_22K_UP		(3 << 4)
+#define PAD_CTL_PUE			(1 << 6 | PAD_CTL_PKE)
+#define PAD_CTL_PUS_100K_DOWN		(0 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP		(1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP		(2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP		(3 << 4 | PAD_CTL_PUE)
 
 #define PAD_CTL_ODE			(1 << 3)
 
@@ -91,16 +109,14 @@ struct pad_desc {
 #define IOMUX_CONFIG_SION		(0x1 << 4)
 
 /*
- * setups a single pad:
- * 	- reserves the pad so that it is not claimed by another driver
- * 	- setups the iomux according to the configuration
+ * setups a single pad in the iomuxer
  */
-int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
+int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
 
 /*
  * setups mutliple pads
  * convenient way to call the above function with tables
  */
-int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count);
+int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
 
 #endif /* __MACH_IOMUX_V3_H__*/
diff --git a/arch/arm/mach-imx/include/mach/pmic.h b/arch/arm/mach-imx/include/mach/pmic.h
deleted file mode 100644
index e9a951bd38..0000000000
--- a/arch/arm/mach-imx/include/mach/pmic.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef __ASM_ARCH_PMIC_H
-#define __ASM_ARCH_PMIC_H
-
-/* The only function the PMIC driver currently exports. It's purpose
- * is to adjust the switchers to 1.45V in order to speed up the CPU
- * to 400MHz. This is probably board dependent, so we have to think
- * about a proper API for the PMIC
- */
-int pmic_power(void);
-
-#endif /* __ASM_ARCH_PMIC_H */
diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c
index bb2307a370..680d26088f 100644
--- a/arch/arm/mach-imx/iomux-v3.c
+++ b/arch/arm/mach-imx/iomux-v3.c
@@ -23,36 +23,46 @@
 #include <mach/iomux-v3.h>
 #include <mach/imx-regs.h>
 
+static void __iomem *base = (void *)IMX_IOMUXC_BASE;
+
 /*
- * setups a single pin:
- * 	- reserves the pin so that it is not claimed by another driver
- * 	- setups the iomux according to the configuration
+ * configures a single pad in the iomuxer
  */
-int mxc_iomux_v3_setup_pad(struct pad_desc *pad)
+int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
 {
-	if (pad->mux_ctrl_ofs)
-		writel(pad->mux_mode, IMX_IOMUXC_BASE + pad->mux_ctrl_ofs);
+	u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
+	u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
+	u32 sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
+	u32 sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
+	u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
+	u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
+
+	if (mux_ctrl_ofs)
+		__raw_writel(mux_mode, base + mux_ctrl_ofs);
+
+	if (sel_input_ofs)
+		__raw_writel(sel_input, base + sel_input_ofs);
 
-	if (pad->select_input_ofs)
-		writel(pad->select_input,
-				IMX_IOMUXC_BASE + pad->select_input_ofs);
+	if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
+		__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
 
-	if (!(pad->pad_ctrl & NO_PAD_CTRL))
-		writel(pad->pad_ctrl, IMX_IOMUXC_BASE + pad->pad_ctrl_ofs);
 	return 0;
 }
 EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
 
-int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count)
+
+int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
 {
-	struct pad_desc *p = pad_list;
+	iomux_v3_cfg_t *p = pad_list;
 	int i;
+	int ret;
 
 	for (i = 0; i < count; i++) {
-		mxc_iomux_v3_setup_pad(p);
+		ret = mxc_iomux_v3_setup_pad(*p);
+		if (ret)
+			return ret;
 		p++;
 	}
 	return 0;
 }
 EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
-
diff --git a/arch/arm/mach-imx/speed-imx6.c b/arch/arm/mach-imx/speed-imx6.c
new file mode 100644
index 0000000000..4cc9fdbbc4
--- /dev/null
+++ b/arch/arm/mach-imx/speed-imx6.c
@@ -0,0 +1,393 @@
+#include <common.h>
+#include <asm/io.h>
+#include <asm-generic/div64.h>
+#include <mach/imx-regs.h>
+#include <mach/clock-imx6.h>
+#include <mach/imx6-anadig.h>
+
+enum pll_clocks {
+	CPU_PLL1,	/* System PLL */
+	BUS_PLL2,	/* System Bus PLL*/
+	USBOTG_PLL3,    /* OTG USB PLL */
+	AUD_PLL4,	/* Audio PLL */
+	VID_PLL5,	/* Video PLL */
+	MLB_PLL6,	/* MLB PLL */
+	USBHOST_PLL7,   /* Host USB PLL */
+	ENET_PLL8,      /* ENET PLL */
+};
+
+#define SZ_DEC_1M		1000000
+
+/* Out-of-reset PFDs and clock source definitions */
+#define PLL2_PFD0_FREQ		352000000
+#define PLL2_PFD1_FREQ		594000000
+#define PLL2_PFD2_FREQ		400000000
+#define PLL2_PFD2_DIV_FREQ	200000000
+#define PLL3_PFD0_FREQ		720000000
+#define PLL3_PFD1_FREQ		540000000
+#define PLL3_PFD2_FREQ		508200000
+#define PLL3_PFD3_FREQ		454700000
+#define PLL3_80M		80000000
+#define PLL3_60M		60000000
+
+#define AHB_CLK_ROOT		132000000
+#define IPG_CLK_ROOT		66000000
+#define ENET_FREQ_0		25000000
+#define ENET_FREQ_1		50000000
+#define ENET_FREQ_2		100000000
+#define ENET_FREQ_3		125000000
+
+#define CONFIG_MX6_HCLK_FREQ      24000000
+
+static u32 __decode_pll(enum pll_clocks pll, u32 infreq)
+{
+	u32 div;
+
+	switch (pll) {
+	case CPU_PLL1:
+		div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_PLL_SYS) &
+			BM_ANADIG_PLL_SYS_DIV_SELECT;
+		return infreq * (div >> 1);
+	case BUS_PLL2:
+		div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_PLL_528) &
+			BM_ANADIG_PLL_528_DIV_SELECT;
+		return infreq * (20 + (div << 1));
+	case USBOTG_PLL3:
+		div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_USB2_PLL_480_CTRL) &
+			BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT;
+		return infreq * (20 + (div << 1));
+	case ENET_PLL8:
+		div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_PLL_ENET) &
+			BM_ANADIG_PLL_ENET_DIV_SELECT;
+		switch (div) {
+		default:
+		case 0:
+			return ENET_FREQ_0;
+		case 1:
+			return ENET_FREQ_1;
+		case 2:
+			return ENET_FREQ_2;
+		case 3:
+			return ENET_FREQ_3;
+		}
+	case AUD_PLL4:
+	case VID_PLL5:
+	case MLB_PLL6:
+	case USBHOST_PLL7:
+	default:
+		return 0;
+	}
+}
+
+static u32 __get_mcu_main_clk(void)
+{
+	u32 reg, freq;
+	reg = (__REG(MXC_CCM_CACRR) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
+	    MXC_CCM_CACRR_ARM_PODF_OFFSET;
+	freq = __decode_pll(CPU_PLL1, CONFIG_MX6_HCLK_FREQ);
+	return freq / (reg + 1);
+}
+
+static u32 __get_periph_clk(void)
+{
+	u32 reg;
+	reg = __REG(MXC_CCM_CBCDR);
+	if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+		reg = __REG(MXC_CCM_CBCMR);
+		switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK) >>
+			MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET) {
+		case 0:
+			return __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ);
+		case 1:
+		case 2:
+			return CONFIG_MX6_HCLK_FREQ;
+		default:
+			return 0;
+		}
+	} else {
+		reg = __REG(MXC_CCM_CBCMR);
+		switch ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) >>
+			MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET) {
+		default:
+		case 0:
+			return __decode_pll(BUS_PLL2, CONFIG_MX6_HCLK_FREQ);
+		case 1:
+			return PLL2_PFD2_FREQ;
+		case 2:
+			return PLL2_PFD0_FREQ;
+		case 3:
+			return PLL2_PFD2_DIV_FREQ;
+		}
+	}
+}
+
+static u32 __get_ipg_clk(void)
+{
+	u32 ahb_podf, ipg_podf;
+
+	ahb_podf = __REG(MXC_CCM_CBCDR);
+	ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
+			MXC_CCM_CBCDR_IPG_PODF_OFFSET;
+	ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
+			MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+	return __get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
+}
+
+u32 imx_get_gptclk(void)
+{
+	return __get_ipg_clk();
+}
+
+static u32 __get_ipg_per_clk(void)
+{
+	u32 podf;
+	u32 clk_root = __get_ipg_clk();
+
+	podf = __REG(MXC_CCM_CSCMR1) & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
+	return clk_root / (podf + 1);
+}
+
+u32 imx_get_uartclk(void)
+{
+	u32 freq = PLL3_80M, reg, podf;
+
+	reg = __REG(MXC_CCM_CSCDR1);
+	podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
+		MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
+	freq /= (podf + 1);
+
+	return freq;
+}
+
+static u32 __get_cspi_clk(void)
+{
+	u32 freq = PLL3_60M, reg, podf;
+
+	reg = __REG(MXC_CCM_CSCDR2);
+	podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
+		MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+	freq /= (podf + 1);
+
+	return freq;
+}
+
+static u32 __get_axi_clk(void)
+{
+	u32 clkroot;
+	u32 cbcdr =  __REG(MXC_CCM_CBCDR);
+	u32 podf = (cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK) >>
+		MXC_CCM_CBCDR_AXI_PODF_OFFSET;
+
+	if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
+		if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
+			clkroot = PLL2_PFD2_FREQ;
+		else
+			clkroot = PLL3_PFD1_FREQ;;
+	} else
+		clkroot = __get_periph_clk();
+
+	return  clkroot / (podf + 1);
+}
+
+static u32 __get_ahb_clk(void)
+{
+	u32 cbcdr =  __REG(MXC_CCM_CBCDR);
+	u32 podf = (cbcdr & MXC_CCM_CBCDR_AHB_PODF_MASK) \
+			>> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+
+	return  __get_periph_clk() / (podf + 1);
+}
+
+static u32 __get_emi_slow_clk(void)
+{
+	u32 cscmr1 =  __REG(MXC_CCM_CSCMR1);
+	u32 emi_clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK) >>
+		MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
+	u32 podf = (cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK) >>
+			MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
+
+	switch (emi_clk_sel) {
+	default:
+	case 0:
+		return __get_axi_clk() / (podf + 1);
+	case 1:
+		return __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ) /
+			(podf + 1);
+	case 2:
+		return PLL2_PFD2_FREQ / (podf + 1);
+	case 3:
+		return PLL2_PFD0_FREQ / (podf + 1);
+	}
+}
+
+static u32 __get_nfc_clk(void)
+{
+	u32 clkroot;
+	u32 cs2cdr =  __REG(MXC_CCM_CS2CDR);
+	u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) \
+			>> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
+	u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) \
+			>> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
+
+	switch ((cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
+		MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET) {
+		default:
+		case 0:
+			clkroot = PLL2_PFD0_FREQ;
+			break;
+		case 1:
+			clkroot = __decode_pll(BUS_PLL2, CONFIG_MX6_HCLK_FREQ);
+			break;
+		case 2:
+			clkroot = __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ);
+			break;
+		case 3:
+			clkroot = PLL2_PFD2_FREQ;
+			break;
+	}
+
+	return  clkroot / (pred+1) / (podf+1);
+}
+
+static u32 __get_ddr_clk(void)
+{
+	u32 cbcdr = __REG(MXC_CCM_CBCDR);
+	u32 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
+		MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
+
+	return __get_periph_clk() / (podf + 1);
+}
+
+static u32 __get_usdhc1_clk(void)
+{
+	u32 clkroot;
+	u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
+	u32 cscdr1 = __REG(MXC_CCM_CSCDR1);
+	u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
+		MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
+
+	if (cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL)
+		clkroot = PLL2_PFD0_FREQ;
+	else
+		clkroot = PLL2_PFD2_FREQ;
+
+	return clkroot / (podf + 1);
+}
+
+static u32 __get_usdhc2_clk(void)
+{
+	u32 clkroot;
+	u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
+	u32 cscdr1 = __REG(MXC_CCM_CSCDR1);
+	u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
+		MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
+
+	if (cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL)
+		clkroot = PLL2_PFD0_FREQ;
+	else
+		clkroot = PLL2_PFD2_FREQ;
+
+	return clkroot / (podf + 1);
+}
+
+static u32 __get_usdhc3_clk(void)
+{
+	u32 clkroot;
+	u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
+	u32 cscdr1 = __REG(MXC_CCM_CSCDR1);
+	u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
+		MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
+
+	if (cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL)
+		clkroot = PLL2_PFD0_FREQ;
+	else
+		clkroot = PLL2_PFD2_FREQ;
+
+	return clkroot / (podf + 1);
+}
+
+static u32 __get_usdhc4_clk(void)
+{
+	u32 clkroot;
+	u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
+	u32 cscdr1 = __REG(MXC_CCM_CSCDR1);
+	u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
+		MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
+
+	if (cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL)
+		clkroot = PLL2_PFD0_FREQ;
+	else
+		clkroot = PLL2_PFD2_FREQ;
+
+	return clkroot / (podf + 1);
+}
+
+u32 imx_get_mmcclk(void)
+{
+	return __get_usdhc3_clk();
+}
+
+u32 imx_get_fecclk(void)
+{
+	return __get_ipg_clk();
+}
+
+void imx_dump_clocks(void)
+{
+	u32 freq;
+
+	freq = __decode_pll(CPU_PLL1, CONFIG_MX6_HCLK_FREQ);
+	printf("mx6q pll1: %d\n", freq);
+	freq = __decode_pll(BUS_PLL2, CONFIG_MX6_HCLK_FREQ);
+	printf("mx6q pll2: %d\n", freq);
+	freq = __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ);
+	printf("mx6q pll3: %d\n", freq);
+	freq = __decode_pll(ENET_PLL8, CONFIG_MX6_HCLK_FREQ);
+	printf("mx6q pll8: %d\n", freq);
+	printf("mcu main:  %d\n", __get_mcu_main_clk());
+	printf("periph:    %d\n", __get_periph_clk());
+	printf("ipg:       %d\n", __get_ipg_clk());
+	printf("ipg per:   %d\n", __get_ipg_per_clk());
+	printf("cspi:      %d\n", __get_cspi_clk());
+	printf("axi:       %d\n", __get_axi_clk());
+	printf("ahb:       %d\n", __get_ahb_clk());
+	printf("emi slow:  %d\n", __get_emi_slow_clk());
+	printf("nfc:       %d\n", __get_nfc_clk());
+	printf("ddr:       %d\n", __get_ddr_clk());
+	printf("usdhc1:    %d\n", __get_usdhc1_clk());
+	printf("usdhc2:    %d\n", __get_usdhc2_clk());
+	printf("usdhc3:    %d\n", __get_usdhc3_clk());
+	printf("usdhc4:    %d\n", __get_usdhc4_clk());
+}
+
+void imx6_ipu_clk_enable(int di)
+{
+	u32 reg;
+
+	if (di == 1) {
+		reg = readl(MXC_CCM_CCGR3);
+		reg |= 0xC033;
+		writel(reg, MXC_CCM_CCGR3);
+	} else {
+		reg = readl(MXC_CCM_CCGR3);
+		reg |= 0x300F;
+		writel(reg, MXC_CCM_CCGR3);
+	}
+
+	reg = readl(MX6_ANATOP_BASE_ADDR + 0xF0);
+	reg &= ~0x00003F00;
+	reg |= 0x00001300;
+	writel(reg, MX6_ANATOP_BASE_ADDR + 0xF4);
+
+	reg = readl(MXC_CCM_CS2CDR);
+	reg &= ~0x00007E00;
+	reg |= 0x00001200;
+	writel(reg, MXC_CCM_CS2CDR);
+
+	reg = readl(MXC_CCM_CSCMR2);
+	reg |= 0x00000C00;
+	writel(reg, MXC_CCM_CSCMR2);
+
+	reg = 0x0002A953;
+	writel(reg, MXC_CCM_CHSCDR);
+}
diff --git a/arch/arm/mach-imx/speed.c b/arch/arm/mach-imx/speed.c
index 63e24b494f..6f8d20b741 100644
--- a/arch/arm/mach-imx/speed.c
+++ b/arch/arm/mach-imx/speed.c
@@ -24,6 +24,7 @@
 #include <asm-generic/div64.h>
 #include <common.h>
 #include <command.h>
+#include <complete.h>
 #include <mach/clock.h>
 
 /*
@@ -80,5 +81,6 @@ static int do_clocks(int argc, char *argv[])
 BAREBOX_CMD_START(dump_clocks)
 	.cmd		= do_clocks,
 	.usage		= "show clock frequencies",
+	BAREBOX_CMD_COMPLETE(empty_complete)
 BAREBOX_CMD_END
 
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 15f7c74315..3348a3cef7 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -68,6 +68,20 @@ endchoice
 
 endif
 
+menu "i.MX specific settings        "
+
+config MXS_OCOTP
+	tristate "OCOTP device"
+	help
+	  Device driver for the On-Chip One Time Programmable (OCOTP). Use the
+	  regular md/mw commands to read and write (if write is supported).
+
+	  Note that the OCOTP words are grouped consecutively (allocation
+	  internal view). Don't use register offsets here, the SET, CLR and
+	  TGL registers are not mapped!
+
+endmenu
+
 menu "Board specific settings       "
 
 if MACH_TX28
@@ -77,6 +91,7 @@ choice
 
 config MACH_TX28STK5
 	bool "TX28-stk5"
+	select MXS_OCOTP
 	help
 	  Select this entry if you are running the TX28 CPU module on the
 	  KARO TX28 Starterkit5.
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index f70a9944cf..172d928128 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -2,3 +2,4 @@ obj-y += imx.o iomux-imx.o reset-imx.o
 obj-$(CONFIG_DRIVER_VIDEO_STM) += imx_lcd_clk.o
 obj-$(CONFIG_ARCH_IMX23) += speed-imx23.o clocksource-imx23.o usb.o
 obj-$(CONFIG_ARCH_IMX28) += speed-imx28.o clocksource-imx28.o
+obj-$(CONFIG_MXS_OCOTP) += ocotp.o
diff --git a/arch/arm/mach-mxs/imx.c b/arch/arm/mach-mxs/imx.c
index a4dae205ca..c64f23ceb5 100644
--- a/arch/arm/mach-mxs/imx.c
+++ b/arch/arm/mach-mxs/imx.c
@@ -19,6 +19,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <complete.h>
 
 extern void imx_dump_clocks(void);
 
@@ -32,4 +33,5 @@ static int do_clocks(int argc, char *argv[])
 BAREBOX_CMD_START(dump_clocks)
 	.cmd		= do_clocks,
 	.usage		= "show clock frequencies",
+	BAREBOX_CMD_COMPLETE(empty_complete)
 BAREBOX_CMD_END
diff --git a/arch/arm/mach-mxs/include/mach/generic.h b/arch/arm/mach-mxs/include/mach/generic.h
index 50f25c5d1b..b69c65aac3 100644
--- a/arch/arm/mach-mxs/include/mach/generic.h
+++ b/arch/arm/mach-mxs/include/mach/generic.h
@@ -28,3 +28,13 @@
 #else
 # define cpu_is_mx28()	(0)
 #endif
+
+#define cpu_is_mx1()	(0)
+#define cpu_is_mx21()	(0)
+#define cpu_is_mx25()	(0)
+#define cpu_is_mx27()	(0)
+#define cpu_is_mx31()	(0)
+#define cpu_is_mx35()	(0)
+#define cpu_is_mx51()	(0)
+#define cpu_is_mx53()	(0)
+#define cpu_is_mx6()	(0)
diff --git a/arch/arm/mach-mxs/include/mach/imx23-regs.h b/arch/arm/mach-mxs/include/mach/imx23-regs.h
index cc8c03e8bb..60f5bf9d6f 100644
--- a/arch/arm/mach-mxs/include/mach/imx23-regs.h
+++ b/arch/arm/mach-mxs/include/mach/imx23-regs.h
@@ -32,6 +32,7 @@
 #define IMX_DBGUART_BASE	0x80070000
 #define IMX_TIM1_BASE		0x80068000
 #define IMX_IOMUXC_BASE		0x80018000
+#define IMX_OCOTP_BASE		0x8002c000
 #define IMX_WDT_BASE		0x8005c000
 #define IMX_CCM_BASE		0x80040000
 #define IMX_I2C1_BASE		0x80058000
diff --git a/arch/arm/mach-mxs/include/mach/imx28-regs.h b/arch/arm/mach-mxs/include/mach/imx28-regs.h
index 0c97c4c2f2..9a2052c159 100644
--- a/arch/arm/mach-mxs/include/mach/imx28-regs.h
+++ b/arch/arm/mach-mxs/include/mach/imx28-regs.h
@@ -29,6 +29,7 @@
 #define IMX_SSP2_BASE		0x80014000
 #define IMX_SSP3_BASE		0x80016000
 #define IMX_IOMUXC_BASE		0x80018000
+#define IMX_OCOTP_BASE		0x8002c000
 #define IMX_FB_BASE		0x80030000
 #define IMX_CCM_BASE		0x80040000
 #define IMX_WDT_BASE		0x80056000
diff --git a/arch/arm/mach-mxs/include/mach/ocotp.h b/arch/arm/mach-mxs/include/mach/ocotp.h
new file mode 100644
index 0000000000..86b30c96e1
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/ocotp.h
@@ -0,0 +1,12 @@
+/*
+ * Header file for mxs ocotp driver - same license as driver
+ *
+ * Copyright (C) 2012 by Wolfram Sang, Pengutronix e.K.
+ */
+
+#ifndef __MACH_OCOTP_H
+#define __MACH_OCOTP_H
+
+int mxs_ocotp_read(void *buf, int count, int offset);
+
+#endif /* __MACH_OCOTP_H */
diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c
new file mode 100644
index 0000000000..38f9ffde16
--- /dev/null
+++ b/arch/arm/mach-mxs/ocotp.c
@@ -0,0 +1,139 @@
+/*
+ * ocotp.c - barebox driver for the On-Chip One Time Programmable for MXS
+ *
+ * Copyright (C) 2012 by Wolfram Sang, Pengutronix e.K.
+ * based on the kernel driver which is
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <xfuncs.h>
+#include <errno.h>
+#include <param.h>
+#include <fcntl.h>
+#include <malloc.h>
+#include <io.h>
+#include <clock.h>
+
+#include <mach/generic.h>
+#include <mach/ocotp.h>
+#include <mach/imx-regs.h>
+
+#define DRIVERNAME "ocotp"
+
+#define OCOTP_WORD_OFFSET		0x20
+
+#define BM_OCOTP_CTRL_BUSY		(1 << 8)
+#define BM_OCOTP_CTRL_ERROR		(1 << 9)
+#define BM_OCOTP_CTRL_RD_BANK_OPEN	(1 << 12)
+
+struct ocotp_priv {
+	struct cdev cdev;
+	void __iomem *base;
+};
+
+static ssize_t mxs_ocotp_cdev_read(struct cdev *cdev, void *buf, size_t count,
+		ulong offset, ulong flags)
+{
+	struct ocotp_priv *priv = cdev->priv;
+	void __iomem *base = priv->base;
+	size_t size = min((ulong)count, cdev->size - offset);
+	uint64_t start;
+	int i;
+
+	/*
+	 * clk_enable(hbus_clk) for ocotp can be skipped
+	 * as it must be on when system is running.
+	 */
+
+	/* try to clear ERROR bit */
+	writel(BM_OCOTP_CTRL_ERROR, base + BIT_CLR);
+
+	/* check both BUSY and ERROR cleared */
+	start = get_time_ns();
+	while (readl(base) & (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR))
+		if (is_timeout(start, MSECOND))
+			return -ETIMEDOUT;
+
+	/* open OCOTP banks for read */
+	writel(BM_OCOTP_CTRL_RD_BANK_OPEN, base + BIT_SET);
+
+	/* approximately wait 32 hclk cycles */
+	udelay(1);
+
+	/* poll BUSY bit becoming cleared */
+	start = get_time_ns();
+	while (readl(base) & BM_OCOTP_CTRL_BUSY)
+		if (is_timeout(start, MSECOND))
+			return -ETIMEDOUT;
+
+	for (i = 0; i < size; i++)
+		/* When reading bytewise, we need to hop over the SET/CLR/TGL regs */
+		((u8 *)buf)[i] = readb(base + OCOTP_WORD_OFFSET +
+				(((i + offset) & 0xfc) << 2) + ((i + offset) & 3));
+
+	/* close banks for power saving */
+	writel(BM_OCOTP_CTRL_RD_BANK_OPEN, base + BIT_CLR);
+
+	return size;
+}
+
+static struct file_operations mxs_ocotp_ops = {
+	.read	= mxs_ocotp_cdev_read,
+	.lseek	= dev_lseek_default,
+};
+
+static int mxs_ocotp_probe(struct device_d *dev)
+{
+	int err;
+	struct ocotp_priv *priv = xzalloc(sizeof (*priv));
+
+	priv->base = dev_request_mem_region(dev, 0);
+	priv->cdev.dev = dev;
+	priv->cdev.ops = &mxs_ocotp_ops;
+	priv->cdev.priv = priv;
+	priv->cdev.size = cpu_is_mx23() ? 128 : 160;
+	priv->cdev.name = DRIVERNAME;
+
+	err = devfs_create(&priv->cdev);
+	if (err < 0)
+		return err;
+
+	return 0;
+}
+
+static struct driver_d mxs_ocotp_driver = {
+	.name	= DRIVERNAME,
+	.probe	= mxs_ocotp_probe,
+};
+
+static int mxs_ocotp_init(void)
+{
+	register_driver(&mxs_ocotp_driver);
+
+	return 0;
+}
+coredevice_initcall(mxs_ocotp_init);
+
+int mxs_ocotp_read(void *buf, int count, int offset)
+{
+	struct cdev *cdev;
+	int ret;
+
+	cdev = cdev_open(DRIVERNAME, O_RDONLY);
+	if (!cdev)
+		return -ENODEV;
+
+	ret = cdev_read(cdev, buf, count, offset, 0);
+
+	cdev_close(cdev);
+
+	return ret;
+}
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 8810e6d9ef..53b0c601c2 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -20,6 +20,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <io.h>
 #include <mach/netx-regs.h>
 #include "eth_firmware.h"
 
@@ -33,11 +34,11 @@ struct fw_header {
 
 static int xc_check_ptr(int xcno, unsigned long adr, unsigned int size)
 {
-	if( adr >= NETX_PA_XMAC(xcno) &&
+	if (adr >= NETX_PA_XMAC(xcno) &&
 	    adr + size < NETX_PA_XMAC(xcno) + XMAC_MEM_SIZE)
 		return 0;
 
-	if( adr >= NETX_PA_XPEC(xcno) &&
+	if (adr >= NETX_PA_XPEC(xcno) &&
 	    adr + size < NETX_PA_XPEC(xcno) + XPEC_MEM_SIZE)
 		return 0;
 
@@ -45,18 +46,17 @@ static int xc_check_ptr(int xcno, unsigned long adr, unsigned int size)
 	return -1;
 }
 
-static int xc_patch(int xcno, void *patch, int count)
+static int xc_patch(int xcno, const u32 *patch, int count)
 {
-	unsigned int adr, val, *p = patch;
+	unsigned int adr, val;
 
-/*	printf("%s: patch: %p size: %d\n",__FUNCTION__,patch,count); */
 	int i;
-	for(i=0; i<count; i++) {
-		adr = *p++;
-		val = *p++;
-		if( xc_check_ptr(xcno, adr, 1) < 0)
+	for (i = 0; i < count; i++) {
+		adr = *patch++;
+		val = *patch++;
+		if (xc_check_ptr(xcno, adr, 1) < 0)
 			return -1;
-		*(volatile unsigned int *)adr = val;
+		writel(val, adr);
 	}
 	return 0;
 }
@@ -64,22 +64,23 @@ static int xc_patch(int xcno, void *patch, int count)
 static void memset32(void *s, int c, int n)
 {
 	int i;
-	unsigned int *t = s;
+	u32 *t = s;
 
-	for(i=0; i<(n>>2); i++)
+	for (i = 0; i < (n >> 2); i++)
 		*t++ = 0;
 }
 
-static void memcpy32(void *trg, void *src, int size)
+static void memcpy32(void *trg, const void *src, int size)
 {
 	int i;
-	unsigned int *t = trg;
-	unsigned int *s = src;
-	for(i=0; i<(size>>2); i++)
+	u32 *t = trg;
+	const u32 *s = src;
+	for (i = 0; i < (size >> 2); i++)
 		*t++ = *s++;
 }
 
-int loadxc(int xcno) {
+int loadxc(int xcno)
+{
 	/* stop xmac / xpec */
 	XMAC_REG(xcno, XMAC_RPU_HOLD_PC) = RPU_HOLD_PC;
 	XMAC_REG(xcno, XMAC_TPU_HOLD_PC) = TPU_HOLD_PC;
@@ -92,7 +93,7 @@ int loadxc(int xcno) {
 	memset32((void*)NETX_PA_XMAC(xcno), 0, 0x800);
 
 	/* can't use barebox memcpy here, we need 32bit accesses */
-	if(xcno == 0) {
+	if (xcno == 0) {
 		memcpy32((void*)(NETX_PA_XMAC(xcno) + XMAC_RPU_PROGRAM_START), rpu_eth0, sizeof(rpu_eth0));
 		memcpy32((void*)(NETX_PA_XMAC(xcno) + XMAC_TPU_PROGRAM_START), tpu_eth0, sizeof(tpu_eth0));
 		memcpy32((void*)NETX_PA_XPEC(xcno) + XPEC_RAM_START, xpec_eth0_mac, sizeof(xpec_eth0_mac));
diff --git a/arch/arm/mach-netx/include/mach/netx-devices.h b/arch/arm/mach-netx/include/mach/netx-devices.h
new file mode 100644
index 0000000000..9c64adb5da
--- /dev/null
+++ b/arch/arm/mach-netx/include/mach/netx-devices.h
@@ -0,0 +1,73 @@
+/*
+ * (c) 2012 Pengutronix, Juergen Beisert <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _NETX_DEVICES_H
+# define _NETX_DEVICES_H
+
+#include <mach/netx-regs.h>
+
+static inline struct device_d *netx_add_uart(resource_size_t base, int index)
+{
+	return add_generic_device("netx_serial", index, NULL,
+				base, 0x40, IORESOURCE_MEM, NULL);
+}
+
+static inline struct device_d *netx_add_uart0(void)
+{
+	return netx_add_uart(NETX_PA_UART0, 0);
+}
+
+static inline struct device_d *netx_add_uart1(void)
+{
+	return netx_add_uart(NETX_PA_UART1, 1);
+}
+
+static inline struct device_d *netx_add_uart3(void)
+{
+	return netx_add_uart(NETX_PA_UART2, 2);
+}
+
+/* parallel flash connected to the SRAM interface */
+static inline struct device_d *netx_add_pflash(resource_size_t size)
+{
+	return add_cfi_flash_device(0, NETX_CS0_BASE, size, 0);
+}
+
+static inline struct device_d *netx_add_eth(int index, void *pdata)
+{
+	return add_generic_device("netx-eth", index, NULL,
+					0, 0, IORESOURCE_MEM, pdata);
+}
+
+static inline struct device_d *netx_add_eth0(void *pdata)
+{
+	return netx_add_eth(0, pdata);
+}
+
+static inline struct device_d *netx_add_eth1(void *pdata)
+{
+	return netx_add_eth(1, pdata);
+}
+
+static inline struct device_d *netx_add_eth2(void *pdata)
+{
+	return netx_add_eth(2, pdata);
+}
+
+static inline struct device_d *netx_add_eth3(void *pdata)
+{
+	return netx_add_eth(3, pdata);
+}
+
+#endif /* _NETX_DEVICES_H */
diff --git a/arch/arm/mach-netx/include/mach/netx-regs.h b/arch/arm/mach-netx/include/mach/netx-regs.h
index c2278cdc48..8496f3a491 100644
--- a/arch/arm/mach-netx/include/mach/netx-regs.h
+++ b/arch/arm/mach-netx/include/mach/netx-regs.h
@@ -20,6 +20,11 @@
 #ifndef __ASM_ARCH_NETX_REGS_H
 #define __ASM_ARCH_NETX_REGS_H
 
+#define NETX_SDRAM_BASE 0x80000000
+#define NETX_CS0_BASE 0xc0000000
+#define NETX_CS1_BASE 0xc8000000
+#define NETX_CS2_BASE 0xd0000000
+
 #define NETX_IO_PHYS 0x00100000
 #define io_p2v(x) (x)
 #define __REG(base,ofs)       (*((volatile unsigned long *)(io_p2v(base) + ofs)))
@@ -59,7 +64,7 @@
 
 #define NETX_PA_SYSTEM  (NETX_IO_PHYS + NETX_OFS_SYSTEM)
 #define NETX_PA_MEMCR   (NETX_IO_PHYS + NETX_OFS_MEMCR)
-#define NETX_PA_DPRAM   (NETX_IO_PHYS + NETX_OFS_DPRAM)
+#define NETX_PA_DPMAS   (NETX_IO_PHYS + NETX_OFS_DPRAM)
 #define NETX_PA_GPIO    (NETX_IO_PHYS + NETX_OFS_GPIO)
 #define NETX_PA_PIO     (NETX_IO_PHYS + NETX_OFS_PIO)
 #define NETX_PA_UART0   (NETX_IO_PHYS + NETX_OFS_UART0)
diff --git a/arch/arm/mach-omap/devices-gpmc-nand.c b/arch/arm/mach-omap/devices-gpmc-nand.c
index 54625ca9ab..0fc32f1d07 100644
--- a/arch/arm/mach-omap/devices-gpmc-nand.c
+++ b/arch/arm/mach-omap/devices-gpmc-nand.c
@@ -68,8 +68,8 @@ int gpmc_generic_nand_devices_init(int cs, int width,
 	/* Configure GPMC CS before register */
 	gpmc_cs_config(nand_plat.cs, nand_cfg);
 
-	add_generic_device("gpmc_nand", -1, NULL, OMAP_GPMC_BASE, 1024 * 4,
-			   IORESOURCE_MEM, &nand_plat);
+	add_generic_device("gpmc_nand", DEVICE_ID_DYNAMIC, NULL, OMAP_GPMC_BASE,
+			1024 * 4, IORESOURCE_MEM, &nand_plat);
 
 	return 0;
 }
diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
index f8d3396f42..c7854751ad 100644
--- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
+++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
@@ -156,6 +156,9 @@ struct s32ktimer {
 #define OMAP4430_ES2_0	2
 #define OMAP4430_ES2_1	3
 #define OMAP4430_ES2_2	4
+#define OMAP4430_ES2_3	5
+#define OMAP4460_ES1_0	6
+#define OMAP4460_ES1_1	7
 
 struct ddr_regs {
 	u32 tim1;
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index db26a594ab..5092242103 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -9,6 +9,26 @@
 #include <mach/xload.h>
 #include <mach/gpmc.h>
 
+/*
+ *  The following several lines are taken from U-Boot to support
+ * recognizing more revisions of OMAP4 chips.
+ */
+
+#define MIDR_CORTEX_A9_R0P1	0x410FC091
+#define MIDR_CORTEX_A9_R1P2	0x411FC092
+#define MIDR_CORTEX_A9_R1P3	0x411FC093
+#define MIDR_CORTEX_A9_R2P10	0x412FC09A
+
+#define CONTROL_ID_CODE         0x4A002204
+
+#define OMAP4_CONTROL_ID_CODE_ES1_0     0x0B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_0     0x1B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_1     0x3B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_2     0x4B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_3     0x6B95C02F
+#define OMAP4460_CONTROL_ID_CODE_ES1_0  0x0B94E02F
+#define OMAP4460_CONTROL_ID_CODE_ES1_1  0x2B94E02F
+
 void __noreturn reset_cpu(unsigned long addr)
 {
 	writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
@@ -362,22 +382,45 @@ static unsigned int cortex_a9_rev(void)
 
 unsigned int omap4_revision(void)
 {
-	unsigned int chip_rev = 0;
 	unsigned int rev = cortex_a9_rev();
 
 	switch(rev) {
-	case 0x410FC091:
+	case MIDR_CORTEX_A9_R0P1:
 		return OMAP4430_ES1_0;
-	case 0x411FC092:
-		chip_rev = (readl(OMAP44XX_CTRL_BASE + 0x204)  >> 28) & 0xF;
-		if (chip_rev == 3)
+	case MIDR_CORTEX_A9_R1P2:
+		switch (readl(CONTROL_ID_CODE)) {
+		case OMAP4_CONTROL_ID_CODE_ES2_0:
+			return OMAP4430_ES2_0;
+			break;
+		case OMAP4_CONTROL_ID_CODE_ES2_1:
 			return OMAP4430_ES2_1;
-		else if (chip_rev >= 4)
+			break;
+		case OMAP4_CONTROL_ID_CODE_ES2_2:
 			return OMAP4430_ES2_2;
-		else
+			break;
+		default:
 			return OMAP4430_ES2_0;
+			break;
+		}
+		break;
+	case MIDR_CORTEX_A9_R1P3:
+		return OMAP4430_ES2_3;
+		break;
+	case MIDR_CORTEX_A9_R2P10:
+		switch (readl(CONTROL_ID_CODE)) {
+		case OMAP4460_CONTROL_ID_CODE_ES1_1:
+			return OMAP4460_ES1_1;
+			break;
+		case OMAP4460_CONTROL_ID_CODE_ES1_0:
+		default:
+			return OMAP4460_ES1_0;
+			break;
+		}
+		break;
+	default:
+		return OMAP4430_SILICON_ID_INVALID;
+		break;
 	}
-	return OMAP4430_SILICON_ID_INVALID;
 }
 
 /*
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 750f466527..029fd8b6f2 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -3,10 +3,12 @@ if ARCH_PXA
 config ARCH_TEXT_BASE
 	hex
 	default 0xa0000000 if MACH_MIOA701
+	default 0xa3f00000 if MACH_PCM027
 
 config BOARDINFO
 	string
 	default "Scoter Mitac Mio A701" if MACH_MIOA701
+	default "Phytec phyCORE-PXA270" if MACH_PCM027
 
 # ----------------------------------------------------------
 
@@ -37,6 +39,14 @@ config MACH_MIOA701
 	select PWM
 	help
 	  Say Y here if you are using a Mitac Mio A701 smartphone
+
+config MACH_PCM027
+	bool "Phytec phyCORE-PXA270"
+	select HAS_CFI
+	select MACH_HAS_LOWLEVEL_INIT
+	select HAVE_MMU
+	help
+	  Say Y here if you are using a Phytec phyCORE PXA270
 	  board
 endchoice