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authorSascha Hauer <s.hauer@pengutronix.de>2014-07-17 16:16:53 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2014-07-18 14:10:29 +0200
commitd985d2276345b6627b8887d0f81cd932beed62cb (patch)
treede8888a7df74f5cba0a27fd2677c5fb3c2a959be /arch/arm
parent239b6559ed5d65cc3e08eae66eb862fefe651e33 (diff)
downloadbarebox-d985d2276345b6627b8887d0f81cd932beed62cb.tar.gz
barebox-d985d2276345b6627b8887d0f81cd932beed62cb.tar.xz
ARM: i.MX: esdctl: i.MX53 has esdctl v4, not v3
On the i.MX53 this has the effect that in early init only half of the memory bank is detected and the barebox image is place in the middle of SDRAM. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-imx/esdctl.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index bb8fec2d45..811592f7da 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -549,9 +549,9 @@ void __naked __noreturn imx53_barebox_entry(void *boarddata)
unsigned long base, size;
upper_or_coalesced_range(MX53_CSD0_BASE_ADDR,
- imx_v3_sdram_size((void *)MX53_ESDCTL_BASE_ADDR, 0),
+ imx_v4_sdram_size((void *)MX53_ESDCTL_BASE_ADDR, 0),
MX53_CSD1_BASE_ADDR,
- imx_v3_sdram_size((void *)MX53_ESDCTL_BASE_ADDR, 1),
+ imx_v4_sdram_size((void *)MX53_ESDCTL_BASE_ADDR, 1),
&base, &size);
barebox_arm_entry(base, size, boarddata);