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author | Trent Piepho <trent.piepho@synapse.com> | 2020-09-25 16:43:14 -0700 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-09-29 09:04:34 +0200 |
commit | c6347aed39e3305198d919b15fe8887154b4ebbf (patch) | |
tree | a790557ce951eb83eacc68ac3cf15befe7a450d0 /arch/arm | |
parent | 874b18607c5181530a64a0e02cf699efa5afcae4 (diff) | |
download | barebox-c6347aed39e3305198d919b15fe8887154b4ebbf.tar.gz barebox-c6347aed39e3305198d919b15fe8887154b4ebbf.tar.xz |
ARM: am335x: Enable TSC/ADC clock
Now that there is a Barebox driver for the ADC, enable the clock to the
TSC/ADC block.
This machine doesn't use common clock framework clocks in Barebox, and
instead enables any clock that might get used. Enalbing the clock could
be made conditional based on enabling the driver, but none of the other
clocks do this.
Signed-off-by: Trent Piepho <trent.piepho@synapse.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-omap/am33xx_clock.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-omap/include/mach/am33xx-clock.h | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-omap/am33xx_clock.c b/arch/arm/mach-omap/am33xx_clock.c index 0a49038270..8fa2c70aa2 100644 --- a/arch/arm/mach-omap/am33xx_clock.c +++ b/arch/arm/mach-omap/am33xx_clock.c @@ -165,6 +165,10 @@ void am33xx_enable_per_clocks(void) __raw_writel(PRCM_MOD_EN, CM_PER_USB0_CLKCTRL); while ((__raw_readl(CM_PER_USB0_CLKCTRL) & 0x30000) != 0x0); + /* TSC & ADC */ + __raw_writel(PRCM_MOD_EN, CM_WKUP_ADC_TSC_CLKCTRL); + while (__raw_readl(CM_WKUP_ADC_TSC_CLKCTRL) != PRCM_MOD_EN); + clkdcoldo = __raw_readl(CM_CLKDCOLDO_DPLL_PER); clkdcoldo = clkdcoldo | 0x100; __raw_writel(clkdcoldo, CM_CLKDCOLDO_DPLL_PER); diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h index 284d5f8cf6..e71ecbcd24 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-clock.h +++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h @@ -138,6 +138,7 @@ #define CM_PER_I2C1_CLKCTRL (CM_PER + 0x48) /* I2C1 */ #define CM_PER_I2C2_CLKCTRL (CM_PER + 0x44) /* I2C2 */ #define CM_WKUP_GPIO0_CLKCTRL (CM_WKUP + 0x8) /* GPIO0 */ +#define CM_WKUP_ADC_TSC_CLKCTRL (CM_WKUP + 0xbc)/* TSCADC */ #define CM_PER_MMC0_CLKCTRL (CM_PER + 0x3C) #define CM_PER_MMC1_CLKCTRL (CM_PER + 0xF4) |