path: root/arch/arm
diff options
authorAhmad Fatoum <>2021-10-30 16:19:34 +0200
committerSascha Hauer <>2021-11-01 10:09:58 +0100
commit79accc24c71592d579e9b30b5901193a73da5a40 (patch)
tree5cac0a136b0fc1674444b721d32ab42e8d8ed6de /arch/arm
parentd136ec5ac6882ba85842c542de472a39b646a101 (diff)
ARM: i.MX8M: nxp-imx8mn-evk: use regular i2c read for device detection
The barebox-nxp-imx8mn-evk image supports both DDR4 and LPDDR4 variants by probing for the PMIC in use as the former uses a BD71847 and the latter a PCA9450B. The PCA9450B was observed to hang on the 0-byte (probe) reads. This results in I/O errors during later PMIC writes and the image would only boot on the EVKs with DDR4, which have the other PMIC. Fix this by switching to a 1 byte read instead. Change tested on i.MX8MN DDR4 EVK as well as another board with LPDDR4. While at it, note the address of the PMIC in the error message, so it's clear, what the result of the i2c probe was. Signed-off-by: Ahmad Fatoum <> Link: Signed-off-by: Sascha Hauer <>
Diffstat (limited to 'arch/arm')
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/boards/nxp-imx8mn-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mn-evk/lowlevel.c
index bac632aa43..de53213ebc 100644
--- a/arch/arm/boards/nxp-imx8mn-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mn-evk/lowlevel.c
@@ -56,7 +56,7 @@ static void pmic_reg_write(void *i2c, int addr, int reg, uint8_t val)
ret = i2c_fsl_xfer(i2c, msgs, ARRAY_SIZE(msgs));
if (ret != 1)
- pr_err("Failed to write to pmic %d\n", ret);
+ pr_err("Failed to write to pmic@%x: %d\n", addr, ret);
static int power_init_board_pca9450(void *i2c, int addr)
@@ -66,7 +66,8 @@ static int power_init_board_pca9450(void *i2c, int addr)
.addr = addr,
.buf = buf,
- .flags = I2C_M_RD
+ .flags = I2C_M_RD,
+ .len = 1,