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author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-04-09 12:24:49 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-04-09 12:24:49 +0200 |
commit | 86762248de707c1d5bc59f7ddf73c47fef2e2999 (patch) | |
tree | 48811e5cfee861b1711b40e67b32b28ce85f2b71 /arch/arm | |
parent | 0272ec9ca9fe43a5d57a603093dc6787e6a3a7e4 (diff) | |
parent | 6daccb9de039ab8b2db41200d64b530d14e428a6 (diff) | |
download | barebox-86762248de707c1d5bc59f7ddf73c47fef2e2999.tar.gz barebox-86762248de707c1d5bc59f7ddf73c47fef2e2999.tar.xz |
Merge branch 'for-next/zynqmp'
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/dts/zynqmp-clk.dtsi | 155 | ||||
-rw-r--r-- | arch/arm/dts/zynqmp-zcu104-revA.dts | 2 | ||||
-rw-r--r-- | arch/arm/dts/zynqmp.dtsi | 17 | ||||
-rw-r--r-- | arch/arm/mach-zynqmp/firmware-zynqmp.c | 3 | ||||
-rw-r--r-- | arch/arm/mach-zynqmp/include/mach/firmware-zynqmp.h | 2 |
5 files changed, 177 insertions, 2 deletions
diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi new file mode 100644 index 0000000000..8d5ec37125 --- /dev/null +++ b/arch/arm/dts/zynqmp-clk.dtsi @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Clock specification for Xilinx ZynqMP + * + * (C) Copyright 2017, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + */ + +#include <dt-bindings/clock/xlnx,zynqmp-clk.h> + +&zynqmp_firmware { + zynqmp_clk: clock-controller { + #clock-cells = <1>; + compatible = "xlnx,zynqmp-clk"; + clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; + clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; + }; +}; + +/ { + pss_ref_clk: pss_ref_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33333333>; + }; + + video_clk: video_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + pss_alt_ref_clk: pss_alt_ref_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + gt_crx_ref_clk: gt_crx_ref_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <108000000>; + }; + + aux_ref_clk: aux_ref_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; +}; + +&can0 { + clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&can1 { + clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&cpu0 { + clocks = <&zynqmp_clk ACPU>; +}; + +&gem0 { + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM_TSU>; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; +}; + +&gem1 { + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM_TSU>; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; +}; + +&gem2 { + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM_TSU>; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; +}; + +&gem3 { + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM_TSU>; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; +}; + +&gpio { + clocks = <&zynqmp_clk LPD_LSBUS>; +}; + +&i2c0 { + clocks = <&zynqmp_clk I2C0_REF>; +}; + +&i2c1 { + clocks = <&zynqmp_clk I2C1_REF>; +}; + +&pcie { + clocks = <&zynqmp_clk PCIE_REF>; +}; + +&sata { + clocks = <&zynqmp_clk SATA_REF>; +}; + +&sdhci0 { + clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&sdhci1 { + clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&spi0 { + clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&spi1 { + clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&ttc0 { + clocks = <&zynqmp_clk LPD_LSBUS>; +}; + +&ttc1 { + clocks = <&zynqmp_clk LPD_LSBUS>; +}; + +&ttc2 { + clocks = <&zynqmp_clk LPD_LSBUS>; +}; + +&ttc3 { + clocks = <&zynqmp_clk LPD_LSBUS>; +}; + +&uart0 { + clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&uart1 { + clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&usb0 { + clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; +}; + +&usb1 { + clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; +}; + +&watchdog0 { + clocks = <&zynqmp_clk WDT>; +}; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 8c467ee970..c03112d7a0 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -8,3 +8,5 @@ */ #include <arm64/xilinx/zynqmp-zcu104-revA.dts> +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi new file mode 100644 index 0000000000..59984ee758 --- /dev/null +++ b/arch/arm/dts/zynqmp.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP + * + * (C) Copyright 2014 - 2015, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + */ + +/ { + firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + }; + }; +}; diff --git a/arch/arm/mach-zynqmp/firmware-zynqmp.c b/arch/arm/mach-zynqmp/firmware-zynqmp.c index a3ee992832..f2187e97be 100644 --- a/arch/arm/mach-zynqmp/firmware-zynqmp.c +++ b/arch/arm/mach-zynqmp/firmware-zynqmp.c @@ -30,8 +30,6 @@ #define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \ ZYNQMP_TZ_VERSION_MINOR) -#define PAYLOAD_ARG_CNT 4 - /* SMC SIP service Call Function Identifier Prefix */ #define PM_SIP_SVC 0xC2000000 @@ -577,6 +575,7 @@ static int zynqmp_firmware_probe(struct device_d *dev) dev_dbg(dev, "Trustzone version v%d.%d\n", pm_tz_version >> 16, pm_tz_version & 0xFFFF); + of_platform_populate(dev->device_node, NULL, dev); out: if (ret) do_fw_call = do_fw_call_fail; diff --git a/arch/arm/mach-zynqmp/include/mach/firmware-zynqmp.h b/arch/arm/mach-zynqmp/include/mach/firmware-zynqmp.h index 7a65f781fb..9e7a2e34f7 100644 --- a/arch/arm/mach-zynqmp/include/mach/firmware-zynqmp.h +++ b/arch/arm/mach-zynqmp/include/mach/firmware-zynqmp.h @@ -15,6 +15,8 @@ #ifndef FIRMWARE_ZYNQMP_H_ #define FIRMWARE_ZYNQMP_H_ +#define PAYLOAD_ARG_CNT 4 + enum pm_ioctl_id { IOCTL_SET_PLL_FRAC_MODE = 8, IOCTL_GET_PLL_FRAC_MODE, |