diff options
| author | Lucas Stach <l.stach@pengutronix.de> | 2017-07-31 20:21:02 +0200 |
|---|---|---|
| committer | Lucas Stach <l.stach@pengutronix.de> | 2017-07-31 20:21:02 +0200 |
| commit | 8b8d55e3c2a1f8b3b6323f59f90da6b51196402c (patch) | |
| tree | 195a0c8a4f8ab427a2cedb67c32f7c8430e8ac25 /arch/arm | |
| parent | d6d7441e90d7859c60cba8b9bc160d7d24692452 (diff) | |
| parent | a0a5a7b84ff8a4dbae93404f88aeedf1c341bc20 (diff) | |
| download | barebox-8b8d55e3c2a1f8b3b6323f59f90da6b51196402c.tar.gz barebox-8b8d55e3c2a1f8b3b6323f59f90da6b51196402c.tar.xz | |
Merge branch 'for-next/imx'
Diffstat (limited to 'arch/arm')
76 files changed, 5263 insertions, 2641 deletions
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 9bbdd684fa..d6011adb28 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_MACH_FREESCALE_MX51_PDK) += freescale-mx51-babbage/ obj-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += freescale-mx53-qsb/ obj-$(CONFIG_MACH_FREESCALE_MX53_SMD) += freescale-mx53-smd/ obj-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += freescale-mx53-vmx53/ +obj-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += freescale-mx7-sabresd/ obj-$(CONFIG_MACH_GE863) += telit-evk-pro3/ obj-$(CONFIG_MACH_GK802) += gk802/ obj-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += globalscale-guruplug/ @@ -89,6 +90,7 @@ obj-$(CONFIG_MACH_PCM043) += phytec-phycore-imx35/ obj-$(CONFIG_MACH_PCM049) += phytec-phycore-omap4460/ obj-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += phytec-som-am335x/ obj-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += phytec-som-imx6/ +obj-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += phytec-phycore-imx7/ obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += plathome-openblocks-ax3/ obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += plathome-openblocks-a6/ obj-$(CONFIG_MACH_PM9261) += pm9261/ diff --git a/arch/arm/boards/cm-fx6/Makefile b/arch/arm/boards/cm-fx6/Makefile index 3a773bbf7b..01c7a259e9 100644 --- a/arch/arm/boards/cm-fx6/Makefile +++ b/arch/arm/boards/cm-fx6/Makefile @@ -1,3 +1,2 @@ obj-y += board.o -extra-y += flash-header-mx6-cm-fx6.dcd.S flash-header-mx6-cm-fx6.dcd lwl-y += lowlevel.o diff --git a/arch/arm/boards/dfi-fs700-m60/Makefile b/arch/arm/boards/dfi-fs700-m60/Makefile index 2d0ec7c1ce..01c7a259e9 100644 --- a/arch/arm/boards/dfi-fs700-m60/Makefile +++ b/arch/arm/boards/dfi-fs700-m60/Makefile @@ -1,4 +1,2 @@ obj-y += board.o -extra-y += flash-header-fs700-m60-6s.dcd.S flash-header-fs700-m60-6q-nanya.dcd.S flash-header-fs700-m60-6q-micron.dcd.S -extra-y += flash-header-fs700-m60-6s.dcd flash-header-fs700-m60-6q-nanya.dcd flash-header-fs700-m60-6q-micron.dcd lwl-y += lowlevel.o diff --git a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg index 835d0c7d4c..2be0210dd6 100644 --- a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg +++ b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg @@ -2,96 +2,99 @@ loadaddr 0x27800000 soc imx6 dcdofs 0x400 -wm 32 0x020e050c 0x00000030 -wm 32 0x020e0510 0x00020030 -wm 32 0x020e0514 0x00020030 -wm 32 0x020e0518 0x00000030 -wm 32 0x020e051c 0x00000030 -wm 32 0x020e0520 0x00020030 -wm 32 0x020e0524 0x00000030 -wm 32 0x020e0528 0x00020030 -wm 32 0x020e056c 0x00020030 -wm 32 0x020e0578 0x00020030 -wm 32 0x020e057c 0x00020030 -wm 32 0x020e0588 0x00020030 -wm 32 0x020e058c 0x00000000 -wm 32 0x020e0590 0x00003000 -wm 32 0x020e0594 0x00020030 -wm 32 0x020e0598 0x00003000 -wm 32 0x020e059c 0x00003030 -wm 32 0x020e05a0 0x00003030 -wm 32 0x020e05a8 0x00000030 -wm 32 0x020e05ac 0x00020030 -wm 32 0x020e05b0 0x00000030 -wm 32 0x020e05b4 0x00020030 -wm 32 0x020e05bc 0x00020030 -wm 32 0x020e05b8 0x00000030 -wm 32 0x020e05c0 0x00000030 -wm 32 0x020e05c4 0x00020030 -wm 32 0x020e0748 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e0758 0x00000000 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e0784 0x00000030 -wm 32 0x020e0788 0x00000030 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0794 0x00000030 -wm 32 0x020e0798 0x000c0000 -wm 32 0x020e079c 0x00000030 -wm 32 0x020e07a0 0x00000030 -wm 32 0x020e07a4 0x00000030 -wm 32 0x020e07a8 0x00000030 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b0018 0x00081740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b000c 0x555a7974 -wm 32 0x021b0010 0xdb538f64 -wm 32 0x021b0014 0x01ff00db -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x005a1023 -wm 32 0x021b0008 0x09444040 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0040 0x00000027 -wm 32 0x021b0000 0x831a0000 -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x0408803a -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x0000803b -wm 32 0x021b001c 0x00428031 -wm 32 0x021b001c 0x00428039 -wm 32 0x021b001c 0x19308030 -wm 32 0x021b001c 0x19308038 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b001c 0x04008048 -wm 32 0x021b0800 0xa1380003 -wm 32 0x021b4800 0xa1380003 -wm 32 0x021b0020 0x00005800 -wm 32 0x021b0818 0x00022227 -wm 32 0x021b4818 0x00022227 -wm 32 0x021b083c 0x434b0350 -wm 32 0x021b0840 0x034c0359 -wm 32 0x021b483c 0x434b0350 -wm 32 0x021b4840 0x03650348 -wm 32 0x021b0848 0x4436383b -wm 32 0x021b4848 0x39393341 -wm 32 0x021b0850 0x35373933 -wm 32 0x021b4850 0x48254a36 -wm 32 0x021b080c 0x001f001f -wm 32 0x021b0810 0x001f001f -wm 32 0x021b480c 0x00440044 -wm 32 0x021b4810 0x00440044 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b001c 0x00000000 -wm 32 0x021b0404 0x00011006 +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6q-ddr-regs.h> + +wm 32 MX6_IOM_DRAM_SDQS5 0x00000030 +wm 32 MX6_IOM_DRAM_DQM5 0x00020030 +wm 32 MX6_IOM_DRAM_DQM4 0x00020030 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000030 +wm 32 MX6_IOM_DRAM_DQM3 0x00020030 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 +wm 32 MX6_IOM_DRAM_DQM2 0x00020030 +wm 32 MX6_IOM_DRAM_CAS 0x00020030 +wm 32 MX6_IOM_DRAM_RAS 0x00020030 +wm 32 MX6_IOM_DRAM_RESET 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00020030 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00020030 +wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00003030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00003030 +wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 +wm 32 MX6_IOM_DRAM_DQM0 0x00020030 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 +wm 32 MX6_IOM_DRAM_DQM1 0x00020030 +wm 32 MX6_IOM_DRAM_DQM6 0x00020030 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 +wm 32 MX6_IOM_DRAM_DQM7 0x00020030 +wm 32 MX6_IOM_GRP_B7DS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_B0DS 0x00000030 +wm 32 MX6_IOM_GRP_B1DS 0x00000030 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 +wm 32 MX6_IOM_GRP_B2DS 0x00000030 +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 +wm 32 MX6_IOM_GRP_B3DS 0x00000030 +wm 32 MX6_IOM_GRP_B4DS 0x00000030 +wm 32 MX6_IOM_GRP_B5DS 0x00000030 +wm 32 MX6_IOM_GRP_B6DS 0x00000030 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MDMISC 0x00081740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDCFG0 0x555a7974 +wm 32 MX6_MMDC_P0_MDCFG1 0xdb538f64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x005a1023 +wm 32 MX6_MMDC_P0_MDOTC 0x09444040 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MDASP 0x00000027 +wm 32 MX6_MMDC_P0_MDCTL 0x831a0000 +wm 32 MX6_MMDC_P0_MDSCR 0x04088032 +wm 32 MX6_MMDC_P0_MDSCR 0x0408803a +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x0000803b +wm 32 MX6_MMDC_P0_MDSCR 0x00428031 +wm 32 MX6_MMDC_P0_MDSCR 0x00428039 +wm 32 MX6_MMDC_P0_MDSCR 0x19308030 +wm 32 MX6_MMDC_P0_MDSCR 0x19308038 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDSCR 0x04008048 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380003 +wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1380003 +wm 32 MX6_MMDC_P0_MDREF 0x00005800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00022227 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00022227 +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x434b0350 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x034c0359 +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x434b0350 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x03650348 +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x4436383b +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x39393341 +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x35373933 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x48254a36 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001f001f +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001f001f +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x00440044 +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x00440044 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 wm 32 0x020c4068 0x00c03f3f wm 32 0x020c406c 0x0030fc03 wm 32 0x020c4070 0x0fffc000 diff --git a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg index e5bc762b48..fb34903e27 100644 --- a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg +++ b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg @@ -2,101 +2,104 @@ loadaddr 0x27800000 soc imx6 dcdofs 0x400 -wm 32 0x020e0798 0x000C0000 -wm 32 0x020e0758 0x00000000 -wm 32 0x020e0588 0x00000030 -wm 32 0x020e0594 0x00000030 -wm 32 0x020e056c 0x00000030 -wm 32 0x020e0578 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e057c 0x00000030 -wm 32 0x020e058c 0x00000000 -wm 32 0x020e059c 0x00000030 -wm 32 0x020e05a0 0x00000030 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e05a8 0x00000030 -wm 32 0x020e05b0 0x00000028 -wm 32 0x020e0524 0x00000028 -wm 32 0x020e051c 0x00000028 -wm 32 0x020e0518 0x00000028 -wm 32 0x020e050c 0x00000028 -wm 32 0x020e05b8 0x00000028 -wm 32 0x020e05c0 0x00000028 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e0784 0x00000028 -wm 32 0x020e0788 0x00000028 -wm 32 0x020e0794 0x00000028 -wm 32 0x020e079c 0x00000028 -wm 32 0x020e07a0 0x00000028 -wm 32 0x020e07a4 0x00000028 -wm 32 0x020e07a8 0x00000028 -wm 32 0x020e0748 0x00000028 -wm 32 0x020e05ac 0x00000028 -wm 32 0x020e05b4 0x00000028 -wm 32 0x020e0528 0x00000028 -wm 32 0x020e0520 0x00000028 -wm 32 0x020e0514 0x00000028 -wm 32 0x020e0510 0x00000028 -wm 32 0x020e05bc 0x00000028 -wm 32 0x020e05c4 0x00000028 - -wm 32 0x021b0800 0xA1390003 -wm 32 0x021b080c 0x001F001F -wm 32 0x021b0810 0x001F001F -wm 32 0x021b480c 0x001F001F -wm 32 0x021b4810 0x001F001F - -wm 32 0x021b083c 0x43260335 -wm 32 0x021b0840 0x031A030B -wm 32 0x021b483c 0x4323033B -wm 32 0x021b4840 0x0323026F - -wm 32 0x021b0848 0x483D4545 -wm 32 0x021b4848 0x44433E48 - -wm 32 0x021b0850 0x41444840 -wm 32 0x021b4850 0x4835483E - -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 - -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 - -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 - -wm 32 0x021b0004 0x00020036 -wm 32 0x021b0008 0x09444040 - -wm 32 0x021b000c 0x8A8F7955 -wm 32 0x021b0010 0xFF328F64 -wm 32 0x021b0014 0x01FF00DB - -wm 32 0x021b0018 0x00001740 -wm 32 0x021b001c 0x00008000 - -wm 32 0x021b002c 0x000026D2 - -wm 32 0x021b0030 0x008F1023 -wm 32 0x021b0040 0x00000047 -wm 32 0x021b0000 0x841A0000 - -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x00048031 -wm 32 0x021b001c 0x09408030 -wm 32 0x021b001c 0x04008040 - -wm 32 0x021b0020 0x00005800 -wm 32 0x021b0818 0x00011117 -wm 32 0x021b4818 0x00011117 - -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0404 0x00011006 -wm 32 0x021b001c 0x00000000 +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6q-ddr-regs.h> + +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00000030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00000030 +wm 32 MX6_IOM_DRAM_CAS 0x00000030 +wm 32 MX6_IOM_DRAM_RAS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_DRAM_RESET 0x00000030 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00000030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00000030 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000028 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_B0DS 0x00000028 +wm 32 MX6_IOM_GRP_B1DS 0x00000028 +wm 32 MX6_IOM_GRP_B2DS 0x00000028 +wm 32 MX6_IOM_GRP_B3DS 0x00000028 +wm 32 MX6_IOM_GRP_B4DS 0x00000028 +wm 32 MX6_IOM_GRP_B5DS 0x00000028 +wm 32 MX6_IOM_GRP_B6DS 0x00000028 +wm 32 MX6_IOM_GRP_B7DS 0x00000028 +wm 32 MX6_IOM_DRAM_DQM0 0x00000028 +wm 32 MX6_IOM_DRAM_DQM1 0x00000028 +wm 32 MX6_IOM_DRAM_DQM2 0x00000028 +wm 32 MX6_IOM_DRAM_DQM3 0x00000028 +wm 32 MX6_IOM_DRAM_DQM4 0x00000028 +wm 32 MX6_IOM_DRAM_DQM5 0x00000028 +wm 32 MX6_IOM_DRAM_DQM6 0x00000028 +wm 32 MX6_IOM_DRAM_DQM7 0x00000028 + +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1390003 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001F001F +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001F001F +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x001F001F +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x001F001F + +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x43260335 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x031A030B +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x4323033B +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x0323026F + +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x483D4545 +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x44433E48 + +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x41444840 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x4835483E + +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 + +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 + +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 + +wm 32 MX6_MMDC_P0_MDPDC 0x00020036 +wm 32 MX6_MMDC_P0_MDOTC 0x09444040 + +wm 32 MX6_MMDC_P0_MDCFG0 0x8A8F7955 +wm 32 MX6_MMDC_P0_MDCFG1 0xFF328F64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01FF00DB + +wm 32 MX6_MMDC_P0_MDMISC 0x00001740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 + +wm 32 MX6_MMDC_P0_MDRWD 0x000026D2 + +wm 32 MX6_MMDC_P0_MDOR 0x008F1023 +wm 32 MX6_MMDC_P0_MDASP 0x00000047 +wm 32 MX6_MMDC_P0_MDCTL 0x841A0000 + +wm 32 MX6_MMDC_P0_MDSCR 0x04088032 +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x00048031 +wm 32 MX6_MMDC_P0_MDSCR 0x09408030 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 + +wm 32 MX6_MMDC_P0_MDREF 0x00005800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00011117 + +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 diff --git a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg index 25cef4ac16..42e98d65d3 100644 --- a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg +++ b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg @@ -2,62 +2,65 @@ loadaddr 0x17800000 soc imx6 dcdofs 0x400 -wm 32 0x020e0774 0x000c0000 -wm 32 0x020e0754 0x00000000 -wm 32 0x020e04ac 0x00000030 -wm 32 0x020e04b0 0x00000030 -wm 32 0x020e0464 0x00000030 -wm 32 0x020e0490 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e0494 0x00000030 -wm 32 0x020e04a0 0x00000000 -wm 32 0x020e04b4 0x00000030 -wm 32 0x020e04b8 0x00000030 -wm 32 0x020e076c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e04bc 0x00000028 -wm 32 0x020e04c0 0x00000028 -wm 32 0x020e04c4 0x00000028 -wm 32 0x020e04c8 0x00000028 -wm 32 0x020e0760 0x00020000 -wm 32 0x020e0764 0x00000028 -wm 32 0x020e0770 0x00000028 -wm 32 0x020e0778 0x00000028 -wm 32 0x020e077c 0x00000028 -wm 32 0x020e0470 0x00000028 -wm 32 0x020e0474 0x00000028 -wm 32 0x020e0478 0x00000028 -wm 32 0x020e047c 0x00000028 -wm 32 0x021b0800 0xa1390003 -wm 32 0x021b080c 0x001f001f -wm 32 0x021b0810 0x001f001f -wm 32 0x021b083c 0x421c0216 -wm 32 0x021b0840 0x017b017a -wm 32 0x021b0848 0x4b4a4e4c -wm 32 0x021b0850 0x3f3f3334 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b0004 0x00020025 -wm 32 0x021b0008 0x00333030 -wm 32 0x021b000c 0x676b5313 -wm 32 0x021b0010 0xb66e8b63 -wm 32 0x021b0014 0x01ff00db -wm 32 0x021b0018 0x00001740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x006b1023 -wm 32 0x021b0040 0x00000027 -wm 32 0x021b0000 0x84190000 -wm 32 0x021b001c 0x04008032 -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x00048031 -wm 32 0x021b001c 0x05208030 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b0020 0x00005800 -wm 32 0x021b0818 0x00011117 -wm 32 0x021b0004 0x00025565 -wm 32 0x021b0404 0x00011006 -wm 32 0x021b001c 0x00000000 +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6dl-ddr-regs.h> + +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00000030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00000030 +wm 32 MX6_IOM_DRAM_CAS 0x00000030 +wm 32 MX6_IOM_DRAM_RAS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_DRAM_RESET 0x00000030 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00000030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00000030 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_DRAM_SDQS0 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000028 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_B0DS 0x00000028 +wm 32 MX6_IOM_GRP_B1DS 0x00000028 +wm 32 MX6_IOM_GRP_B2DS 0x00000028 +wm 32 MX6_IOM_GRP_B3DS 0x00000028 +wm 32 MX6_IOM_DRAM_DQM0 0x00000028 +wm 32 MX6_IOM_DRAM_DQM1 0x00000028 +wm 32 MX6_IOM_DRAM_DQM2 0x00000028 +wm 32 MX6_IOM_DRAM_DQM3 0x00000028 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001f001f +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001f001f +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x421c0216 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x017b017a +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x4b4a4e4c +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x3f3f3334 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDPDC 0x00020025 +wm 32 MX6_MMDC_P0_MDOTC 0x00333030 +wm 32 MX6_MMDC_P0_MDCFG0 0x676b5313 +wm 32 MX6_MMDC_P0_MDCFG1 0xb66e8b63 +wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db +wm 32 MX6_MMDC_P0_MDMISC 0x00001740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x006b1023 +wm 32 MX6_MMDC_P0_MDASP 0x00000027 +wm 32 MX6_MMDC_P0_MDCTL 0x84190000 +wm 32 MX6_MMDC_P0_MDSCR 0x04008032 +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x00048031 +wm 32 MX6_MMDC_P0_MDSCR 0x05208030 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDREF 0x00005800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P0_MDPDC 0x00025565 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 diff --git a/arch/arm/boards/efika-mx-smartbook/Makefile b/arch/arm/boards/efika-mx-smartbook/Makefile index d00e0f6ed0..73d7b9696c 100644 --- a/arch/arm/boards/efika-mx-smartbook/Makefile +++ b/arch/arm/boards/efika-mx-smartbook/Makefile @@ -1,5 +1,3 @@ -obj-y += board.o flash-header-imx51-genesi-efikasb.dcd.o +obj-y += board.o lwl-y += lowlevel.o -extra-y += flash-header-imx51-genesi-efikasb.dcd.S -extra-y += flash-header-imx51-genesi-efikasb.dcd bbenv-y += defaultenv-efikasb diff --git a/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg b/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg index a3389218d5..d54b3ea851 100644 --- a/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg +++ b/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg @@ -13,69 +13,71 @@ soc imx7 loadaddr 0x80000000 dcdofs 0x400 +#include <mach/imx7-ddr-regs.h> + wm 32 0x30340004 0x4F400005 wm 32 0x30391000 0x00000002 -wm 32 0x307a0000 0x03040008 -wm 32 0x307a0064 0x00200038 -wm 32 0x307a0490 0x00000001 -wm 32 0x307a00d0 0x00350001 -wm 32 0x307a00dc 0x00c3000a -wm 32 0x307a00e0 0x00010000 -wm 32 0x307a00e4 0x00110006 -wm 32 0x307a00f4 0x0000033f -wm 32 0x307a0100 0x0a0e110b -wm 32 0x307a0104 0x00020211 -wm 32 0x307a0108 0x03060708 -wm 32 0x307a010c 0x00a0500c -wm 32 0x307a0110 0x05020307 -wm 32 0x307a0114 0x02020404 -wm 32 0x307a0118 0x02020003 -wm 32 0x307a011c 0x00000202 -wm 32 0x307a0120 0x00000202 +wm 32 MX7_DDRC_MSTR 0x03040008 +wm 32 MX7_DDRC_RFSHTMG 0x00200038 +wm 32 MX7_DDRC_MP_PCTRL_0 0x00000001 +wm 32 MX7_DDRC_INIT0 0x00350001 +wm 32 MX7_DDRC_INIT3 0x00c3000a +wm 32 MX7_DDRC_INIT4 0x00010000 +wm 32 MX7_DDRC_INIT5 0x00110006 +wm 32 MX7_DDRC_RANKCTL 0x0000033f +wm 32 MX7_DDRC_DRAMTMG0 0x0a0e110b +wm 32 MX7_DDRC_DRAMTMG1 0x00020211 +wm 32 MX7_DDRC_DRAMTMG2 0x03060708 +wm 32 MX7_DDRC_DRAMTMG3 0x00a0500c +wm 32 MX7_DDRC_DRAMTMG4 0x05020307 +wm 32 MX7_DDRC_DRAMTMG5 0x02020404 +wm 32 MX7_DDRC_DRAMTMG6 0x02020003 +wm 32 MX7_DDRC_DRAMTMG7 0x00000202 +wm 32 MX7_DDRC_DRAMTMG8 0x00000202 -wm 32 0x307a0180 0x00600018 -wm 32 0x307a0184 0x00e00100 -wm 32 0x307a0190 0x02098205 -wm 32 0x307a0194 0x00060303 -wm 32 0x307a01a0 0x80400003 -wm 32 0x307a01a4 0x00100020 -wm 32 0x307a01a8 0x80100004 +wm 32 MX7_DDRC_ZQCTL0 0x00600018 +wm 32 MX7_DDRC_ZQCTL1 0x00e00100 +wm 32 MX7_DDRC_DFITMG0 0x02098205 +wm 32 MX7_DDRC_DFITMG1 0x00060303 +wm 32 MX7_DDRC_DFIUPD0 0x80400003 +wm 32 MX7_DDRC_DFIUPD1 0x00100020 +wm 32 MX7_DDRC_DFIUPD2 0x80100004 -wm 32 0x307a0200 0x00000015 -wm 32 0x307a0204 0x00161616 -wm 32 0x307a0210 0x00000f0f -wm 32 0x307a0214 0x04040404 -wm 32 0x307a0218 0x0f0f0404 +wm 32 MX7_DDRC_ADDRMAP0 0x00000015 +wm 32 MX7_DDRC_ADDRMAP1 0x00161616 +wm 32 MX7_DDRC_ADDRMAP4 0x00000f0f +wm 32 MX7_DDRC_ADDRMAP5 0x04040404 +wm 32 MX7_DDRC_ADDRMAP6 0x0f0f0404 -wm 32 0x307a0240 0x06000600 -wm 32 0x307a0244 0x00000000 +wm 32 MX7_DDRC_ODTCFG 0x06000600 +wm 32 MX7_DDRC_ODTMAP 0x00000000 wm 32 0x30391000 0x00000000 -wm 32 0x30790000 0x17421e40 -wm 32 0x30790004 0x10210100 -wm 32 0x30790008 0x00010000 -wm 32 0x30790010 0x0007080c -wm 32 0x307900b0 0x1010007e +wm 32 MX7_DDR_PHY_PHY_CON0 0x17421e40 +wm 32 MX7_DDR_PHY_PHY_CON1 0x10210100 +wm 32 MX7_DDR_PHY_PHY_CON2 0x00010000 +wm 32 MX7_DDR_PHY_PHY_CON4 0x0007080c +wm 32 MX7_DDR_PHY_MDLL_CON0 0x1010007e -wm 32 0x3079001C 0x01010000 -wm 32 0x3079009c 0x00000d6e +wm 32 MX7_DDR_PHY_RODT_CON0 0x01010000 +wm 32 MX7_DDR_PHY_DRVDS_CON0 0x00000d6e -wm 32 0x30790030 0x06060606 -wm 32 0x30790020 0x0a0a0a0a -wm 32 0x30790050 0x01000008 -wm 32 0x30790050 0x00000008 -wm 32 0x30790018 0x0000000f -wm 32 0x307900c0 0x0e487304 -wm 32 0x307900c0 0x0e4c7304 -wm 32 0x307900c0 0x0e4c7306 -wm 32 0x307900c0 0x0e4c7304 +wm 32 MX7_DDR_PHY_OFFSET_WR_CON0 0x06060606 +wm 32 MX7_DDR_PHY_OFFSET_RD_CON0 0x0a0a0a0a +wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x01000008 +wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x00000008 +wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e487304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e4c7304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e4c7306 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e4c7304 -check 32 while_any_bit_clear 0x307900c4 0x1 +check 32 while_any_bit_clear MX7_DDR_PHY_ZQ_CON1 0x1 -wm 32 0x307900c0 0x0e487304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e487304 wm 32 0x30384130 0x00000000 wm 32 0x30340020 0x00000178 wm 32 0x30384130 0x00000002 -check 32 while_any_bit_clear 0x307a0004 0x1 +check 32 while_any_bit_clear MX7_DDRC_STAT 0x1 diff --git a/arch/arm/boards/element14-warp7/lowlevel.c b/arch/arm/boards/element14-warp7/lowlevel.c index 38b7745f64..89a77d2f88 100644 --- a/arch/arm/boards/element14-warp7/lowlevel.c +++ b/arch/arm/boards/element14-warp7/lowlevel.c @@ -17,10 +17,16 @@ static noinline void warp7_start(void) void __iomem *ccmbase = IOMEM(MX7_CCM_BASE_ADDR); void *fdt; + /* CCM_CCGR148_CLR, uart1 */ writel(0x3, ccmbase + 0x4000 + 16 * 148 + 0x8); + /* CCM_TARGET_ROOT95 = UART1_CLK_ROOT */ writel(0x10000000, ccmbase + 0x8000 + 128 * 95); + /* CCM_CCGR148_SET, uart1 */ writel(0x3, ccmbase + 0x4000 + 16 * 148 + 0x4); + + /* MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX without daisy chaining */ writel(0x0, iomuxbase + 0x128); + /* MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX */ writel(0x0, iomuxbase + 0x12c); imx7_uart_setup(uart); @@ -45,4 +51,4 @@ ENTRY_FUNCTION(start_imx7s_element14_warp7, r0, r1, r2) barrier(); warp7_start(); -}
\ No newline at end of file +} diff --git a/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg b/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg index 90f7e0199e..f04adf86a4 100644 --- a/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg +++ b/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg @@ -2,97 +2,100 @@ soc imx6 loadaddr 0x10000000 dcdofs 0x400 -wm 32 0x020e04bc 0x00000030 -wm 32 0x020e04c0 0x00000030 -wm 32 0x020e04c4 0x00000030 -wm 32 0x020e04c8 0x00000030 -wm 32 0x020e04cc 0x00000030 -wm 32 0x020e04d0 0x00000030 -wm 32 0x020e04d4 0x00000030 -wm 32 0x020e04d8 0x00000030 -wm 32 0x020e0764 0x00000030 -wm 32 0x020e0770 0x00000030 -wm 32 0x020e0778 0x00000030 -wm 32 0x020e077c 0x00000030 -wm 32 0x020e0780 0x00000030 -wm 32 0x020e0784 0x00000030 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0748 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e076c 0x00000030 -wm 32 0x020e0470 0x00020030 -wm 32 0x020e0474 0x00020030 -wm 32 0x020e0478 0x00020030 -wm 32 0x020e047c 0x00020030 -wm 32 0x020e0480 0x00020030 -wm 32 0x020e0484 0x00020030 -wm 32 0x020e0488 0x00020030 -wm 32 0x020e048c 0x00020030 -wm 32 0x020e0464 0x00020030 -wm 32 0x020e0490 0x00020030 -wm 32 0x020e04ac 0x00020030 -wm 32 0x020e04b0 0x00020030 -wm 32 0x020e0494 0x00020030 -wm 32 0x020e04a4 0x00003000 -wm 32 0x020e04a8 0x00003000 -wm 32 0x020e04b4 0x00003030 -wm 32 0x020e04b8 0x00003030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e0760 0x00020000 -wm 32 0x020e0754 0x00000000 -wm 32 0x020e04a0 0x00000000 -wm 32 0x020e0774 0x000c0000 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b0018 0x00081740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b0004 0x0002002d -wm 32 0x021b000c 0x8c435323 -wm 32 0x021b0010 0xb66e8d63 -wm 32 0x021b0014 0x01ff00db -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x00431023 -wm 32 0x021b0008 0x00333030 -wm 32 0x021b0004 0x0002556d -wm 32 0x021b0040 0x00000027 -wm 32 0x021b0000 0xc4190000 -wm 32 0x021b001c 0x04008032 -wm 32 0x021b001c 0x0400803a -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x0000803b -wm 32 0x021b001c 0x00048031 -wm 32 0x021b001c 0x00048039 -wm 32 0x021b001c 0x13208030 -wm 32 0x021b001c 0x13208038 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b001c 0x04008048 -wm 32 0x021b0800 0xa1390003 -wm 32 0x021b4800 0xa1390003 -wm 32 0x021b0020 0x00005800 -wm 32 0x021b0818 0x00022227 -wm 32 0x021b4818 0x00022227 -wm 32 0x021b083c 0x42350231 -wm 32 0x021b483c 0x42350231 -wm 32 0x021b0840 0x021a0218 -wm 32 0x021b4840 0x021a0218 -wm 32 0x021b0848 0x4b4b4e49 -wm 32 0x021b4848 0x4b4b4e49 -wm 32 0x021b0850 0x3f3f3035 -wm 32 0x021b4850 0x3f3f3035 -wm 32 0x021b080c 0x0040003c -wm 32 0x021b0810 0x0032003e -wm 32 0x021b480c 0x0040003c -wm 32 0x021b4810 0x0032003e -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b001c 0x00000000 -wm 32 0x021b0404 0x00011006 +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6dl-ddr-regs.h> + +wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 +wm 32 MX6_IOM_GRP_B0DS 0x00000030 +wm 32 MX6_IOM_GRP_B1DS 0x00000030 +wm 32 MX6_IOM_GRP_B2DS 0x00000030 +wm 32 MX6_IOM_GRP_B3DS 0x00000030 +wm 32 MX6_IOM_GRP_B4DS 0x00000030 +wm 32 MX6_IOM_GRP_B5DS 0x00000030 +wm 32 MX6_IOM_GRP_B6DS 0x00000030 +wm 32 MX6_IOM_GRP_B7DS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 +wm 32 MX6_IOM_DRAM_DQM0 0x00020030 +wm 32 MX6_IOM_DRAM_DQM1 0x00020030 +wm 32 MX6_IOM_DRAM_DQM2 0x00020030 +wm 32 MX6_IOM_DRAM_DQM3 0x00020030 +wm 32 MX6_IOM_DRAM_DQM4 0x00020030 +wm 32 MX6_IOM_DRAM_DQM5 0x00020030 +wm 32 MX6_IOM_DRAM_DQM6 0x00020030 +wm 32 MX6_IOM_DRAM_DQM7 0x00020030 +wm 32 MX6_IOM_DRAM_CAS 0x00020030 +wm 32 MX6_IOM_DRAM_RAS 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00020030 +wm 32 MX6_IOM_DRAM_RESET 0x00020030 +wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000 +wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00003030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00003030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MDMISC 0x00081740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDPDC 0x0002002d +wm 32 MX6_MMDC_P0_MDCFG0 0x8c435323 +wm 32 MX6_MMDC_P0_MDCFG1 0xb66e8d63 +wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x00431023 +wm 32 MX6_MMDC_P0_MDOTC 0x00333030 +wm 32 MX6_MMDC_P0_MDPDC 0x0002556d +wm 32 MX6_MMDC_P0_MDASP 0x00000027 +wm 32 MX6_MMDC_P0_MDCTL 0xc4190000 +wm 32 MX6_MMDC_P0_MDSCR 0x04008032 +wm 32 MX6_MMDC_P0_MDSCR 0x0400803a +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x0000803b +wm 32 MX6_MMDC_P0_MDSCR 0x00048031 +wm 32 MX6_MMDC_P0_MDSCR 0x00048039 +wm 32 MX6_MMDC_P0_MDSCR 0x13208030 +wm 32 MX6_MMDC_P0_MDSCR 0x13208038 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDSCR 0x04008048 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 +wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1390003 +wm 32 MX6_MMDC_P0_MDREF 0x00005800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00022227 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00022227 +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x42350231 +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x42350231 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x021a0218 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x021a0218 +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x4b4b4e49 +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x4b4b4e49 +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x3f3f3035 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x3f3f3035 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x0040003c +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x0032003e +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x0040003c +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x0032003e +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 wm 32 0x020c4068 0x00c03f3f wm 32 0x020c406c 0x0030fc03 wm 32 0x020c4070 0x0fffc000 diff --git a/arch/arm/boards/embedsky-e9/Makefile b/arch/arm/boards/embedsky-e9/Makefile index db2dba7769..86afde47fb 100644 --- a/arch/arm/boards/embedsky-e9/Makefile +++ b/arch/arm/boards/embedsky-e9/Makefile @@ -1,4 +1,3 @@ -obj-y += board.o flash-header-e9.dcd.o -extra-y += flash-header-e9.dcd.S flash-header-e9.dcd +obj-y += board.o lwl-y += lowlevel.o bbenv-y += defaultenv-e9 diff --git a/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg b/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg index 52edefd77a..1139312da6 100644 --- a/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg +++ b/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg @@ -2,86 +2,89 @@ loadaddr 0x27800000 soc imx6 dcdofs 0x400 -wm 32 0x020e0798 0x000c0000 -wm 32 0x020e0758 0x00000000 -wm 32 0x020e0588 0x00000030 -wm 32 0x020e0594 0x00000030 -wm 32 0x020e056c 0x00000030 -wm 32 0x020e0578 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e057c 0x00000030 -wm 32 0x020e058c 0x00000000 -wm 32 0x020e059c 0x00000030 -wm 32 0x020e05a0 0x00000030 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e05a8 0x00000018 -wm 32 0x020e05b0 0x00000018 -wm 32 0x020e0524 0x00000018 -wm 32 0x020e051c 0x00000018 -wm 32 0x020e0518 0x00000018 -wm 32 0x020e050c 0x00000018 -wm 32 0x020e05b8 0x00000018 -wm 32 0x020e05c0 0x00000018 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e0784 0x00000018 -wm 32 0x020e0788 0x00000018 -wm 32 0x020e0794 0x00000018 -wm 32 0x020e079c 0x00000018 -wm 32 0x020e07a0 0x00000018 -wm 32 0x020e07a4 0x00000018 -wm 32 0x020e07a8 0x00000018 -wm 32 0x020e0748 0x00000018 -wm 32 0x020e05ac 0x00000018 -wm 32 0x020e05b4 0x00000018 -wm 32 0x020e0528 0x00000018 -wm 32 0x020e0520 0x00000018 -wm 32 0x020e0514 0x00000018 -wm 32 0x020e0510 0x00000018 -wm 32 0x020e05bc 0x00000018 -wm 32 0x020e05c4 0x00000018 -wm 32 0x021b0800 0xa1390003 -wm 32 0x021b080c 0x001f001f -wm 32 0x021b0810 0x001f001f -wm 32 0x021b480c 0x001f001f -wm 32 0x021b4810 0x001f001f -wm 32 0x021b083c 0x4333033f -wm 32 0x021b0840 0x032c031d -wm 32 0x021b483c 0x43200332 -wm 32 0x021b4840 0x031a026a -wm 32 0x021b0848 0x4d464746 -wm 32 0x021b4848 0x47453f4d -wm 32 0x021b0850 0x3e434440 -wm 32 0x021b4850 0x47384839 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b0004 0x00020036 -wm 32 0x021b0008 0x09444040 -wm 32 0x021b000c 0x8a8f7955 -wm 32 0x021b0010 0xff328f64 -wm 32 0x021b0014 0x01ff00db -wm 32 0x021b0018 0x00001740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x008f1023 -wm 32 0x021b0040 0x00000047 -wm 32 0x021b0000 0x841a0000 -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x00048031 -wm 32 0x021b001c 0x09408030 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b0020 0x00005800 -wm 32 0x021b0818 0x00011117 -wm 32 0x021b4818 0x00011117 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0404 0x00011006 -wm 32 0x021b001c 0x00000000 +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6q-ddr-regs.h> + +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00000030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00000030 +wm 32 MX6_IOM_DRAM_CAS 0x00000030 +wm 32 MX6_IOM_DRAM_RAS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_DRAM_RESET 0x00000030 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00000030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00000030 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_DRAM_SDQS0 0x00000018 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000018 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000018 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000018 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000018 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000018 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000018 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000018 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_B0DS 0x00000018 +wm 32 MX6_IOM_GRP_B1DS 0x00000018 +wm 32 MX6_IOM_GRP_B2DS 0x00000018 +wm 32 MX6_IOM_GRP_B3DS 0x00000018 +wm 32 MX6_IOM_GRP_B4DS 0x00000018 +wm 32 MX6_IOM_GRP_B5DS 0x00000018 +wm 32 MX6_IOM_GRP_B6DS 0x00000018 +wm 32 MX6_IOM_GRP_B7DS 0x00000018 +wm 32 MX6_IOM_DRAM_DQM0 0x00000018 +wm 32 MX6_IOM_DRAM_DQM1 0x00000018 +wm 32 MX6_IOM_DRAM_DQM2 0x00000018 +wm 32 MX6_IOM_DRAM_DQM3 0x00000018 +wm 32 MX6_IOM_DRAM_DQM4 0x00000018 +wm 32 MX6_IOM_DRAM_DQM5 0x00000018 +wm 32 MX6_IOM_DRAM_DQM6 0x00000018 +wm 32 MX6_IOM_DRAM_DQM7 0x00000018 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001f001f +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001f001f +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x001f001f +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x001f001f +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x4333033f +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x032c031d +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x43200332 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x031a026a +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x4d464746 +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x47453f4d +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x3e434440 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x47384839 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDPDC 0x00020036 +wm 32 MX6_MMDC_P0_MDOTC 0x09444040 +wm 32 MX6_MMDC_P0_MDCFG0 0x8a8f7955 +wm 32 MX6_MMDC_P0_MDCFG1 0xff328f64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db +wm 32 MX6_MMDC_P0_MDMISC 0x00001740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x008f1023 +wm 32 MX6_MMDC_P0_MDASP 0x00000047 +wm 32 MX6_MMDC_P0_MDCTL 0x841a0000 +wm 32 MX6_MMDC_P0_MDSCR 0x04088032 +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x00048031 +wm 32 MX6_MMDC_P0_MDSCR 0x09408030 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDREF 0x00005800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 diff --git a/arch/arm/boards/embest-riotboard/Makefile b/arch/arm/boards/embest-riotboard/Makefile index 9f8e1f2b21..01c7a259e9 100644 --- a/arch/arm/boards/embest-riotboard/Makefile +++ b/arch/arm/boards/embest-riotboard/Makefile @@ -1,3 +1,2 @@ -obj-y += board.o flash-header-embest-riotboard.dcd.o -extra-y += flash-header-embest-riotboard.dcd.S flash-header-embest-riotboard.dcd +obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg b/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg index 04e162b8f1..c9a8098f6d 100644 --- a/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg +++ b/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg @@ -1,62 +1,66 @@ loadaddr 0x20000000 soc imx6 dcdofs 0x400 -wm 32 0x020e0774 0x000c0000 -wm 32 0x020e0754 0x00000000 -wm 32 0x020e04ac 0x00000030 -wm 32 0x020e04b0 0x00000030 -wm 32 0x020e0464 0x00000030 -wm 32 0x020e0490 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e0494 0x00000030 -wm 32 0x020e04a0 0x00000000 -wm 32 0x020e04b4 0x00000030 -wm 32 0x020e04b8 0x00000030 -wm 32 0x020e076c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e04bc 0x00000028 -wm 32 0x020e04c0 0x00000028 -wm 32 0x020e04c4 0x00000028 -wm 32 0x020e04c8 0x00000028 -wm 32 0x020e0760 0x00020000 -wm 32 0x020e0764 0x00000028 -wm 32 0x020e0770 0x00000028 -wm 32 0x020e0778 0x00000028 -wm 32 0x020e077c 0x00000028 -wm 32 0x020e0470 0x00000028 -wm 32 0x020e0474 0x00000028 -wm 32 0x020e0478 0x00000028 -wm 32 0x020e047c 0x00000028 -wm 32 0x021b0800 0xa1390003 -wm 32 0x021b080c 0x001f001f -wm 32 0x021b0810 0x001f001f -wm 32 0x021b083c 0x421c0216 -wm 32 0x021b0840 0x017b017a -wm 32 0x021b0848 0x4b4a4e4c -wm 32 0x021b0850 0x3f3f3334 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b0004 0x00020025 -wm 32 0x021b0008 0x00333030 -wm 32 0x021b000c 0x676b5313 -wm 32 0x021b0010 0xb66e8b63 -wm 32 0x021b0014 0x01ff00db -wm 32 0x021b0018 0x00001740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x006b1023 -wm 32 0x021b0040 0x00000027 -wm 32 0x021b0000 0x84190000 -wm 32 0x021b001c 0x04008032 -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x00048031 -wm 32 0x021b001c 0x05208030 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b0020 0x00005800 -wm 32 0x021b0818 0x00011117 -wm 32 0x021b0004 0x00025565 -wm 32 0x021b0404 0x00011006 -wm 32 0x021b001c 0x00000000 + +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6dl-ddr-regs.h> + +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00000030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00000030 +wm 32 MX6_IOM_DRAM_CAS 0x00000030 +wm 32 MX6_IOM_DRAM_RAS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_DRAM_RESET 0x00000030 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00000030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00000030 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_DRAM_SDQS0 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000028 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_B0DS 0x00000028 +wm 32 MX6_IOM_GRP_B1DS 0x00000028 +wm 32 MX6_IOM_GRP_B2DS 0x00000028 +wm 32 MX6_IOM_GRP_B3DS 0x00000028 +wm 32 MX6_IOM_DRAM_DQM0 0x00000028 +wm 32 MX6_IOM_DRAM_DQM1 0x00000028 +wm 32 MX6_IOM_DRAM_DQM2 0x00000028 +wm 32 MX6_IOM_DRAM_DQM3 0x00000028 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001f001f +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001f001f +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x421c0216 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x017b017a +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x4b4a4e4c +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x3f3f3334 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDPDC 0x00020025 +wm 32 MX6_MMDC_P0_MDOTC 0x00333030 +wm 32 MX6_MMDC_P0_MDCFG0 0x676b5313 +wm 32 MX6_MMDC_P0_MDCFG1 0xb66e8b63 +wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db +wm 32 MX6_MMDC_P0_MDMISC 0x00001740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x006b1023 +wm 32 MX6_MMDC_P0_MDASP 0x00000027 +wm 32 MX6_MMDC_P0_MDCTL 0x84190000 +wm 32 MX6_MMDC_P0_MDSCR 0x04008032 +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x00048031 +wm 32 MX6_MMDC_P0_MDSCR 0x05208030 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDREF 0x00005800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P0_MDPDC 0x00025565 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 diff --git a/arch/arm/boards/freescale-mx51-babbage/Makefile b/arch/arm/boards/freescale-mx51-babbage/Makefile index 31b8fcd8a2..01c7a259e9 100644 --- a/arch/arm/boards/freescale-mx51-babbage/Makefile +++ b/arch/arm/boards/freescale-mx51-babbage/Makefile @@ -1,6 +1,2 @@ -obj-y += board.o flash-header-imx51-babbage.dcd.o -extra-y += flash-header-imx51-babbage.dcd.S flash-header-imx51-babbage.dcd +obj-y += board.o lwl-y += lowlevel.o - -obj-$(CONFIG_ARCH_IMX_XLOAD) += flash-header-imx51-babbage-xload.dcd.o -extra-$(CONFIG_ARCH_IMX_XLOAD) += flash-header-imx51-babbage-xload.dcd.S flash-header-imx51-babbage-xload.dcd diff --git a/arch/arm/boards/freescale-mx53-qsb/Makefile b/arch/arm/boards/freescale-mx53-qsb/Makefile index bcaa974f35..01c7a259e9 100644 --- a/arch/arm/boards/freescale-mx53-qsb/Makefile +++ b/arch/arm/boards/freescale-mx53-qsb/Makefile @@ -1,3 +1,2 @@ -obj-y += board.o flash-header-imx53-loco.dcd.o -extra-y += flash-header-imx53-loco.dcd.S flash-header-imx53-loco.dcd +obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/freescale-mx53-vmx53/Makefile b/arch/arm/boards/freescale-mx53-vmx53/Makefile index 33d5e59d35..01c7a259e9 100644 --- a/arch/arm/boards/freescale-mx53-vmx53/Makefile +++ b/arch/arm/boards/freescale-mx53-vmx53/Makefile @@ -1,3 +1,2 @@ -obj-y += board.o flash-header-imx53-vmx53.dcd.o -extra-y += flash-header-imx53-vmx53.dcd.S flash-header-imx53-vmx53.dcd +obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/freescale-mx6-sabrelite/Makefile b/arch/arm/boards/freescale-mx6-sabrelite/Makefile index 6ae9e75e2d..01c7a259e9 100644 --- a/arch/arm/boards/freescale-mx6-sabrelite/Makefile +++ b/arch/arm/boards/freescale-mx6-sabrelite/Makefile @@ -1,3 +1,2 @@ -obj-y += board.o flash-header-mx6-sabrelite.dcd.o -extra-y += flash-header-mx6-sabrelite.dcd.S flash-header-mx6-sabrelite.dcd +obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg b/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg index 60a39fe870..3ce8562f51 100644 --- a/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg +++ b/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg @@ -2,96 +2,99 @@ soc imx6 loadaddr 0x20000000 dcdofs 0x400 -wm 32 0x020e05a8 0x00000030 -wm 32 0x020e05b0 0x00000030 -wm 32 0x020e0524 0x00000030 -wm 32 0x020e051c 0x00000030 -wm 32 0x020e0518 0x00000030 -wm 32 0x020e050c 0x00000030 -wm 32 0x020e05b8 0x00000030 -wm 32 0x020e05c0 0x00000030 -wm 32 0x020e05ac 0x00020030 -wm 32 0x020e05b4 0x00020030 -wm 32 0x020e0528 0x00020030 -wm 32 0x020e0520 0x00020030 -wm 32 0x020e0514 0x00020030 -wm 32 0x020e0510 0x00020030 -wm 32 0x020e05bc 0x00020030 -wm 32 0x020e05c4 0x00020030 -wm 32 0x020e056c 0x00020030 -wm 32 0x020e0578 0x00020030 -wm 32 0x020e0588 0x00020030 -wm 32 0x020e0594 0x00020030 -wm 32 0x020e057c 0x00020030 -wm 32 0x020e0590 0x00003000 -wm 32 0x020e0598 0x00003000 -wm 32 0x020e058c 0x00000000 -wm 32 0x020e059c 0x00003030 -wm 32 0x020e05a0 0x00003030 -wm 32 0x020e0784 0x00000030 -wm 32 0x020e0788 0x00000030 -wm 32 0x020e0794 0x00000030 -wm 32 0x020e079c 0x00000030 -wm 32 0x020e07a0 0x00000030 -wm 32 0x020e07a4 0x00000030 -wm 32 0x020e07a8 0x00000030 -wm 32 0x020e0748 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e0758 0x00000000 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0798 0x000c0000 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b0018 0x00081740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b000c 0x555a7975 -wm 32 0x021b0010 0xff538e64 -wm 32 0x021b0014 0x01ff00db -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x005b0e21 -wm 32 0x021b0008 0x09444040 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0040 0x00000027 -wm 32 0x021b0000 0x831a0000 -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x0408803a -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x0000803b -wm 32 0x021b001c 0x00428031 -wm 32 0x021b001c 0x00428039 -wm 32 0x021b001c 0x09408030 -wm 32 0x021b001c 0x09408038 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b001c 0x04008048 -wm 32 0x021b0800 0xa1380003 -wm 32 0x021b4800 0xa1380003 -wm 32 0x021b0020 0x00005800 -wm 32 0x021b0818 0x00022227 -wm 32 0x021b4818 0x00022227 -wm 32 0x021b083c 0x434b0350 -wm 32 0x021b0840 0x034c0359 -wm 32 0x021b483c 0x434b0350 -wm 32 0x021b4840 0x03650348 -wm 32 0x021b0848 0x4436383b -wm 32 0x021b4848 0x39393341 -wm 32 0x021b0850 0x35373933 -wm 32 0x021b4850 0x48254A36 -wm 32 0x021b080c 0x001f001f -wm 32 0x021b0810 0x001f001f -wm 32 0x021b480c 0x00440044 -wm 32 0x021b4810 0x00440044 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b001c 0x00000000 -wm 32 0x021b0404 0x00011006 +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6q-ddr-regs.h> + +wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 +wm 32 MX6_IOM_DRAM_DQM0 0x00020030 +wm 32 MX6_IOM_DRAM_DQM1 0x00020030 +wm 32 MX6_IOM_DRAM_DQM2 0x00020030 +wm 32 MX6_IOM_DRAM_DQM3 0x00020030 +wm 32 MX6_IOM_DRAM_DQM4 0x00020030 +wm 32 MX6_IOM_DRAM_DQM5 0x00020030 +wm 32 MX6_IOM_DRAM_DQM6 0x00020030 +wm 32 MX6_IOM_DRAM_DQM7 0x00020030 +wm 32 MX6_IOM_DRAM_CAS 0x00020030 +wm 32 MX6_IOM_DRAM_RAS 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00020030 +wm 32 MX6_IOM_DRAM_RESET 0x00020030 +wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000 +wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00003030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00003030 +wm 32 MX6_IOM_GRP_B0DS 0x00000030 +wm 32 MX6_IOM_GRP_B1DS 0x00000030 +wm 32 MX6_IOM_GRP_B2DS 0x00000030 +wm 32 MX6_IOM_GRP_B3DS 0x00000030 +wm 32 MX6_IOM_GRP_B4DS 0x00000030 +wm 32 MX6_IOM_GRP_B5DS 0x00000030 +wm 32 MX6_IOM_GRP_B6DS 0x00000030 +wm 32 MX6_IOM_GRP_B7DS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MDMISC 0x00081740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDCFG0 0x555a7975 +wm 32 MX6_MMDC_P0_MDCFG1 0xff538e64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x005b0e21 +wm 32 MX6_MMDC_P0_MDOTC 0x09444040 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MDASP 0x00000027 +wm 32 MX6_MMDC_P0_MDCTL 0x831a0000 +wm 32 MX6_MMDC_P0_MDSCR 0x04088032 +wm 32 MX6_MMDC_P0_MDSCR 0x0408803a +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x0000803b +wm 32 MX6_MMDC_P0_MDSCR 0x00428031 +wm 32 MX6_MMDC_P0_MDSCR 0x00428039 +wm 32 MX6_MMDC_P0_MDSCR 0x09408030 +wm 32 MX6_MMDC_P0_MDSCR 0x09408038 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDSCR 0x04008048 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380003 +wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1380003 +wm 32 MX6_MMDC_P0_MDREF 0x00005800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00022227 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00022227 +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x434b0350 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x034c0359 +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x434b0350 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x03650348 +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x4436383b +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x39393341 +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x35373933 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x48254A36 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001f001f +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001f001f +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x00440044 +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x00440044 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 wm 32 0x020c4068 0x00c03f3f wm 32 0x020c406c 0x0030fc03 wm 32 0x020c4070 0x0fffc000 diff --git a/arch/arm/boards/freescale-mx6-sabresd/Makefile b/arch/arm/boards/freescale-mx6-sabresd/Makefile index f72c641e17..01c7a259e9 100644 --- a/arch/arm/boards/freescale-mx6-sabresd/Makefile +++ b/arch/arm/boards/freescale-mx6-sabresd/Makefile @@ -1,3 +1,2 @@ -obj-y += board.o flash-header-mx6-sabresd.dcd.o -extra-y += flash-header-mx6-sabresd.dcd.S flash-header-mx6-sabresd.dcd +obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/freescale-mx7-sabresd/Makefile b/arch/arm/boards/freescale-mx7-sabresd/Makefile new file mode 100644 index 0000000000..01c7a259e9 --- /dev/null +++ b/arch/arm/boards/freescale-mx7-sabresd/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/freescale-mx7-sabresd/board.c b/arch/arm/boards/freescale-mx7-sabresd/board.c new file mode 100644 index 0000000000..37941efdbe --- /dev/null +++ b/arch/arm/boards/freescale-mx7-sabresd/board.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2017 Zodiac Inflight Innovation + * Author: Andrey Smirnov <andrew.smirnov@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <init.h> +#include <io.h> +#include <mach/imx7-regs.h> +#include <linux/phy.h> +#include <mfd/imx7-iomuxc-gpr.h> + +#include <phy-id-list.h> + +static int bcm54220_phy_fixup(struct phy_device *dev) +{ + phy_write(dev, 0x1e, 0x21); + phy_write(dev, 0x1f, 0x7ea8); + phy_write(dev, 0x1e, 0x2f); + phy_write(dev, 0x1f, 0x71b7); + + return 0; +} + +static void mx7_sabresd_init_fec1(void) +{ + void __iomem *gpr = IOMEM(MX7_IOMUXC_GPR_BASE_ADDR); + uint32_t gpr1; + + gpr1 = readl(gpr + IOMUXC_GPR1); + gpr1 &= ~(IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK | + IMX7D_GPR1_ENET1_CLK_DIR_MASK); + writel(gpr1, gpr + IOMUXC_GPR1); +} + +static int mx7_sabresd_coredevices_init(void) +{ + if (!of_machine_is_compatible("fsl,imx7d-sdb")) + return 0; + + mx7_sabresd_init_fec1(); + + phy_register_fixup_for_uid(PHY_ID_BCM54220, 0xffffffff, + bcm54220_phy_fixup); + + return 0; +} +coredevice_initcall(mx7_sabresd_coredevices_init); diff --git a/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg b/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg new file mode 100644 index 0000000000..fd4861153f --- /dev/null +++ b/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2016 NXP Semiconductors + * + * SPDX-License-Identifier: GPL-2.0 + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + * + * Taken from upstream U-Boot git://git.denx.de/u-boot.git, commit + * 1a8150d4b16fbafa6f1d207ddb85eda7dc399e2d + */ + +soc imx7 +loadaddr 0x80000000 +dcdofs 0x400 + +#include <mach/imx7-ddr-regs.h> + +wm 32 0x30340004 0x4F400005 + +wm 32 0x30391000 0x00000002 + +wm 32 MX7_DDRC_MSTR 0x01040001 +wm 32 MX7_DDRC_DFIUPD0 0x80400003 +wm 32 MX7_DDRC_DFIUPD1 0x00100020 +wm 32 MX7_DDRC_DFIUPD2 0x80100004 +wm 32 MX7_DDRC_RFSHTMG 0x00400046 +wm 32 MX7_DDRC_MP_PCTRL_0 0x00000001 +wm 32 MX7_DDRC_INIT0 0x00020083 +wm 32 MX7_DDRC_INIT1 0x00690000 +wm 32 MX7_DDRC_INIT3 0x09300004 +wm 32 MX7_DDRC_INIT4 0x04080000 +wm 32 MX7_DDRC_INIT5 0x00100004 +wm 32 MX7_DDRC_RANKCTL 0x0000033f +wm 32 MX7_DDRC_DRAMTMG0 0x09081109 +wm 32 MX7_DDRC_DRAMTMG1 0x0007020d +wm 32 MX7_DDRC_DRAMTMG2 0x03040407 +wm 32 MX7_DDRC_DRAMTMG3 0x00002006 +wm 32 MX7_DDRC_DRAMTMG4 0x04020205 +wm 32 MX7_DDRC_DRAMTMG5 0x03030202 +wm 32 MX7_DDRC_DRAMTMG8 0x00000803 +wm 32 MX7_DDRC_ZQCTL0 0x00800020 +wm 32 MX7_DDRC_ZQCTL1 0x02000100 +wm 32 MX7_DDRC_DFITMG0 0x02098204 +wm 32 MX7_DDRC_DFITMG1 0x00030303 +wm 32 MX7_DDRC_ADDRMAP0 0x00000016 +wm 32 MX7_DDRC_ADDRMAP1 0x00171717 +wm 32 MX7_DDRC_ADDRMAP5 0x04040404 +wm 32 MX7_DDRC_ADDRMAP6 0x0f040404 +wm 32 MX7_DDRC_ODTCFG 0x06000604 +wm 32 MX7_DDRC_ODTMAP 0x00000001 + +wm 32 0x30391000 0x00000000 + +wm 32 MX7_DDR_PHY_PHY_CON0 0x17420f40 +wm 32 MX7_DDR_PHY_PHY_CON1 0x10210100 +wm 32 MX7_DDR_PHY_PHY_CON4 0x00060807 +wm 32 MX7_DDR_PHY_MDLL_CON0 0x1010007e +wm 32 MX7_DDR_PHY_DRVDS_CON0 0x00000d6e +wm 32 MX7_DDR_PHY_OFFSET_RD_CON0 0x08080808 +wm 32 MX7_DDR_PHY_OFFSET_WR_CON0 0x08080808 +wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x01000010 +wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x00000010 + +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447306 + +check 32 while_any_bit_clear MX7_DDR_PHY_ZQ_CON1 0x1 + +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 + +wm 32 0x30384130 0x00000000 +wm 32 0x30340020 0x00000178 +wm 32 0x30384130 0x00000002 + +wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f + +check 32 while_any_bit_clear MX7_DDRC_STAT 0x1 diff --git a/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c new file mode 100644 index 0000000000..96ccbbfeb8 --- /dev/null +++ b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c @@ -0,0 +1,46 @@ +#include <debug_ll.h> +#include <io.h> +#include <common.h> +#include <linux/sizes.h> +#include <mach/generic.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/imx7-ccm-regs.h> +#include <mach/iomux-mx7.h> +#include <mach/debug_ll.h> +#include <asm/cache.h> + +extern char __dtb_imx7d_sdb_start[]; + +static inline void setup_uart(void) +{ + void __iomem *iomux = IOMEM(MX7_IOMUXC_BASE_ADDR); + void __iomem *ccm = IOMEM(MX7_CCM_BASE_ADDR); + + writel(CCM_CCGR_SETTINGn_NEEDED(0), + ccm + CCM_CCGRn_CLR(CCM_CCGR_UART1)); + writel(CCM_TARGET_ROOTn_ENABLE | UART1_CLK_ROOT__OSC_24M, + ccm + CCM_TARGET_ROOTn(UART1_CLK_ROOT)); + writel(CCM_CCGR_SETTINGn_NEEDED(0), + ccm + CCM_CCGRn_SET(CCM_CCGR_UART1)); + + mx7_setup_pad(iomux, MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX); + + imx7_uart_setup_ll(); + + putc_ll('>'); +} + +ENTRY_FUNCTION(start_imx7d_sabresd, r0, r1, r2) +{ + void *fdt; + + imx7_cpu_lowlevel_init(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + fdt = __dtb_imx7d_sdb_start - get_runtime_offset(); + + barebox_arm_entry(0x80000000, SZ_1G, fdt); +} diff --git a/arch/arm/boards/freescale-vf610-twr/Makefile b/arch/arm/boards/freescale-vf610-twr/Makefile index 6b029ce2fe..b08c4a93ca 100644 --- a/arch/arm/boards/freescale-vf610-twr/Makefile +++ b/arch/arm/boards/freescale-vf610-twr/Makefile @@ -1,3 +1 @@ -obj-y += flash-header-vf610-twr.dcd.o -extra-y += flash-header-vf610-twr.dcd.S flash-header-vf610-twr.dcd lwl-y += lowlevel.o diff --git a/arch/arm/boards/gk802/Makefile b/arch/arm/boards/gk802/Makefile index d9c7ab60ed..01c7a259e9 100644 --- a/arch/arm/boards/gk802/Makefile +++ b/arch/arm/boards/gk802/Makefile @@ -1,3 +1,2 @@ -obj-y += board.o flash-header.dcd.o -extra-y += flash-header.dcd.S flash-header.dcd +obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/gk802/flash-header.imxcfg b/arch/arm/boards/gk802/flash-header.imxcfg index 9638b02bda..f26fe77b03 100644 --- a/arch/arm/boards/gk802/flash-header.imxcfg +++ b/arch/arm/boards/gk802/flash-header.imxcfg @@ -1,96 +1,100 @@ loadaddr 0x10000000 soc imx6 dcdofs 0x400 -wm 32 0x020e05a8 0x00000030 -wm 32 0x020e05b0 0x00000030 -wm 32 0x020e0524 0x00000030 -wm 32 0x020e051c 0x00000030 -wm 32 0x020e0518 0x00000030 -wm 32 0x020e050c 0x00000030 -wm 32 0x020e05b8 0x00000030 -wm 32 0x020e05c0 0x00000030 -wm 32 0x020e05ac 0x00020030 -wm 32 0x020e05b4 0x00020030 -wm 32 0x020e0528 0x00020030 -wm 32 0x020e0520 0x00020030 -wm 32 0x020e0514 0x00020030 -wm 32 0x020e0510 0x00020030 -wm 32 0x020e05bc 0x00020030 -wm 32 0x020e05c4 0x00020030 -wm 32 0x020e056c 0x00020030 -wm 32 0x020e0578 0x00020030 -wm 32 0x020e0588 0x00020030 -wm 32 0x020e0594 0x00020030 -wm 32 0x020e057c 0x00020030 -wm 32 0x020e0590 0x00003000 -wm 32 0x020e0598 0x00003000 -wm 32 0x020e058c 0x00000000 -wm 32 0x020e059c 0x00003030 -wm 32 0x020e05a0 0x00003030 -wm 32 0x020e0784 0x00000030 -wm 32 0x020e0788 0x00000030 -wm 32 0x020e0794 0x00000030 -wm 32 0x020e079c 0x00000030 -wm 32 0x020e07a0 0x00000030 -wm 32 0x020e07a4 0x00000030 -wm 32 0x020e07a8 0x00000030 -wm 32 0x020e0748 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e0758 0x00000000 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0798 0x000c0000 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b0018 0x00081740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b000c 0x555a7975 -wm 32 0x021b0010 0xff538e64 -wm 32 0x021b0014 0x01ff00db -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x005b0e21 -wm 32 0x021b0008 0x09444040 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0040 0x00000027 -wm 32 0x021b0000 0x831a0000 -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x0408803a -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x0000803b -wm 32 0x021b001c 0x00428031 -wm 32 0x021b001c 0x00428039 -wm 32 0x021b001c 0x09408030 -wm 32 0x021b001c 0x09408038 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b001c 0x04008048 -wm 32 0x021b0800 0xa1380003 -wm 32 0x021b4800 0xa1380003 -wm 32 0x021b0020 0x00005800 -wm 32 0x021b0818 0x00000007 -wm 32 0x021b4818 0x00000007 -wm 32 0x021b083c 0x427b030a -wm 32 0x021b0840 0x02740269 -wm 32 0x021b483c 0x43100313 -wm 32 0x021b4840 0x027d024d -wm 32 0x021b0848 0x46384240 -wm 32 0x021b4848 0x4442414a -wm 32 0x021b0850 0x45444645 -wm 32 0x021b4850 0x4a354946 -wm 32 0x021b080c 0x001f001f -wm 32 0x021b0810 0x001f001f -wm 32 0x021b480c 0x00440044 -wm 32 0x021b4810 0x00440044 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b001c 0x00000000 -wm 32 0x021b0404 0x00011006 + +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6q-ddr-regs.h> + +wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 +wm 32 MX6_IOM_DRAM_DQM0 0x00020030 +wm 32 MX6_IOM_DRAM_DQM1 0x00020030 +wm 32 MX6_IOM_DRAM_DQM2 0x00020030 +wm 32 MX6_IOM_DRAM_DQM3 0x00020030 +wm 32 MX6_IOM_DRAM_DQM4 0x00020030 +wm 32 MX6_IOM_DRAM_DQM5 0x00020030 +wm 32 MX6_IOM_DRAM_DQM6 0x00020030 +wm 32 MX6_IOM_DRAM_DQM7 0x00020030 +wm 32 MX6_IOM_DRAM_CAS 0x00020030 +wm 32 MX6_IOM_DRAM_RAS 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00020030 +wm 32 MX6_IOM_DRAM_RESET 0x00020030 +wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000 +wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00003030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00003030 +wm 32 MX6_IOM_GRP_B0DS 0x00000030 +wm 32 MX6_IOM_GRP_B1DS 0x00000030 +wm 32 MX6_IOM_GRP_B2DS 0x00000030 +wm 32 MX6_IOM_GRP_B3DS 0x00000030 +wm 32 MX6_IOM_GRP_B4DS 0x00000030 +wm 32 MX6_IOM_GRP_B5DS 0x00000030 +wm 32 MX6_IOM_GRP_B6DS 0x00000030 +wm 32 MX6_IOM_GRP_B7DS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MDMISC 0x00081740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDCFG0 0x555a7975 +wm 32 MX6_MMDC_P0_MDCFG1 0xff538e64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x005b0e21 +wm 32 MX6_MMDC_P0_MDOTC 0x09444040 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MDASP 0x00000027 +wm 32 MX6_MMDC_P0_MDCTL 0x831a0000 +wm 32 MX6_MMDC_P0_MDSCR 0x04088032 +wm 32 MX6_MMDC_P0_MDSCR 0x0408803a +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x0000803b +wm 32 MX6_MMDC_P0_MDSCR 0x00428031 +wm 32 MX6_MMDC_P0_MDSCR 0x00428039 +wm 32 MX6_MMDC_P0_MDSCR 0x09408030 +wm 32 MX6_MMDC_P0_MDSCR 0x09408038 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDSCR 0x04008048 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380003 +wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1380003 +wm 32 MX6_MMDC_P0_MDREF 0x00005800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00000007 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00000007 +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x427b030a +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x02740269 +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x43100313 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x027d024d +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x46384240 +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x4442414a +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x45444645 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x4a354946 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001f001f +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001f001f +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x00440044 +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x00440044 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 wm 32 0x020e0010 0xf00000ff wm 32 0x020e0018 0x007f007f wm 32 0x020e001c 0x007f007f diff --git a/arch/arm/boards/guf-santaro/flash-header.imxcfg b/arch/arm/boards/guf-santaro/flash-header.imxcfg index 510cae3c88..2e85e13ba9 100644 --- a/arch/arm/boards/guf-santaro/flash-header.imxcfg +++ b/arch/arm/boards/guf-santaro/flash-header.imxcfg @@ -2,108 +2,111 @@ loadaddr 0x10000000 soc imx6 dcdofs 0x400 -wm 32 0x020e0798 0x000c0000 -wm 32 0x020e0758 0x00000000 - -wm 32 0x020e0588 0x00000030 -wm 32 0x020e0594 0x00000030 - -wm 32 0x020e056c 0x00000030 -wm 32 0x020e0578 0x00000030 -wm 32 0x020e074c 0x00000030 - -wm 32 0x020e057c 0x00000030 - -wm 32 0x020e058c 0x00000000 -wm 32 0x020e059c 0x00000030 -wm 32 0x020e05a0 0x00000030 -wm 32 0x020e078c 0x00000030 - -wm 32 0x020e0750 0x00020000 - -wm 32 0x020e05a8 0x00000030 -wm 32 0x020e05b0 0x00000030 -wm 32 0x020e0524 0x00000030 -wm 32 0x020e051c 0x00000030 -wm 32 0x020e0518 0x00000030 -wm 32 0x020e050c 0x00000030 -wm 32 0x020e05b8 0x00000030 -wm 32 0x020e05c0 0x00000030 - -wm 32 0x020e0774 0x00020000 - -wm 32 0x020e0784 0x00000030 -wm 32 0x020e0788 0x00000030 -wm 32 0x020e0794 0x00000030 -wm 32 0x020e079c 0x00000030 -wm 32 0x020e07a0 0x00000030 -wm 32 0x020e07a4 0x00000030 -wm 32 0x020e07a8 0x00000030 -wm 32 0x020e0748 0x00000030 - -wm 32 0x020e05ac 0x00000030 -wm 32 0x020e05b4 0x00000030 -wm 32 0x020e0528 0x00000030 -wm 32 0x020e0520 0x00000030 -wm 32 0x020e0514 0x00000030 -wm 32 0x020e0510 0x00000030 -wm 32 0x020e05bc 0x00000030 -wm 32 0x020e05c4 0x00000030 - -wm 32 0x021b0800 0xa1390003 - -wm 32 0x021b080c 0x001f001f -wm 32 0x021b0810 0x001f001f -wm 32 0x021b480c 0x001f001f -wm 32 0x021b4810 0x001f001f - -wm 32 0x021b083c 0x4333033f -wm 32 0x021b0840 0x032c031d -wm 32 0x021b483c 0x43200332 -wm 32 0x021b4840 0x031a026a -wm 32 0x021b0848 0x4d464746 -wm 32 0x021b4848 0x47453f4d -wm 32 0x021b0850 0x3e434440 -wm 32 0x021b4850 0x47384839 - -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 - -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 - -wm 32 0x021b0004 0x00020036 -wm 32 0x021b0008 0x09444040 -wm 32 0x021b000c 0x555a7975 -wm 32 0x021b0010 0xff538f64 -wm 32 0x021b0014 0x01ff00db -wm 32 0x021b0018 0x00001740 - -wm 32 0x021b001c 0x00008000 -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x005a1023 -wm 32 0x021b0040 0x00000027 - -wm 32 0x021b0000 0x831a0000 - -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x00048031 -wm 32 0x021b001c 0x09408030 -wm 32 0x021b001c 0x04008040 - -wm 32 0x021b0020 0x00005800 - -wm 32 0x021b0818 0x00011117 -wm 32 0x021b4818 0x00011117 - -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0404 0x00011006 -wm 32 0x021b001c 0x00000000 +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6q-ddr-regs.h> + +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 + +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00000030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00000030 + +wm 32 MX6_IOM_DRAM_CAS 0x00000030 +wm 32 MX6_IOM_DRAM_RAS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 + +wm 32 MX6_IOM_DRAM_RESET 0x00000030 + +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00000030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00000030 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 + +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 + +wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 + +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 + +wm 32 MX6_IOM_GRP_B0DS 0x00000030 +wm 32 MX6_IOM_GRP_B1DS 0x00000030 +wm 32 MX6_IOM_GRP_B2DS 0x00000030 +wm 32 MX6_IOM_GRP_B3DS 0x00000030 +wm 32 MX6_IOM_GRP_B4DS 0x00000030 +wm 32 MX6_IOM_GRP_B5DS 0x00000030 +wm 32 MX6_IOM_GRP_B6DS 0x00000030 +wm 32 MX6_IOM_GRP_B7DS 0x00000030 + +wm 32 MX6_IOM_DRAM_DQM0 0x00000030 +wm 32 MX6_IOM_DRAM_DQM1 0x00000030 +wm 32 MX6_IOM_DRAM_DQM2 0x00000030 +wm 32 MX6_IOM_DRAM_DQM3 0x00000030 +wm 32 MX6_IOM_DRAM_DQM4 0x00000030 +wm 32 MX6_IOM_DRAM_DQM5 0x00000030 +wm 32 MX6_IOM_DRAM_DQM6 0x00000030 +wm 32 MX6_IOM_DRAM_DQM7 0x00000030 + +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 + +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001f001f +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001f001f +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x001f001f +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x001f001f + +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x4333033f +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x032c031d +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x43200332 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x031a026a +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x4d464746 +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x47453f4d +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x3e434440 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x47384839 + +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 + +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 + +wm 32 MX6_MMDC_P0_MDPDC 0x00020036 +wm 32 MX6_MMDC_P0_MDOTC 0x09444040 +wm 32 MX6_MMDC_P0_MDCFG0 0x555a7975 +wm 32 MX6_MMDC_P0_MDCFG1 0xff538f64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db +wm 32 MX6_MMDC_P0_MDMISC 0x00001740 + +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x005a1023 +wm 32 MX6_MMDC_P0_MDASP 0x00000027 + +wm 32 MX6_MMDC_P0_MDCTL 0x831a0000 + +wm 32 MX6_MMDC_P0_MDSCR 0x04088032 +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x00048031 +wm 32 MX6_MMDC_P0_MDSCR 0x09408030 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 + +wm 32 MX6_MMDC_P0_MDREF 0x00005800 + +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00011117 + +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg index dd1ae6e5e9..c58ef4e35a 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg @@ -2,6 +2,9 @@ soc imx6 loadaddr 0x20000000 dcdofs 0x400 +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6dl-ddr-regs.h> + wm 32 0x020e0158 0x00000016 wm 32 0x020e0174 0x00000011 wm 32 0x020e0528 0x0000f079 @@ -30,107 +33,107 @@ wm 32 0x020e0314 0x00000001 wm 32 0x020e0318 0x00000001 wm 32 0x020e08f8 0x00000003 wm 32 0x020e027c 0x00000000 -wm 32 0x020e0470 0x00020030 -wm 32 0x020e0474 0x00020030 -wm 32 0x020e0478 0x00020030 -wm 32 0x020e047c 0x00020030 -wm 32 0x020e0424 0x00020200 -wm 32 0x020e0428 0x00020200 -wm 32 0x020e0444 0x00020200 -wm 32 0x020e0448 0x00020200 -wm 32 0x020e044c 0x00020200 -wm 32 0x020e0450 0x00020200 -wm 32 0x020e0454 0x00020200 -wm 32 0x020e0458 0x00020200 -wm 32 0x020e045c 0x00020200 -wm 32 0x020e0460 0x00020200 -wm 32 0x020e042c 0x00020200 -wm 32 0x020e0430 0x00020200 -wm 32 0x020e0434 0x00020200 -wm 32 0x020e0438 0x00020200 -wm 32 0x020e043c 0x00020200 -wm 32 0x020e0440 0x00020200 -wm 32 0x020e0464 0x00020030 -wm 32 0x020e0490 0x00020030 -wm 32 0x020e04ac 0x00020030 -wm 32 0x020e04b0 0x00020030 -wm 32 0x020e0494 0x00020030 -wm 32 0x020e04a4 0x00003000 -wm 32 0x020e04a8 0x00003000 -wm 32 0x020e0498 0x00000000 -wm 32 0x020e049c 0x00000000 -wm 32 0x020e04a0 0x00000000 -wm 32 0x020e04b4 0x00003030 -wm 32 0x020e04b8 0x00003030 -wm 32 0x020e0784 0x00000030 +wm 32 MX6_IOM_DRAM_DQM0 0x00020030 +wm 32 MX6_IOM_DRAM_DQM1 0x00020030 +wm 32 MX6_IOM_DRAM_DQM2 0x00020030 +wm 32 MX6_IOM_DRAM_DQM3 0x00020030 +wm 32 MX6_IOM_DRAM_ADDR00 0x00020200 +wm 32 MX6_IOM_DRAM_ADDR01 0x00020200 +wm 32 MX6_IOM_DRAM_ADDR02 0x00020200 +wm 32 MX6_IOM_DRAM_ADDR03 0x00020200 +wm 32 MX6_IOM_DRAM_ADDR04 0x00020200 +wm 32 MX6_IOM_DRAM_ADDR05 0x00020200 +wm 32 MX6_IOM_DRAM_ADDR06 0x00020200 +wm 32 MX6_IOM_DRAM_ADDR07 0x00020200 +wm 32 MX6_IOM_DRAM_ADDR08 0x00020200 +wm 32 MX6_IOM_DRAM_ADDR09 0x00020200 +wm 32 MX6_IOM_DRAM_ADDR10 0x00020200 +wm 32 MX6_IOM_DRAM_ADDR11 0x00020200 +wm 32 MX6_IOM_DRAM_ADDR12 0x00020200 +wm 32 MX6_IOM_DRAM_ADDR13 0x00020200 +wm 32 MX6_IOM_DRAM_ADDR14 0x00020200 +wm 32 MX6_IOM_DRAM_ADDR15 0x00020200 +wm 32 MX6_IOM_DRAM_CAS 0x00020030 +wm 32 MX6_IOM_DRAM_RAS 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00020030 +wm 32 MX6_IOM_DRAM_RESET 0x00020030 +wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000 +wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000 +wm 32 MX6_IOM_DRAM_SDBA0 0x00000000 +wm 32 MX6_IOM_DRAM_SDBA1 0x00000000 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00003030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00003030 +wm 32 MX6_IOM_GRP_B5DS 0x00000030 wm 32 0x020e0788 0x00000030 wm 32 0x020e0794 0x00000030 wm 32 0x020e079c 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e0754 0x00000000 -wm 32 0x020e0760 0x00020000 -wm 32 0x020e078c 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_B6DS 0x00000030 wm 32 0x020e0798 0x000c0000 wm 32 0x020e0758 0x00002000 -wm 32 0x020e075c 0x00000000 -wm 32 0x021b001c 0x04008010 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b0800 0xa1390001 -wm 32 0x021b080c 0x001e001e -wm 32 0x021b0810 0x001e001e -wm 32 0x021b083c 0x42490244 -wm 32 0x021b0840 0x022f0238 -wm 32 0x021b0848 0x40404040 -wm 32 0x021b0850 0x40404040 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b0018 0x00000742 -check 32 while_all_bits_clear 0x021b0018 0x00000002 -wm 32 0x021b001c 0x00008000 -check 32 while_any_bit_clear 0x021b001c 0x00004000 -wm 32 0x021b0000 0x83190000 -check 32 while_any_bit_clear 0x021b0018 0x40000000 -wm 32 0x021b000c 0x3f435333 -wm 32 0x021b0010 0xb66e8a63 -wm 32 0x021b0014 0x01ff00db -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x00431023 -wm 32 0x021b0008 0x1b333030 -wm 32 0x021b0004 0x0002006d -wm 32 0x021b0040 0x00000017 -wm 32 0x021b001c 0x05208030 -wm 32 0x021b001c 0x00048031 -wm 32 0x021b001c 0x00408032 -wm 32 0x021b001c 0x00008033 -wm 32 0x021b0020 0x0000c000 -wm 32 0x021b001c 0x00008020 -wm 32 0x021b0818 0x00022222 -wm 32 0x021b0890 0x00000003 -wm 32 0x021b0404 0x00000001 -wm 32 0x021b001c 0x04008010 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b0800 0xa1390001 -check 32 while_all_bits_clear 0x021b0800 0x00010000 -wm 32 0x021b0800 0xa1380000 -wm 32 0x021b001c 0x00048033 -wm 32 0x020e04bc 0x00000030 -wm 32 0x020e04c0 0x00000030 -wm 32 0x020e04c4 0x00000030 -wm 32 0x020e04c8 0x00000030 -wm 32 0x021b001c 0x04008050 -wm 32 0x021b0860 0x00000030 -check 32 while_all_bits_clear 0x021b0860 0x0000001f -wm 32 0x021b001c 0x04008050 -wm 32 0x021b0864 0x00000030 -check 32 while_all_bits_clear 0x021b0864 0x0000001f -wm 32 0x021b001c 0x00008033 -wm 32 0x021b0800 0xa138002b -wm 32 0x021b0020 0x00001800 -wm 32 0x021b0404 0x00001000 -wm 32 0x021b0004 0x0002556d -wm 32 0x021b001c 0x00000000 -check 32 while_all_bits_clear 0x021b001c 0x00004000 +wm 32 MX6_IOM_GRP_DDRHYS 0x00000000 +wm 32 MX6_MMDC_P0_MDSCR 0x04008010 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001e001e +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001e001e +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x42490244 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x022f0238 +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x40404040 +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x40404040 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDMISC 0x00000742 +check 32 while_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +check 32 while_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000 +wm 32 MX6_MMDC_P0_MDCTL 0x83190000 +check 32 while_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000 +wm 32 MX6_MMDC_P0_MDCFG0 0x3f435333 +wm 32 MX6_MMDC_P0_MDCFG1 0xb66e8a63 +wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x00431023 +wm 32 MX6_MMDC_P0_MDOTC 0x1b333030 +wm 32 MX6_MMDC_P0_MDPDC 0x0002006d +wm 32 MX6_MMDC_P0_MDASP 0x00000017 +wm 32 MX6_MMDC_P0_MDSCR 0x05208030 +wm 32 MX6_MMDC_P0_MDSCR 0x00048031 +wm 32 MX6_MMDC_P0_MDSCR 0x00408032 +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDREF 0x0000c000 +wm 32 MX6_MMDC_P0_MDSCR 0x00008020 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00022222 +wm 32 MX6_MMDC_P0_MPPDCMPR2 0x00000003 +wm 32 MX6_MMDC_P0_MAPSR 0x00000001 +wm 32 MX6_MMDC_P0_MDSCR 0x04008010 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001 +check 32 while_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000 +wm 32 MX6_MMDC_P0_MDSCR 0x00048033 +wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000030 +wm 32 MX6_MMDC_P0_MDSCR 0x04008050 +wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030 +check 32 while_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f +wm 32 MX6_MMDC_P0_MDSCR 0x04008050 +wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030 +check 32 while_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b +wm 32 MX6_MMDC_P0_MDREF 0x00001800 +wm 32 MX6_MMDC_P0_MAPSR 0x00001000 +wm 32 MX6_MMDC_P0_MDPDC 0x0002556d +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 +check 32 while_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000 diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg index be4efe3c70..56cb3292a9 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg @@ -2,6 +2,9 @@ soc imx6 loadaddr 0x20000000 dcdofs 0x400 +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6q-ddr-regs.h> + wm 32 0x020e00a4 0x00000016 wm 32 0x020e00c4 0x00000011 wm 32 0x020e03b8 0x0000f079 @@ -30,14 +33,14 @@ wm 32 0x020e02c0 0x00000001 wm 32 0x020e02c4 0x00000001 wm 32 0x020e091c 0x00000003 wm 32 0x020e02ec 0x00000000 -wm 32 0x020e05ac 0x00020030 -wm 32 0x020e05b4 0x00020030 -wm 32 0x020e0528 0x00020030 -wm 32 0x020e0520 0x00020030 -wm 32 0x020e0514 0x00020030 -wm 32 0x020e0510 0x00020030 -wm 32 0x020e05bc 0x00020030 -wm 32 0x020e05c4 0x00020030 +wm 32 MX6_IOM_DRAM_DQM0 0x00020030 +wm 32 MX6_IOM_DRAM_DQM1 0x00020030 +wm 32 MX6_IOM_DRAM_DQM2 0x00020030 +wm 32 MX6_IOM_DRAM_DQM3 0x00020030 +wm 32 MX6_IOM_DRAM_DQM4 0x00020030 +wm 32 MX6_IOM_DRAM_DQM5 0x00020030 +wm 32 MX6_IOM_DRAM_DQM6 0x00020030 +wm 32 MX6_IOM_DRAM_DQM7 0x00020030 wm 32 0x020e052c 0x00020200 wm 32 0x020e0530 0x00020200 wm 32 0x020e0534 0x00020200 @@ -54,32 +57,32 @@ wm 32 0x020e055c 0x00020200 wm 32 0x020e0560 0x00020200 wm 32 0x020e0564 0x00020200 wm 32 0x020e0568 0x00020200 -wm 32 0x020e056c 0x00020030 -wm 32 0x020e0578 0x00020030 -wm 32 0x020e0588 0x00020030 -wm 32 0x020e0594 0x00020030 -wm 32 0x020e057c 0x00020030 -wm 32 0x020e0590 0x00003000 -wm 32 0x020e0598 0x00003000 +wm 32 MX6_IOM_DRAM_CAS 0x00020030 +wm 32 MX6_IOM_DRAM_RAS 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00020030 +wm 32 MX6_IOM_DRAM_RESET 0x00020030 +wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000 +wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000 wm 32 0x020e0580 0x00000000 wm 32 0x020e0584 0x00000000 -wm 32 0x020e058c 0x00000000 -wm 32 0x020e059c 0x00003030 -wm 32 0x020e05a0 0x00003030 -wm 32 0x020e0784 0x00000030 -wm 32 0x020e0788 0x00000030 -wm 32 0x020e0794 0x00000030 -wm 32 0x020e079c 0x00000030 -wm 32 0x020e07a0 0x00000030 -wm 32 0x020e07a4 0x00000030 -wm 32 0x020e07a8 0x00000030 -wm 32 0x020e0748 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e0758 0x00000000 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0798 0x000c0000 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00003030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00003030 +wm 32 MX6_IOM_GRP_B0DS 0x00000030 +wm 32 MX6_IOM_GRP_B1DS 0x00000030 +wm 32 MX6_IOM_GRP_B2DS 0x00000030 +wm 32 MX6_IOM_GRP_B3DS 0x00000030 +wm 32 MX6_IOM_GRP_B4DS 0x00000030 +wm 32 MX6_IOM_GRP_B5DS 0x00000030 +wm 32 MX6_IOM_GRP_B6DS 0x00000030 +wm 32 MX6_IOM_GRP_B7DS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 wm 32 0x020e0768 0x00002000 wm 32 0x020e0770 0x00000000 wm 32 0x020e0754 0x00000200 @@ -90,85 +93,85 @@ wm 32 0x020e076c 0x00000200 wm 32 0x020e0778 0x00000200 wm 32 0x020e077c 0x00000200 wm 32 0x020e0780 0x00000200 -wm 32 0x021b001c 0x04008010 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b0800 0xa1390001 -wm 32 0x021b080c 0x001e001e -wm 32 0x021b0810 0x001e001e -wm 32 0x021b480c 0x001e001e -wm 32 0x021b4810 0x001e001e -wm 32 0x021b083c 0x43430349 -wm 32 0x021b0840 0x03330334 -wm 32 0x021b483c 0x434b0351 -wm 32 0x021b4840 0x033d030e -wm 32 0x021b0848 0x40404040 -wm 32 0x021b0850 0x40404040 -wm 32 0x021b4848 0x40404040 -wm 32 0x021b4850 0x40404040 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b0018 0x00000742 -check 32 while_all_bits_clear 0x021b0018 0x00000002 -wm 32 0x021b001c 0x00008000 -check 32 while_any_bit_clear 0x021b001c 0x00004000 -wm 32 0x021b0000 0x831a0000 -check 32 while_any_bit_clear 0x021b0018 0x40000000 -wm 32 0x021b000c 0x545a79a4 -wm 32 0x021b0010 0xff538e64 -wm 32 0x021b0014 0x01ff00dd -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x005a1023 -wm 32 0x021b0008 0x24444040 -wm 32 0x021b0004 0x00020076 -wm 32 0x021b0040 0x00000027 -wm 32 0x021b001c 0x09308030 -wm 32 0x021b001c 0x00048031 -wm 32 0x021b001c 0x00488032 -wm 32 0x021b001c 0x00008033 -wm 32 0x021b0020 0x0000c000 -wm 32 0x021b001c 0x00008020 -wm 32 0x021b0818 0x00022222 -wm 32 0x021b4818 0x00022222 -wm 32 0x021b0890 0x00000003 -wm 32 0x021b0404 0x00000001 -wm 32 0x021b001c 0x04008010 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b0800 0xa1390001 -check 32 while_all_bits_clear 0x021b0800 0x00010000 -wm 32 0x021b0800 0xa1380000 -wm 32 0x021b001c 0x00048033 -wm 32 0x020e05a8 0x00000030 -wm 32 0x020e05b0 0x00000030 -wm 32 0x020e0524 0x00000030 -wm 32 0x020e051c 0x00000030 -wm 32 0x020e0518 0x00000030 -wm 32 0x020e050c 0x00000030 -wm 32 0x020e05b8 0x00000030 -wm 32 0x020e05c0 0x00000030 -wm 32 0x021b001c 0x04008050 -wm 32 0x021b0860 0x00000030 -wm 32 0x021b4860 0x00000030 -check 32 while_all_bits_clear 0x021b0860 0x0000001f -check 32 while_all_bits_clear 0x021b4860 0x0000001f -wm 32 0x021b001c 0x04008050 -wm 32 0x021b0864 0x00000030 -check 32 while_all_bits_clear 0x021b0864 0x0000001f -wm 32 0x021b001c 0x04008050 -wm 32 0x021b4864 0x00000030 -check 32 while_all_bits_clear 0x021b4864 0x0000001f -wm 32 0x021b001c 0x00008033 -wm 32 0x021b0800 0xa138002b -wm 32 0x021b0020 0x00001800 -wm 32 0x021b0404 0x00001000 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b001c 0x00000000 -check 32 while_all_bits_clear 0x021b001c 0x00004000 +wm 32 MX6_MMDC_P0_MDSCR 0x04008010 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001e001e +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001e001e +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x001e001e +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x001e001e +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x43430349 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x03330334 +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x434b0351 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x033d030e +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x40404040 +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x40404040 +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x40404040 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x40404040 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDMISC 0x00000742 +check 32 while_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +check 32 while_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000 +wm 32 MX6_MMDC_P0_MDCTL 0x831a0000 +check 32 while_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000 +wm 32 MX6_MMDC_P0_MDCFG0 0x545a79a4 +wm 32 MX6_MMDC_P0_MDCFG1 0xff538e64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00dd +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x005a1023 +wm 32 MX6_MMDC_P0_MDOTC 0x24444040 +wm 32 MX6_MMDC_P0_MDPDC 0x00020076 +wm 32 MX6_MMDC_P0_MDASP 0x00000027 +wm 32 MX6_MMDC_P0_MDSCR 0x09308030 +wm 32 MX6_MMDC_P0_MDSCR 0x00048031 +wm 32 MX6_MMDC_P0_MDSCR 0x00488032 +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDREF 0x0000c000 +wm 32 MX6_MMDC_P0_MDSCR 0x00008020 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00022222 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00022222 +wm 32 MX6_MMDC_P0_MPPDCMPR2 0x00000003 +wm 32 MX6_MMDC_P0_MAPSR 0x00000001 +wm 32 MX6_MMDC_P0_MDSCR 0x04008010 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001 +check 32 while_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000 +wm 32 MX6_MMDC_P0_MDSCR 0x00048033 +wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 +wm 32 MX6_MMDC_P0_MDSCR 0x04008050 +wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030 +wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030 +check 32 while_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f +check 32 while_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f +wm 32 MX6_MMDC_P0_MDSCR 0x04008050 +wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030 +check 32 while_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f +wm 32 MX6_MMDC_P0_MDSCR 0x04008050 +wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030 +check 32 while_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b +wm 32 MX6_MMDC_P0_MDREF 0x00001800 +wm 32 MX6_MMDC_P0_MAPSR 0x00001000 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 +check 32 while_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000 diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg index 455aab92ca..4eaca00fc7 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg @@ -2,6 +2,9 @@ soc imx6 loadaddr 0x20000000 dcdofs 0x400 +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6q-ddr-regs.h> + wm 32 0x020e00a4 0x00000016 wm 32 0x020e00c4 0x00000011 wm 32 0x020e03b8 0x0000f079 @@ -39,14 +42,14 @@ wm 32 0x020e02c0 0x00000001 wm 32 0x020e02c4 0x00000001 wm 32 0x020e091c 0x00000003 wm 32 0x020e02ec 0x00000000 -wm 32 0x020e05ac 0x00020030 -wm 32 0x020e05b4 0x00020030 -wm 32 0x020e0528 0x00020030 -wm 32 0x020e0520 0x00020030 -wm 32 0x020e0514 0x00020030 -wm 32 0x020e0510 0x00020030 -wm 32 0x020e05bc 0x00020030 -wm 32 0x020e05c4 0x00020030 +wm 32 MX6_IOM_DRAM_DQM0 0x00020030 +wm 32 MX6_IOM_DRAM_DQM1 0x00020030 +wm 32 MX6_IOM_DRAM_DQM2 0x00020030 +wm 32 MX6_IOM_DRAM_DQM3 0x00020030 +wm 32 MX6_IOM_DRAM_DQM4 0x00020030 +wm 32 MX6_IOM_DRAM_DQM5 0x00020030 +wm 32 MX6_IOM_DRAM_DQM6 0x00020030 +wm 32 MX6_IOM_DRAM_DQM7 0x00020030 wm 32 0x020e052c 0x00020200 wm 32 0x020e0530 0x00020200 wm 32 0x020e0534 0x00020200 @@ -63,32 +66,32 @@ wm 32 0x020e055c 0x00020200 wm 32 0x020e0560 0x00020200 wm 32 0x020e0564 0x00020200 wm 32 0x020e0568 0x00020200 -wm 32 0x020e056c 0x00020030 -wm 32 0x020e0578 0x00020030 -wm 32 0x020e0588 0x00020030 -wm 32 0x020e0594 0x00020030 -wm 32 0x020e057c 0x00020030 -wm 32 0x020e0590 0x00003000 -wm 32 0x020e0598 0x00003000 +wm 32 MX6_IOM_DRAM_CAS 0x00020030 +wm 32 MX6_IOM_DRAM_RAS 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00020030 +wm 32 MX6_IOM_DRAM_RESET 0x00020030 +wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000 +wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000 wm 32 0x020e0580 0x00000000 wm 32 0x020e0584 0x00000000 -wm 32 0x020e058c 0x00000000 -wm 32 0x020e059c 0x00003030 -wm 32 0x020e05a0 0x00003030 -wm 32 0x020e0784 0x00000030 -wm 32 0x020e0788 0x00000030 -wm 32 0x020e0794 0x00000030 -wm 32 0x020e079c 0x00000030 -wm 32 0x020e07a0 0x00000030 -wm 32 0x020e07a4 0x00000030 -wm 32 0x020e07a8 0x00000030 -wm 32 0x020e0748 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e0758 0x00000000 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0798 0x000c0000 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00003030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00003030 +wm 32 MX6_IOM_GRP_B0DS 0x00000030 +wm 32 MX6_IOM_GRP_B1DS 0x00000030 +wm 32 MX6_IOM_GRP_B2DS 0x00000030 +wm 32 MX6_IOM_GRP_B3DS 0x00000030 +wm 32 MX6_IOM_GRP_B4DS 0x00000030 +wm 32 MX6_IOM_GRP_B5DS 0x00000030 +wm 32 MX6_IOM_GRP_B6DS 0x00000030 +wm 32 MX6_IOM_GRP_B7DS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 wm 32 0x020e0768 0x00002000 wm 32 0x020e0770 0x00000000 wm 32 0x020e0754 0x00000200 @@ -99,85 +102,85 @@ wm 32 0x020e076c 0x00000200 wm 32 0x020e0778 0x00000200 wm 32 0x020e077c 0x00000200 wm 32 0x020e0780 0x00000200 -wm 32 0x021b001c 0x04008010 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b0800 0xa1390001 -wm 32 0x021b080c 0x001e001e -wm 32 0x021b0810 0x001e001e -wm 32 0x021b480c 0x001e001e -wm 32 0x021b4810 0x001e001e -wm 32 0x021b083c 0x43430349 -wm 32 0x021b0840 0x03330334 -wm 32 0x021b483c 0x434b0351 -wm 32 0x021b4840 0x033d030e -wm 32 0x021b0848 0x40404040 -wm 32 0x021b0850 0x40404040 -wm 32 0x021b4848 0x40404040 -wm 32 0x021b4850 0x40404040 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b0018 0x00000742 -check 32 while_all_bits_clear 0x021b0018 0x00000002 -wm 32 0x021b001c 0x00008000 -check 32 while_any_bit_clear 0x021b001c 0x00004000 -wm 32 0x021b0000 0x841a0000 -check 32 while_any_bit_clear 0x021b0018 0x40000000 -wm 32 0x021b000c 0x898f78f4 -wm 32 0x021b0010 0xff328e64 -wm 32 0x021b0014 0x01ff00db -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x008f1023 -wm 32 0x021b0008 0x24444040 -wm 32 0x021b0004 0x00020076 -wm 32 0x021b0040 0x00000047 -wm 32 0x021b001c 0x09308030 -wm 32 0x021b001c 0x00048031 -wm 32 0x021b001c 0x00488032 -wm 32 0x021b001c 0x00008033 -wm 32 0x021b0020 0x0000c000 -wm 32 0x021b001c 0x00008020 -wm 32 0x021b0818 0x00022222 -wm 32 0x021b4818 0x00022222 -wm 32 0x021b0890 0x00000003 -set_bits 32 0x021b0400 0x02000000 -wm 32 0x021b0404 0x00000001 -wm 32 0x021b001c 0x04008010 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b0800 0xa1390001 -check 32 while_all_bits_clear 0x021b0800 0x00010000 -wm 32 0x021b0800 0xa1380000 -wm 32 0x021b001c 0x00048033 -wm 32 0x020e05a8 0x00000030 -wm 32 0x020e05b0 0x00000030 -wm 32 0x020e0524 0x00000030 -wm 32 0x020e051c 0x00000030 -wm 32 0x020e0518 0x00000030 -wm 32 0x020e050c 0x00000030 -wm 32 0x020e05b8 0x00000030 -wm 32 0x020e05c0 0x00000030 -wm 32 0x021b001c 0x04008050 -wm 32 0x021b0860 0x00000030 -wm 32 0x021b4860 0x00000030 -check 32 while_all_bits_clear 0x021b0860 0x0000001f -check 32 while_all_bits_clear 0x021b4860 0x0000001f -wm 32 0x021b001c 0x04008050 -wm 32 0x021b0864 0x00000030 -check 32 while_all_bits_clear 0x021b0864 0x0000001f -wm 32 0x021b001c 0x04008050 -wm 32 0x021b4864 0x00000030 -check 32 while_all_bits_clear 0x021b4864 0x0000001f -wm 32 0x021b001c 0x00008033 -wm 32 0x021b0800 0xa138002b -wm 32 0x021b0020 0x00001800 -wm 32 0x021b0404 0x00001000 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b001c 0x00000000 -check 32 while_all_bits_clear 0x021b001c 0x00004000 +wm 32 MX6_MMDC_P0_MDSCR 0x04008010 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001e001e +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001e001e +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x001e001e +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x001e001e +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x43430349 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x03330334 +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x434b0351 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x033d030e +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x40404040 +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x40404040 +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x40404040 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x40404040 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDMISC 0x00000742 +check 32 while_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +check 32 while_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000 +wm 32 MX6_MMDC_P0_MDCTL 0x841a0000 +check 32 while_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000 +wm 32 MX6_MMDC_P0_MDCFG0 0x898f78f4 +wm 32 MX6_MMDC_P0_MDCFG1 0xff328e64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x008f1023 +wm 32 MX6_MMDC_P0_MDOTC 0x24444040 +wm 32 MX6_MMDC_P0_MDPDC 0x00020076 +wm 32 MX6_MMDC_P0_MDASP 0x00000047 +wm 32 MX6_MMDC_P0_MDSCR 0x09308030 +wm 32 MX6_MMDC_P0_MDSCR 0x00048031 +wm 32 MX6_MMDC_P0_MDSCR 0x00488032 +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDREF 0x0000c000 +wm 32 MX6_MMDC_P0_MDSCR 0x00008020 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00022222 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00022222 +wm 32 MX6_MMDC_P0_MPPDCMPR2 0x00000003 +set_bits 32 MX6_MMDC_P0_MAARCR 0x02000000 +wm 32 MX6_MMDC_P0_MAPSR 0x00000001 +wm 32 MX6_MMDC_P0_MDSCR 0x04008010 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001 +check 32 while_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000 +wm 32 MX6_MMDC_P0_MDSCR 0x00048033 +wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 +wm 32 MX6_MMDC_P0_MDSCR 0x04008050 +wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030 +wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030 +check 32 while_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f +check 32 while_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f +wm 32 MX6_MMDC_P0_MDSCR 0x04008050 +wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030 +check 32 while_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f +wm 32 MX6_MMDC_P0_MDSCR 0x04008050 +wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030 +check 32 while_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b +wm 32 MX6_MMDC_P0_MDREF 0x00001800 +wm 32 MX6_MMDC_P0_MAPSR 0x00001000 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 +check 32 while_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000 diff --git a/arch/arm/boards/kindle-mx50/Makefile b/arch/arm/boards/kindle-mx50/Makefile index 76ad17a1c2..2cc614a878 100644 --- a/arch/arm/boards/kindle-mx50/Makefile +++ b/arch/arm/boards/kindle-mx50/Makefile @@ -1,4 +1,3 @@ -obj-y += board.o flash-header-kindle-lpddr1.dcd.o flash-header-kindle-lpddr2.dcd.o -extra-y += flash-header-kindle-lpddr1.dcd.S flash-header-kindle-lpddr1.dcd flash-header-kindle-lpddr2.dcd.S flash-header-kindle-lpddr2.dcd +obj-y += board.o lwl-y += lowlevel.o bbenv-y += defaultenv-kindle-mx50 diff --git a/arch/arm/boards/phytec-phycore-imx7/Makefile b/arch/arm/boards/phytec-phycore-imx7/Makefile new file mode 100644 index 0000000000..01c7a259e9 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx7/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/phytec-phycore-imx7/board.c b/arch/arm/boards/phytec-phycore-imx7/board.c new file mode 100644 index 0000000000..c3ebd1fadf --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx7/board.c @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2017 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <init.h> +#include <environment.h> +#include <mach/bbu.h> +#include <asm/armlinux.h> +#include <generated/mach-types.h> +#include <partition.h> +#include <mach/generic.h> +#include <linux/sizes.h> +#include <asm/psci.h> +#include <io.h> +#include <mach/imx7-regs.h> +#include <serial/imx-uart.h> +#include <asm/secure.h> + +static int phycore_mx7_devices_init(void) +{ + if (!of_machine_is_compatible("phytec,imx7d-phycore-som")) + return 0; + + imx6_bbu_internal_mmc_register_handler("mmc", "/dev/mmc2.boot0.barebox", + BBU_HANDLER_FLAG_DEFAULT); + + psci_set_putc(imx_uart_putc, IOMEM(MX7_UART5_BASE_ADDR)); + + return 0; +} +device_initcall(phycore_mx7_devices_init); diff --git a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg new file mode 100644 index 0000000000..b1608dd9c7 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2016 NXP Semiconductors + * + * SPDX-License-Identifier: GPL-2.0 + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +soc imx7 +loadaddr 0x80000000 +dcdofs 0x400 + +wm 32 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +wm 32 0x30360388 0x40000000 +wm 32 0x30360384 0x40000000 + +wm 32 0x30391000 0x00000002 +wm 32 0x307a0000 0x01040001 +wm 32 0x307a01a0 0x80400003 +wm 32 0x307a01a4 0x00100020 +wm 32 0x307a01a8 0x80100004 +wm 32 0x307a0064 0x00400046 +wm 32 0x307a0490 0x00000001 +wm 32 0x307a00d0 0x00020083 +wm 32 0x307a00d4 0x00690000 +wm 32 0x307a00dc 0x09300004 +wm 32 0x307a00e0 0x04080000 +wm 32 0x307a00e4 0x00100004 +wm 32 0x307a00f4 0x0000033f +wm 32 0x307a0100 0x09081109 +wm 32 0x307a0104 0x0007020d +wm 32 0x307a0108 0x03040407 +wm 32 0x307a010c 0x00002006 +wm 32 0x307a0110 0x04020205 +wm 32 0x307a0114 0x03030202 +wm 32 0x307a0120 0x00000803 +wm 32 0x307a0180 0x00800020 +wm 32 0x307a0184 0x02000100 +wm 32 0x307a0190 0x02098204 +wm 32 0x307a0194 0x00030303 +wm 32 0x307a0200 0x00000016 +wm 32 0x307a0204 0x00171717 +wm 32 0x307a0214 0x04040404 +wm 32 0x307a0218 0x0f040404 +wm 32 0x307a0240 0x06000604 +wm 32 0x307a0244 0x00000001 +wm 32 0x30391000 0x00000000 +wm 32 0x30790000 0x17420f40 +wm 32 0x30790004 0x10210100 +wm 32 0x30790010 0x00060807 +wm 32 0x307900b0 0x1010007e +wm 32 0x3079009c 0x00000d6e +wm 32 0x30790020 0x08080808 +wm 32 0x30790030 0x08080808 +wm 32 0x30790050 0x01000010 +wm 32 0x30790050 0x00000010 + +wm 32 0x307900c0 0x0e407304 +wm 32 0x307900c0 0x0e447304 +wm 32 0x307900c0 0x0e447306 + +check 32 while_any_bit_clear 0x307900c4 0x1 + +wm 32 0x307900c0 0x0e447304 +wm 32 0x307900c0 0x0e407304 + +wm 32 0x30384130 0x00000000 +wm 32 0x30340020 0x00000178 +wm 32 0x30384130 0x00000002 +wm 32 0x30790018 0x0000000f + +check 32 while_any_bit_clear 0x307a0004 0x1 diff --git a/arch/arm/boards/phytec-phycore-imx7/lowlevel.c b/arch/arm/boards/phytec-phycore-imx7/lowlevel.c new file mode 100644 index 0000000000..ee2d7ae553 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx7/lowlevel.c @@ -0,0 +1,48 @@ +#define DEBUG +#include <io.h> +#include <common.h> +#include <linux/sizes.h> +#include <mach/generic.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/debug_ll.h> +#include <asm/cache.h> + +extern char __dtb_imx7d_phyboard_zeta_start[]; + +static noinline void phytec_phycore_imx7_start(void) +{ + void __iomem *iomuxbase = IOMEM(0x302c0000); + void __iomem *uart = IOMEM(MX7_UART5_BASE_ADDR); + void __iomem *ccmbase = IOMEM(MX7_CCM_BASE_ADDR); + void *fdt; + + writel(0x3, ccmbase + 0x4000 + 16 * 152 + 0x8); + writel(0x10000000, ccmbase + 0x8000 + 128 * 99); + writel(0x3, ccmbase + 0x4000 + 16 * 152 + 0x4); + writel(0x3, iomuxbase + 0x18); + writel(0x3, iomuxbase + 0x1c); + + imx7_uart_setup(uart); + + pbl_set_putc(imx_uart_putc, uart); + + pr_debug("Phytec phyCORE i.MX7\n"); + + fdt = __dtb_imx7d_phyboard_zeta_start - get_runtime_offset(); + + barebox_arm_entry(0x80000000, SZ_512M, fdt); +} + +ENTRY_FUNCTION(start_phytec_phycore_imx7, r0, r1, r2) +{ + imx7_cpu_lowlevel_init(); + + arm_early_mmu_cache_invalidate(); + + relocate_to_current_adr(); + setup_c(); + barrier(); + + phytec_phycore_imx7_start(); +}
\ No newline at end of file diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h index ebcc1ddf94..06ba308fb8 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h @@ -2,96 +2,99 @@ soc imx6 loadaddr 0x10000000 dcdofs 0x400 -wm 32 0x020e05a8 0x00000028 -wm 32 0x020e05b0 0x00000028 -wm 32 0x020e0524 0x00000028 -wm 32 0x020e051c 0x00000028 -wm 32 0x020e0518 0x00000028 -wm 32 0x020e050c 0x00000028 -wm 32 0x020e05b8 0x00000028 -wm 32 0x020e05c0 0x00000028 -wm 32 0x020e05ac 0x00000028 -wm 32 0x020e05b4 0x00000028 -wm 32 0x020e0528 0x00000028 -wm 32 0x020e0520 0x00000028 -wm 32 0x020e0514 0x00000028 -wm 32 0x020e0510 0x00000028 -wm 32 0x020e05bc 0x00000028 -wm 32 0x020e05c4 0x00000028 -wm 32 0x020e056c 0x00000028 -wm 32 0x020e0578 0x00000028 -wm 32 0x020e0588 0x00000028 -wm 32 0x020e0594 0x00000028 -wm 32 0x020e057c 0x00000028 -wm 32 0x020e0590 0x00003000 -wm 32 0x020e0598 0x00003000 -wm 32 0x020e058c 0x00000000 -wm 32 0x020e059c 0x00000028 -wm 32 0x020e05a0 0x00000028 -wm 32 0x020e0784 0x00000028 -wm 32 0x020e0788 0x00000028 -wm 32 0x020e0794 0x00000028 -wm 32 0x020e079c 0x00000028 -wm 32 0x020e07a0 0x00000028 -wm 32 0x020e07a4 0x00000028 -wm 32 0x020e07a8 0x00000028 -wm 32 0x020e0748 0x00000028 -wm 32 0x020e074c 0x00000028 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e0758 0x00000000 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e078c 0x00000028 -wm 32 0x020e0798 0x000c0000 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b0018 0x00091740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b0010 0xff328f64 -wm 32 0x021b0014 0x01ff00db -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0008 0x09444040 -wm 32 0x021b0004 0x00025576 +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6q-ddr-regs.h> + +wm 32 MX6_IOM_DRAM_SDQS0 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000028 +wm 32 MX6_IOM_DRAM_DQM0 0x00000028 +wm 32 MX6_IOM_DRAM_DQM1 0x00000028 +wm 32 MX6_IOM_DRAM_DQM2 0x00000028 +wm 32 MX6_IOM_DRAM_DQM3 0x00000028 +wm 32 MX6_IOM_DRAM_DQM4 0x00000028 +wm 32 MX6_IOM_DRAM_DQM5 0x00000028 +wm 32 MX6_IOM_DRAM_DQM6 0x00000028 +wm 32 MX6_IOM_DRAM_DQM7 0x00000028 +wm 32 MX6_IOM_DRAM_CAS 0x00000028 +wm 32 MX6_IOM_DRAM_RAS 0x00000028 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00000028 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00000028 +wm 32 MX6_IOM_DRAM_RESET 0x00000028 +wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000 +wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00000028 +wm 32 MX6_IOM_DRAM_SDODT1 0x00000028 +wm 32 MX6_IOM_GRP_B0DS 0x00000028 +wm 32 MX6_IOM_GRP_B1DS 0x00000028 +wm 32 MX6_IOM_GRP_B2DS 0x00000028 +wm 32 MX6_IOM_GRP_B3DS 0x00000028 +wm 32 MX6_IOM_GRP_B4DS 0x00000028 +wm 32 MX6_IOM_GRP_B5DS 0x00000028 +wm 32 MX6_IOM_GRP_B6DS 0x00000028 +wm 32 MX6_IOM_GRP_B7DS 0x00000028 +wm 32 MX6_IOM_GRP_ADDDS 0x00000028 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_CTLDS 0x00000028 +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MDMISC 0x00091740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDCFG1 0xff328f64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOTC 0x09444040 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 SETUP_MDCFG0 SETUP_MDOR_MDASP_MDCTL -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x0408803a -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x0000803b -wm 32 0x021b001c 0x00048031 -wm 32 0x021b001c 0x00048039 -wm 32 0x021b001c 0x09408030 -wm 32 0x021b001c 0x09408038 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b001c 0x04008048 -wm 32 0x021b0800 0xa1390003 -wm 32 0x021b4800 0xa1380003 -wm 32 0x021b0020 0x00007800 -wm 32 0x021b0818 0x00011117 -wm 32 0x021b4818 0x00011117 -wm 32 0x021b083c 0x4350035e -wm 32 0x021b0840 0x035c0358 -wm 32 0x021b483c 0x436e0376 -wm 32 0x021b4840 0x03770352 -wm 32 0x021b0848 0x3c333436 -wm 32 0x021b4848 0x35332f3b -wm 32 0x021b0850 0x37363e39 -wm 32 0x021b4850 0x432f433d -wm 32 0x021b080c 0x0013001b -wm 32 0x021b0810 0x003b0034 -wm 32 0x021b480c 0x0037004b -wm 32 0x021b4810 0x004b0055 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b001c 0x00000000 -wm 32 0x021b0404 0x00011006 +wm 32 MX6_MMDC_P0_MDSCR 0x04088032 +wm 32 MX6_MMDC_P0_MDSCR 0x0408803a +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x0000803b +wm 32 MX6_MMDC_P0_MDSCR 0x00048031 +wm 32 MX6_MMDC_P0_MDSCR 0x00048039 +wm 32 MX6_MMDC_P0_MDSCR 0x09408030 +wm 32 MX6_MMDC_P0_MDSCR 0x09408038 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDSCR 0x04008048 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 +wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1380003 +wm 32 MX6_MMDC_P0_MDREF 0x00007800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x4350035e +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x035c0358 +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x436e0376 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x03770352 +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x3c333436 +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x35332f3b +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x37363e39 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x432f433d +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x0013001b +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x003b0034 +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x0037004b +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x004b0055 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 wm 32 0x020e0010 0xf00000ff wm 32 0x020e0018 0x007f007f wm 32 0x020e001c 0x007f007f diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h index 7cdf45ccea..8b83aeae63 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h @@ -2,100 +2,103 @@ soc imx6 loadaddr 0x10000000 dcdofs 0x400 -wm 32 0x020e0798 0x000C0000 -wm 32 0x020e0758 0x00000000 -wm 32 0x020e0588 0x00000030 -wm 32 0x020e0594 0x00000030 -wm 32 0x020e056c 0x00000030 -wm 32 0x020e0578 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e057c 0x00000030 -wm 32 0x020e058c 0x00000000 -wm 32 0x020e059c 0x00000030 -wm 32 0x020e05a0 0x00000030 -wm 32 0x020e0590 0x00003000 -wm 32 0x020e0598 0x00003000 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e05a8 0x00000028 -wm 32 0x020e05b0 0x00000028 -wm 32 0x020e0524 0x00000028 -wm 32 0x020e051c 0x00000028 -wm 32 0x020e0518 0x00000028 -wm 32 0x020e050c 0x00000028 -wm 32 0x020e05b8 0x00000028 -wm 32 0x020e05c0 0x00000028 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e0784 0x00000028 -wm 32 0x020e0788 0x00000028 -wm 32 0x020e0794 0x00000028 -wm 32 0x020e079c 0x00000028 -wm 32 0x020e07a0 0x00000028 -wm 32 0x020e07a4 0x00000028 -wm 32 0x020e07a8 0x00000028 -wm 32 0x020e0748 0x00000028 -wm 32 0x020e05ac 0x00000028 -wm 32 0x020e05b4 0x00000028 -wm 32 0x020e0528 0x00000028 -wm 32 0x020e0520 0x00000028 -wm 32 0x020e0514 0x00000028 -wm 32 0x020e0510 0x00000028 -wm 32 0x020e05bc 0x00000028 -wm 32 0x020e05c4 0x00000028 -wm 32 0x021b0800 0xa1390003 -wm 32 0x021b4800 0xa1380003 -wm 32 0x021b080c 0x00140014 -wm 32 0x021b0810 0x00230018 -wm 32 0x021b480c 0x000A001E -wm 32 0x021b4810 0x000A0015 -wm 32 0x021b083c 0x43080314 -wm 32 0x021b0840 0x02680300 -wm 32 0x021b483c 0x430C0318 -wm 32 0x021b4840 0x03000254 -wm 32 0x021b0848 0x3A323234 -wm 32 0x021b4848 0x3E3C3242 -wm 32 0x021b0850 0x2A2E3632 -wm 32 0x021b4850 0x3C323E34 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b0004 0x00020036 -wm 32 0x021b0008 0x09444040 +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6q-ddr-regs.h> + +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00000030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00000030 +wm 32 MX6_IOM_DRAM_CAS 0x00000030 +wm 32 MX6_IOM_DRAM_RAS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_DRAM_RESET 0x00000030 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00000030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00000030 +wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000 +wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_DRAM_SDQS0 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000028 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_B0DS 0x00000028 +wm 32 MX6_IOM_GRP_B1DS 0x00000028 +wm 32 MX6_IOM_GRP_B2DS 0x00000028 +wm 32 MX6_IOM_GRP_B3DS 0x00000028 +wm 32 MX6_IOM_GRP_B4DS 0x00000028 +wm 32 MX6_IOM_GRP_B5DS 0x00000028 +wm 32 MX6_IOM_GRP_B6DS 0x00000028 +wm 32 MX6_IOM_GRP_B7DS 0x00000028 +wm 32 MX6_IOM_DRAM_DQM0 0x00000028 +wm 32 MX6_IOM_DRAM_DQM1 0x00000028 +wm 32 MX6_IOM_DRAM_DQM2 0x00000028 +wm 32 MX6_IOM_DRAM_DQM3 0x00000028 +wm 32 MX6_IOM_DRAM_DQM4 0x00000028 +wm 32 MX6_IOM_DRAM_DQM5 0x00000028 +wm 32 MX6_IOM_DRAM_DQM6 0x00000028 +wm 32 MX6_IOM_DRAM_DQM7 0x00000028 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 +wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1380003 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x00140014 +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x00230018 +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x000A001E +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x000A0015 +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x43080314 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x02680300 +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x430C0318 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x03000254 +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x3A323234 +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x3E3C3242 +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x2A2E3632 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x3C323E34 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDPDC 0x00020036 +wm 32 MX6_MMDC_P0_MDOTC 0x09444040 SETUP_MDCFG0 -wm 32 0x021b0010 0xFF328F64 -wm 32 0x021b0014 0x01FF00DB -wm 32 0x021b0018 0x00011740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x003F1023 +wm 32 MX6_MMDC_P0_MDCFG1 0xFF328F64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01FF00DB +wm 32 MX6_MMDC_P0_MDMISC 0x00011740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x003F1023 SETUP_MDASP_MDCTL -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x0408803a -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x0000803b -wm 32 0x021b001c 0x00048031 -wm 32 0x021b001c 0x00048039 -wm 32 0x021b001c 0x09408030 -wm 32 0x021b001c 0x09408038 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b001c 0x04008048 -wm 32 0x021b0020 0x00007800 -wm 32 0x021b0818 0x00011117 -wm 32 0x021b4818 0x00011117 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0404 0x00011006 -wm 32 0x021b001c 0x00000000 +wm 32 MX6_MMDC_P0_MDSCR 0x04088032 +wm 32 MX6_MMDC_P0_MDSCR 0x0408803a +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x0000803b +wm 32 MX6_MMDC_P0_MDSCR 0x00048031 +wm 32 MX6_MMDC_P0_MDSCR 0x00048039 +wm 32 MX6_MMDC_P0_MDSCR 0x09408030 +wm 32 MX6_MMDC_P0_MDSCR 0x09408038 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDSCR 0x04008048 +wm 32 MX6_MMDC_P0_MDREF 0x00007800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 wm 32 0x020e0010 0xf00000ff wm 32 0x020e0018 0x007F007F wm 32 0x020e001c 0x007F007F diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h index a6e4578cb1..da4708e4e3 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h @@ -2,97 +2,100 @@ soc imx6 loadaddr 0x10000000 dcdofs 0x400 -wm 32 0x020e0774 0x000C0000 -wm 32 0x020e0754 0x00000000 -wm 32 0x020e04ac 0x00000030 -wm 32 0x020e04b0 0x00000030 -wm 32 0x020e0464 0x00000030 -wm 32 0x020e0490 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e0494 0x00000030 -wm 32 0x020e04a0 0x00000000 -wm 32 0x020e04b4 0x00000030 -wm 32 0x020e04b8 0x00000030 -wm 32 0x020e04a4 0x00003000 -wm 32 0x020e04a8 0x00003000 -wm 32 0x020e076c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e04bc 0x00000028 -wm 32 0x020e04c0 0x00000028 -wm 32 0x020e04c4 0x00000028 -wm 32 0x020e04c8 0x00000028 -wm 32 0x020e04cc 0x00000028 -wm 32 0x020e04d0 0x00000028 -wm 32 0x020e04d4 0x00000028 -wm 32 0x020e04d8 0x00000028 -wm 32 0x020e0760 0x00020000 -wm 32 0x020e0764 0x00000028 -wm 32 0x020e0770 0x00000028 -wm 32 0x020e0778 0x00000028 -wm 32 0x020e077c 0x00000028 -wm 32 0x020e0780 0x00000028 -wm 32 0x020e0784 0x00000028 -wm 32 0x020e078c 0x00000028 -wm 32 0x020e0748 0x00000028 -wm 32 0x020e0470 0x00000028 -wm 32 0x020e0474 0x00000028 -wm 32 0x020e0478 0x00000028 -wm 32 0x020e047c 0x00000028 -wm 32 0x020e0480 0x00000028 -wm 32 0x020e0484 0x00000028 -wm 32 0x020e0488 0x00000028 -wm 32 0x020e048c 0x00000028 -wm 32 0x021b0800 0xa1390003 -wm 32 0x021b4800 0xa1380003 -wm 32 0x021b080c 0x0019001C -wm 32 0x021b0810 0x00140019 -wm 32 0x021b480c 0x00030003 -wm 32 0x021b4810 0x00030010 -wm 32 0x021b083c 0x42140210 -wm 32 0x021b0840 0x02040208 -wm 32 0x021b483c 0x42040208 -wm 32 0x021b4840 0x01680178 -wm 32 0x021b0848 0x40423E3E -wm 32 0x021b4848 0x4242443E -wm 32 0x021b0850 0x2C2C2A30 -wm 32 0x021b4850 0x2E2A3228 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0008 0x09444040 +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6dl-ddr-regs.h> + +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00000030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00000030 +wm 32 MX6_IOM_DRAM_CAS 0x00000030 +wm 32 MX6_IOM_DRAM_RAS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_DRAM_RESET 0x00000030 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00000030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00000030 +wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000 +wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_DRAM_SDQS0 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000028 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_B0DS 0x00000028 +wm 32 MX6_IOM_GRP_B1DS 0x00000028 +wm 32 MX6_IOM_GRP_B2DS 0x00000028 +wm 32 MX6_IOM_GRP_B3DS 0x00000028 +wm 32 MX6_IOM_GRP_B4DS 0x00000028 +wm 32 MX6_IOM_GRP_B5DS 0x00000028 +wm 32 MX6_IOM_GRP_B6DS 0x00000028 +wm 32 MX6_IOM_GRP_B7DS 0x00000028 +wm 32 MX6_IOM_DRAM_DQM0 0x00000028 +wm 32 MX6_IOM_DRAM_DQM1 0x00000028 +wm 32 MX6_IOM_DRAM_DQM2 0x00000028 +wm 32 MX6_IOM_DRAM_DQM3 0x00000028 +wm 32 MX6_IOM_DRAM_DQM4 0x00000028 +wm 32 MX6_IOM_DRAM_DQM5 0x00000028 +wm 32 MX6_IOM_DRAM_DQM6 0x00000028 +wm 32 MX6_IOM_DRAM_DQM7 0x00000028 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 +wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1380003 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x0019001C +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x00140019 +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x00030003 +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x00030010 +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x42140210 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x02040208 +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x42040208 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x01680178 +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x40423E3E +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x4242443E +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x2C2C2A30 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x2E2A3228 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MDOTC 0x09444040 SETUP_MDCFG0 -wm 32 0x021b0010 0xff538f64 -wm 32 0x021b0014 0x01ff0124 -wm 32 0x021b0018 0x00091740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x003F1023 +wm 32 MX6_MMDC_P0_MDCFG1 0xff538f64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01ff0124 +wm 32 MX6_MMDC_P0_MDMISC 0x00091740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x003F1023 SETUP_MDASP_MDCTL -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x0408803a -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x0000803b -wm 32 0x021b001c 0x00428031 -wm 32 0x021b001c 0x00428039 -wm 32 0x021b001c 0x09408030 -wm 32 0x021b001c 0x09408038 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b001c 0x04008048 -wm 32 0x021b0020 0x00007800 -wm 32 0x021b0818 0x00011117 -wm 32 0x021b4818 0x00011117 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0404 0x00011006 -wm 32 0x021b001c 0x00000000 +wm 32 MX6_MMDC_P0_MDSCR 0x04088032 +wm 32 MX6_MMDC_P0_MDSCR 0x0408803a +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x0000803b +wm 32 MX6_MMDC_P0_MDSCR 0x00428031 +wm 32 MX6_MMDC_P0_MDSCR 0x00428039 +wm 32 MX6_MMDC_P0_MDSCR 0x09408030 +wm 32 MX6_MMDC_P0_MDSCR 0x09408038 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDSCR 0x04008048 +wm 32 MX6_MMDC_P0_MDREF 0x00007800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h index 507b9c6236..c5ed9b759f 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h @@ -2,100 +2,103 @@ soc imx6 loadaddr 0x10000000 dcdofs 0x400 -wm 32 0x020e0798 0x000C0000 -wm 32 0x020e0758 0x00000000 -wm 32 0x020e0588 0x00000030 -wm 32 0x020e0594 0x00000030 -wm 32 0x020e056c 0x00000030 -wm 32 0x020e0578 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e057c 0x00000030 -wm 32 0x020e058c 0x00000000 -wm 32 0x020e059c 0x00000030 -wm 32 0x020e05a0 0x00000030 -wm 32 0x020e0590 0x00003000 -wm 32 0x020e0598 0x00003000 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e05a8 0x00000028 -wm 32 0x020e05b0 0x00000028 -wm 32 0x020e0524 0x00000028 -wm 32 0x020e051c 0x00000028 -wm 32 0x020e0518 0x00000028 -wm 32 0x020e050c 0x00000028 -wm 32 0x020e05b8 0x00000028 -wm 32 0x020e05c0 0x00000028 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e0784 0x00000028 -wm 32 0x020e0788 0x00000028 -wm 32 0x020e0794 0x00000028 -wm 32 0x020e079c 0x00000028 -wm 32 0x020e07a0 0x00000028 -wm 32 0x020e07a4 0x00000028 -wm 32 0x020e07a8 0x00000028 -wm 32 0x020e0748 0x00000028 -wm 32 0x020e05ac 0x00000028 -wm 32 0x020e05b4 0x00000028 -wm 32 0x020e0528 0x00000028 -wm 32 0x020e0520 0x00000028 -wm 32 0x020e0514 0x00000028 -wm 32 0x020e0510 0x00000028 -wm 32 0x020e05bc 0x00000028 -wm 32 0x020e05c4 0x00000028 -wm 32 0x021b0800 0xa1390003 -wm 32 0x021b4800 0xa1380003 -wm 32 0x021b080c 0x00110011 -wm 32 0x021b0810 0x00240024 -wm 32 0x021b480c 0x00260038 -wm 32 0x021b4810 0x002C0038 -wm 32 0x021b083c 0x03400350 -wm 32 0x021b0840 0x03440340 -wm 32 0x021b483c 0x034C0354 -wm 32 0x021b4840 0x035C033C -wm 32 0x021b0848 0x322A2A2A -wm 32 0x021b4848 0x302C2834 -wm 32 0x021b0850 0x34303834 -wm 32 0x021b4850 0x422A3E36 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0008 0x09444040 +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6q-ddr-regs.h> + +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00000030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00000030 +wm 32 MX6_IOM_DRAM_CAS 0x00000030 +wm 32 MX6_IOM_DRAM_RAS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_DRAM_RESET 0x00000030 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00000030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00000030 +wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000 +wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_DRAM_SDQS0 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000028 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_B0DS 0x00000028 +wm 32 MX6_IOM_GRP_B1DS 0x00000028 +wm 32 MX6_IOM_GRP_B2DS 0x00000028 +wm 32 MX6_IOM_GRP_B3DS 0x00000028 +wm 32 MX6_IOM_GRP_B4DS 0x00000028 +wm 32 MX6_IOM_GRP_B5DS 0x00000028 +wm 32 MX6_IOM_GRP_B6DS 0x00000028 +wm 32 MX6_IOM_GRP_B7DS 0x00000028 +wm 32 MX6_IOM_DRAM_DQM0 0x00000028 +wm 32 MX6_IOM_DRAM_DQM1 0x00000028 +wm 32 MX6_IOM_DRAM_DQM2 0x00000028 +wm 32 MX6_IOM_DRAM_DQM3 0x00000028 +wm 32 MX6_IOM_DRAM_DQM4 0x00000028 +wm 32 MX6_IOM_DRAM_DQM5 0x00000028 +wm 32 MX6_IOM_DRAM_DQM6 0x00000028 +wm 32 MX6_IOM_DRAM_DQM7 0x00000028 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 +wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1380003 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x00110011 +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x00240024 +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x00260038 +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x002C0038 +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x03400350 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x03440340 +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x034C0354 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x035C033C +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x322A2A2A +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x302C2834 +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x34303834 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x422A3E36 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MDOTC 0x09444040 SETUP_MDCFG0 -wm 32 0x021b0010 0xff538f64 -wm 32 0x021b0014 0x01ff0124 -wm 32 0x021b0018 0x00091740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x003F1023 +wm 32 MX6_MMDC_P0_MDCFG1 0xff538f64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01ff0124 +wm 32 MX6_MMDC_P0_MDMISC 0x00091740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x003F1023 SETUP_MDASP_MDCTL -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x0408803a -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x0000803b -wm 32 0x021b001c 0x00048031 -wm 32 0x021b001c 0x00048039 -wm 32 0x021b001c 0x09408030 -wm 32 0x021b001c 0x09408038 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b001c 0x04008048 -wm 32 0x021b0020 0x00007800 -wm 32 0x021b0818 0x00011117 -wm 32 0x021b4818 0x00011117 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0404 0x00011006 -wm 32 0x021b001c 0x00000000 +wm 32 MX6_MMDC_P0_MDSCR 0x04088032 +wm 32 MX6_MMDC_P0_MDSCR 0x0408803a +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x0000803b +wm 32 MX6_MMDC_P0_MDSCR 0x00048031 +wm 32 MX6_MMDC_P0_MDSCR 0x00048039 +wm 32 MX6_MMDC_P0_MDSCR 0x09408030 +wm 32 MX6_MMDC_P0_MDSCR 0x09408038 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDSCR 0x04008048 +wm 32 MX6_MMDC_P0_MDREF 0x00007800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 wm 32 0x020e0010 0xf00000ff wm 32 0x020e0018 0x007F007F wm 32 0x020e001c 0x007F007F diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h index 6cdf429cb1..405529ddf8 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h @@ -2,97 +2,100 @@ soc imx6 loadaddr 0x10000000 dcdofs 0x400 -wm 32 0x020e0774 0x000C0000 -wm 32 0x020e0754 0x00000000 -wm 32 0x020e04ac 0x00000030 -wm 32 0x020e04b0 0x00000030 -wm 32 0x020e0464 0x00000030 -wm 32 0x020e0490 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e0494 0x00000030 -wm 32 0x020e04a0 0x00000000 -wm 32 0x020e04b4 0x00000030 -wm 32 0x020e04b8 0x00000030 -wm 32 0x020e04a4 0x00003000 -wm 32 0x020e04a8 0x00003000 -wm 32 0x020e076c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e04bc 0x00000028 -wm 32 0x020e04c0 0x00000028 -wm 32 0x020e04c4 0x00000028 -wm 32 0x020e04c8 0x00000028 -wm 32 0x020e04cc 0x00000028 -wm 32 0x020e04d0 0x00000028 -wm 32 0x020e04d4 0x00000028 -wm 32 0x020e04d8 0x00000028 -wm 32 0x020e0760 0x00020000 -wm 32 0x020e0764 0x00000028 -wm 32 0x020e0770 0x00000028 -wm 32 0x020e0778 0x00000028 -wm 32 0x020e077c 0x00000028 -wm 32 0x020e0780 0x00000028 -wm 32 0x020e0784 0x00000028 -wm 32 0x020e078c 0x00000028 -wm 32 0x020e0748 0x00000028 -wm 32 0x020e0470 0x00000028 -wm 32 0x020e0474 0x00000028 -wm 32 0x020e0478 0x00000028 -wm 32 0x020e047c 0x00000028 -wm 32 0x020e0480 0x00000028 -wm 32 0x020e0484 0x00000028 -wm 32 0x020e0488 0x00000028 -wm 32 0x020e048c 0x00000028 -wm 32 0x021b0800 0xa1390003 -wm 32 0x021b4800 0xa1380003 -wm 32 0x021b080c 0x00110011 -wm 32 0x021b0810 0x00240024 -wm 32 0x021b480c 0x00260038 -wm 32 0x021b4810 0x002C0038 -wm 32 0x021b083c 0x02480248 -wm 32 0x021b0840 0x022f022d -wm 32 0x021b483c 0x02540258 -wm 32 0x021b4840 0x0236021e -wm 32 0x021b0848 0x332f3033 -wm 32 0x021b4848 0x302d2c35 -wm 32 0x021b0850 0x3030362a -wm 32 0x021b4850 0x3423372d -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0008 0x09444040 +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6dl-ddr-regs.h> + +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00000030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00000030 +wm 32 MX6_IOM_DRAM_CAS 0x00000030 +wm 32 MX6_IOM_DRAM_RAS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_DRAM_RESET 0x00000030 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00000030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00000030 +wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000 +wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_DRAM_SDQS0 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000028 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_B0DS 0x00000028 +wm 32 MX6_IOM_GRP_B1DS 0x00000028 +wm 32 MX6_IOM_GRP_B2DS 0x00000028 +wm 32 MX6_IOM_GRP_B3DS 0x00000028 +wm 32 MX6_IOM_GRP_B4DS 0x00000028 +wm 32 MX6_IOM_GRP_B5DS 0x00000028 +wm 32 MX6_IOM_GRP_B6DS 0x00000028 +wm 32 MX6_IOM_GRP_B7DS 0x00000028 +wm 32 MX6_IOM_DRAM_DQM0 0x00000028 +wm 32 MX6_IOM_DRAM_DQM1 0x00000028 +wm 32 MX6_IOM_DRAM_DQM2 0x00000028 +wm 32 MX6_IOM_DRAM_DQM3 0x00000028 +wm 32 MX6_IOM_DRAM_DQM4 0x00000028 +wm 32 MX6_IOM_DRAM_DQM5 0x00000028 +wm 32 MX6_IOM_DRAM_DQM6 0x00000028 +wm 32 MX6_IOM_DRAM_DQM7 0x00000028 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 +wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1380003 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x00110011 +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x00240024 +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x00260038 +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x002C0038 +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x02480248 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x022f022d +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x02540258 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x0236021e +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x332f3033 +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x302d2c35 +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x3030362a +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x3423372d +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MDOTC 0x09444040 SETUP_MDCFG0 -wm 32 0x021b0010 0xff538f64 -wm 32 0x021b0014 0x01ff0124 -wm 32 0x021b0018 0x00091740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x003F1023 +wm 32 MX6_MMDC_P0_MDCFG1 0xff538f64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01ff0124 +wm 32 MX6_MMDC_P0_MDMISC 0x00091740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x003F1023 SETUP_MDASP_MDCTL -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x0408803a -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x0000803b -wm 32 0x021b001c 0x00428031 -wm 32 0x021b001c 0x00428039 -wm 32 0x021b001c 0x09408030 -wm 32 0x021b001c 0x09408038 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b001c 0x04008048 -wm 32 0x021b0020 0x00007800 -wm 32 0x021b0818 0x00011117 -wm 32 0x021b4818 0x00011117 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0404 0x00011006 -wm 32 0x021b001c 0x00000000 +wm 32 MX6_MMDC_P0_MDSCR 0x04088032 +wm 32 MX6_MMDC_P0_MDSCR 0x0408803a +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x0000803b +wm 32 MX6_MMDC_P0_MDSCR 0x00428031 +wm 32 MX6_MMDC_P0_MDSCR 0x00428039 +wm 32 MX6_MMDC_P0_MDSCR 0x09408030 +wm 32 MX6_MMDC_P0_MDSCR 0x09408038 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDSCR 0x04008048 +wm 32 MX6_MMDC_P0_MDREF 0x00007800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 diff --git a/arch/arm/boards/technexion-pico-hobbit/Makefile b/arch/arm/boards/technexion-pico-hobbit/Makefile index b60dcd2bc1..02e17035a0 100644 --- a/arch/arm/boards/technexion-pico-hobbit/Makefile +++ b/arch/arm/boards/technexion-pico-hobbit/Makefile @@ -1,7 +1,3 @@ obj-y += board.o lwl-y += lowlevel.o -extra-y += flash-header-imx6ul-pico-hobbit-256.dcd.S \ - flash-header-imx6ul-pico-hobbit-256.dcd \ - flash-header-imx6ul-pico-hobbit-512.dcd.S \ - flash-header-imx6ul-pico-hobbit-512.dcd bbenv-y += defaultenv-pico-hobbit diff --git a/arch/arm/boards/technexion-wandboard/Makefile b/arch/arm/boards/technexion-wandboard/Makefile index 8fc428c80a..01c7a259e9 100644 --- a/arch/arm/boards/technexion-wandboard/Makefile +++ b/arch/arm/boards/technexion-wandboard/Makefile @@ -1,3 +1,2 @@ -obj-y += board.o flash-header-technexion-wandboard.dcd.o -extra-y += flash-header-technexion-wandboard.dcd.S flash-header-technexion-wandboard.dcd +obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/tqma6x/Makefile b/arch/arm/boards/tqma6x/Makefile index f250e5977c..01c7a259e9 100644 --- a/arch/arm/boards/tqma6x/Makefile +++ b/arch/arm/boards/tqma6x/Makefile @@ -1,5 +1,2 @@ obj-y += board.o -obj-y += flash-header-tqma6q.dcd.o flash-header-tqma6dl.dcd.o -extra-y += flash-header-tqma6q.dcd.S flash-header-tqma6dl.dcd.S -extra-y += flash-header-tqma6q.dcd flash-header-tqma6dl.dcd lwl-y += lowlevel.o diff --git a/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg b/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg index 614b7a3da0..192ebda743 100644 --- a/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg +++ b/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg @@ -1,92 +1,96 @@ soc imx6 loadaddr 0x20000000 dcdofs 0x400 -wm 32 0x020e04bc 0x00000030 -wm 32 0x020e04c0 0x00000030 -wm 32 0x020e04c4 0x00000030 -wm 32 0x020e04c8 0x00000030 -wm 32 0x020e04cc 0x00000030 -wm 32 0x020e04d0 0x00000030 -wm 32 0x020e04d4 0x00000030 -wm 32 0x020e04d8 0x00000030 -wm 32 0x020e0764 0x00000030 -wm 32 0x020e0770 0x00000030 -wm 32 0x020e0778 0x00000030 -wm 32 0x020e077c 0x00000030 -wm 32 0x020e0780 0x00000030 -wm 32 0x020e0784 0x00000030 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0748 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e076c 0x00000030 -wm 32 0x020e0470 0x00020030 -wm 32 0x020e0474 0x00020030 -wm 32 0x020e0478 0x00020030 -wm 32 0x020e047c 0x00020030 -wm 32 0x020e0480 0x00020030 -wm 32 0x020e0484 0x00020030 -wm 32 0x020e0488 0x00020030 -wm 32 0x020e048c 0x00020030 -wm 32 0x020e0464 0x00020030 -wm 32 0x020e0490 0x00020030 -wm 32 0x020e04ac 0x00020030 -wm 32 0x020e04b0 0x00020030 -wm 32 0x020e0494 0x000e0030 -wm 32 0x020e04a4 0x00003000 -wm 32 0x020e04a8 0x00003000 -wm 32 0x020e04b4 0x00003030 -wm 32 0x020e04b8 0x00003030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e0760 0x00020000 -wm 32 0x020e0754 0x00000000 -wm 32 0x020e04a0 0x00000000 -wm 32 0x020e0774 0x000C0000 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b0018 0x00081740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b0004 0x0002002D -wm 32 0x021b000c 0x40435323 -wm 32 0x021b0010 0xB66E8D63 -wm 32 0x021b0014 0x01FF00DB -wm 32 0x021b002c 0x000026D2 -wm 32 0x021b0030 0x00431023 -wm 32 0x021b0008 0x00333030 -wm 32 0x021b0004 0x0002556D -wm 32 0x021b0040 0x00000017 -wm 32 0x021b0000 0x83190000 -wm 32 0x021b001c 0x04008032 -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x00048031 -wm 32 0x021b001c 0x13208030 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b0800 0xA1390003 -wm 32 0x021b4800 0xA1390003 -wm 32 0x021b0020 0x00005800 -wm 32 0x021b0818 0x00022227 -wm 32 0x021b4818 0x00022227 -wm 32 0x021b083c 0x42350231 -wm 32 0x021b483c 0x42350231 -wm 32 0x021b0840 0x021A0218 -wm 32 0x021b4840 0x021A0218 -wm 32 0x021b0848 0x4B4B4E49 -wm 32 0x021b4848 0x4B4B4E49 -wm 32 0x021b0850 0x3F3F3035 -wm 32 0x021b4850 0x3F3F3035 -wm 32 0x021b080c 0x0040003C -wm 32 0x021b0810 0x0032003E -wm 32 0x021b480c 0x0040003C -wm 32 0x021b4810 0x0032003E -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b001c 0x00000000 -wm 32 0x021b0404 0x00011006 + +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6dl-ddr-regs.h> + +wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 +wm 32 MX6_IOM_GRP_B0DS 0x00000030 +wm 32 MX6_IOM_GRP_B1DS 0x00000030 +wm 32 MX6_IOM_GRP_B2DS 0x00000030 +wm 32 MX6_IOM_GRP_B3DS 0x00000030 +wm 32 MX6_IOM_GRP_B4DS 0x00000030 +wm 32 MX6_IOM_GRP_B5DS 0x00000030 +wm 32 MX6_IOM_GRP_B6DS 0x00000030 +wm 32 MX6_IOM_GRP_B7DS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 +wm 32 MX6_IOM_DRAM_DQM0 0x00020030 +wm 32 MX6_IOM_DRAM_DQM1 0x00020030 +wm 32 MX6_IOM_DRAM_DQM2 0x00020030 +wm 32 MX6_IOM_DRAM_DQM3 0x00020030 +wm 32 MX6_IOM_DRAM_DQM4 0x00020030 +wm 32 MX6_IOM_DRAM_DQM5 0x00020030 +wm 32 MX6_IOM_DRAM_DQM6 0x00020030 +wm 32 MX6_IOM_DRAM_DQM7 0x00020030 +wm 32 MX6_IOM_DRAM_CAS 0x00020030 +wm 32 MX6_IOM_DRAM_RAS 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00020030 +wm 32 MX6_IOM_DRAM_RESET 0x000e0030 +wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000 +wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00003030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00003030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MDMISC 0x00081740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDPDC 0x0002002D +wm 32 MX6_MMDC_P0_MDCFG0 0x40435323 +wm 32 MX6_MMDC_P0_MDCFG1 0xB66E8D63 +wm 32 MX6_MMDC_P0_MDCFG2 0x01FF00DB +wm 32 MX6_MMDC_P0_MDRWD 0x000026D2 +wm 32 MX6_MMDC_P0_MDOR 0x00431023 +wm 32 MX6_MMDC_P0_MDOTC 0x00333030 +wm 32 MX6_MMDC_P0_MDPDC 0x0002556D +wm 32 MX6_MMDC_P0_MDASP 0x00000017 +wm 32 MX6_MMDC_P0_MDCTL 0x83190000 +wm 32 MX6_MMDC_P0_MDSCR 0x04008032 +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x00048031 +wm 32 MX6_MMDC_P0_MDSCR 0x13208030 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1390003 +wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xA1390003 +wm 32 MX6_MMDC_P0_MDREF 0x00005800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00022227 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00022227 +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x42350231 +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x42350231 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x021A0218 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x021A0218 +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x4B4B4E49 +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x4B4B4E49 +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x3F3F3035 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x3F3F3035 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x0040003C +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x0032003E +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x0040003C +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x0032003E +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 wm 32 0x020C4068 0x00C03F3F wm 32 0x020C406c 0x0030FC03 wm 32 0x020C4070 0x0FFFC000 diff --git a/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg b/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg index 4319776645..1fd75a24b2 100644 --- a/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg +++ b/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg @@ -2,96 +2,99 @@ soc imx6 loadaddr 0x20000000 dcdofs 0x400 -wm 32 0x020e05a8 0x00000030 -wm 32 0x020e05b0 0x00000030 -wm 32 0x020e0524 0x00000030 -wm 32 0x020e051c 0x00000030 -wm 32 0x020e0518 0x00000030 -wm 32 0x020e050c 0x00000030 -wm 32 0x020e05b8 0x00000030 -wm 32 0x020e05c0 0x00000030 -wm 32 0x020e05ac 0x00020030 -wm 32 0x020e05b4 0x00020030 -wm 32 0x020e0528 0x00020030 -wm 32 0x020e0520 0x00020030 -wm 32 0x020e0514 0x00020030 -wm 32 0x020e0510 0x00020030 -wm 32 0x020e05bc 0x00020030 -wm 32 0x020e05c4 0x00020030 -wm 32 0x020e056c 0x00020030 -wm 32 0x020e0578 0x00020030 -wm 32 0x020e0588 0x00020030 -wm 32 0x020e0594 0x00020030 -wm 32 0x020e057c 0x00020030 -wm 32 0x020e0590 0x00003000 -wm 32 0x020e0598 0x00003000 -wm 32 0x020e058c 0x00000000 -wm 32 0x020e059c 0x00003030 -wm 32 0x020e05a0 0x00003030 -wm 32 0x020e0784 0x00000030 -wm 32 0x020e0788 0x00000030 -wm 32 0x020e0794 0x00000030 -wm 32 0x020e079c 0x00000030 -wm 32 0x020e07a0 0x00000030 -wm 32 0x020e07a4 0x00000030 -wm 32 0x020e07a8 0x00000030 -wm 32 0x020e0748 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e0758 0x00000000 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0798 0x000c0000 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b0018 0x00081740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b000c 0x555a7974 -wm 32 0x021b0010 0xdb538f64 -wm 32 0x021b0014 0x01ff00db -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x005a1023 -wm 32 0x021b0008 0x09444040 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0040 0x00000027 -wm 32 0x021b0000 0x831a0000 -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x0408803a -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x0000803b -wm 32 0x021b001c 0x00428031 -wm 32 0x021b001c 0x00428039 -wm 32 0x021b001c 0x19308030 -wm 32 0x021b001c 0x19308038 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b001c 0x04008048 -wm 32 0x021b0800 0xa1380003 -wm 32 0x021b4800 0xa1380003 -wm 32 0x021b0020 0x00005800 -wm 32 0x021b0818 0x00022227 -wm 32 0x021b4818 0x00022227 -wm 32 0x021b083c 0x434b0350 -wm 32 0x021b0840 0x034c0359 -wm 32 0x021b483c 0x434b0350 -wm 32 0x021b4840 0x03650348 -wm 32 0x021b0848 0x4436383b -wm 32 0x021b4848 0x39393341 -wm 32 0x021b0850 0x35373933 -wm 32 0x021b4850 0x48254a36 -wm 32 0x021b080c 0x001f001f -wm 32 0x021b0810 0x001f001f -wm 32 0x021b480c 0x00440044 -wm 32 0x021b4810 0x00440044 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b001c 0x00000000 -wm 32 0x021b0404 0x00011006 +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6q-ddr-regs.h> + +wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 +wm 32 MX6_IOM_DRAM_DQM0 0x00020030 +wm 32 MX6_IOM_DRAM_DQM1 0x00020030 +wm 32 MX6_IOM_DRAM_DQM2 0x00020030 +wm 32 MX6_IOM_DRAM_DQM3 0x00020030 +wm 32 MX6_IOM_DRAM_DQM4 0x00020030 +wm 32 MX6_IOM_DRAM_DQM5 0x00020030 +wm 32 MX6_IOM_DRAM_DQM6 0x00020030 +wm 32 MX6_IOM_DRAM_DQM7 0x00020030 +wm 32 MX6_IOM_DRAM_CAS 0x00020030 +wm 32 MX6_IOM_DRAM_RAS 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00020030 +wm 32 MX6_IOM_DRAM_RESET 0x00020030 +wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000 +wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00003030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00003030 +wm 32 MX6_IOM_GRP_B0DS 0x00000030 +wm 32 MX6_IOM_GRP_B1DS 0x00000030 +wm 32 MX6_IOM_GRP_B2DS 0x00000030 +wm 32 MX6_IOM_GRP_B3DS 0x00000030 +wm 32 MX6_IOM_GRP_B4DS 0x00000030 +wm 32 MX6_IOM_GRP_B5DS 0x00000030 +wm 32 MX6_IOM_GRP_B6DS 0x00000030 +wm 32 MX6_IOM_GRP_B7DS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MDMISC 0x00081740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDCFG0 0x555a7974 +wm 32 MX6_MMDC_P0_MDCFG1 0xdb538f64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x005a1023 +wm 32 MX6_MMDC_P0_MDOTC 0x09444040 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MDASP 0x00000027 +wm 32 MX6_MMDC_P0_MDCTL 0x831a0000 +wm 32 MX6_MMDC_P0_MDSCR 0x04088032 +wm 32 MX6_MMDC_P0_MDSCR 0x0408803a +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x0000803b +wm 32 MX6_MMDC_P0_MDSCR 0x00428031 +wm 32 MX6_MMDC_P0_MDSCR 0x00428039 +wm 32 MX6_MMDC_P0_MDSCR 0x19308030 +wm 32 MX6_MMDC_P0_MDSCR 0x19308038 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDSCR 0x04008048 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380003 +wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1380003 +wm 32 MX6_MMDC_P0_MDREF 0x00005800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00022227 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00022227 +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x434b0350 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x034c0359 +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x434b0350 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x03650348 +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x4436383b +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x39393341 +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x35373933 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x48254a36 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001f001f +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001f001f +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x00440044 +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x00440044 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 wm 32 0x020c4068 0x00c03f3f wm 32 0x020c406c 0x0030fc03 wm 32 0x020c4070 0x0fffc000 diff --git a/arch/arm/boards/udoo/Makefile b/arch/arm/boards/udoo/Makefile index ae17789b8f..01c7a259e9 100644 --- a/arch/arm/boards/udoo/Makefile +++ b/arch/arm/boards/udoo/Makefile @@ -1,3 +1,2 @@ -obj-y += board.o flash-header-mx6-udoo.dcd.o -extra-y += flash-header-mx6-udoo.dcd.S flash-header-mx6-udoo.dcd +obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg b/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg index b142f59aab..a0647a71a8 100644 --- a/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg +++ b/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg @@ -2,103 +2,105 @@ soc imx6 loadaddr 0x20000000 dcdofs 0x400 +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6q-ddr-regs.h> /* MX6_IOM_DRAM_SDQS0 -> MX6_IOM_DRAM_SDQS7 */ -wm 32 0x020e05a8 0x00000030 -wm 32 0x020e05b0 0x00000030 -wm 32 0x020e0524 0x00000030 -wm 32 0x020e051c 0x00000030 -wm 32 0x020e0518 0x00000030 -wm 32 0x020e050c 0x00000030 -wm 32 0x020e05b8 0x00000030 -wm 32 0x020e05c0 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 /********************************************/ /* MX6_IOM_DRAM_DQM0 -> MX6_IOM_DRAM_DQM7 */ -wm 32 0x020e05ac 0x00020030 -wm 32 0x020e05b4 0x00020030 -wm 32 0x020e0528 0x00020030 -wm 32 0x020e0520 0x00020030 -wm 32 0x020e0514 0x00020030 -wm 32 0x020e0510 0x00020030 -wm 32 0x020e05bc 0x00020030 -wm 32 0x020e05c4 0x00020030 +wm 32 MX6_IOM_DRAM_DQM0 0x00020030 +wm 32 MX6_IOM_DRAM_DQM1 0x00020030 +wm 32 MX6_IOM_DRAM_DQM2 0x00020030 +wm 32 MX6_IOM_DRAM_DQM3 0x00020030 +wm 32 MX6_IOM_DRAM_DQM4 0x00020030 +wm 32 MX6_IOM_DRAM_DQM5 0x00020030 +wm 32 MX6_IOM_DRAM_DQM6 0x00020030 +wm 32 MX6_IOM_DRAM_DQM7 0x00020030 /******************************************/ -wm 32 0x020e056c 0x00020030 /* MX6_IOM_DRAM_CAS */ -wm 32 0x020e0578 0x00020030 /* MX6_IOM_DRAM_RAS */ -wm 32 0x020e0588 0x00020030 /* MX6_IOM_DRAM_SDCLK_0 */ -wm 32 0x020e0594 0x00020030 /* MX6_IOM_DRAM_SDCLK_1 */ -wm 32 0x020e057c 0x00020030 /* MX6_IOM_DRAM_RESET */ -wm 32 0x020e0590 0x00003000 -wm 32 0x020e0598 0x00003000 -wm 32 0x020e058c 0x00000000 -wm 32 0x020e059c 0x00003030 -wm 32 0x020e05a0 0x00003030 +wm 32 MX6_IOM_DRAM_CAS 0x00020030 /* MX6_IOM_DRAM_CAS */ +wm 32 MX6_IOM_DRAM_RAS 0x00020030 /* MX6_IOM_DRAM_RAS */ +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00020030 /* MX6_IOM_DRAM_SDCLK_0 */ +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00020030 /* MX6_IOM_DRAM_SDCLK_1 */ +wm 32 MX6_IOM_DRAM_RESET 0x00020030 /* MX6_IOM_DRAM_RESET */ +wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000 +wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00003030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00003030 /* MX6_IOM_GRP_B0DS -> MX6_IOM_GRP_B7DS */ -wm 32 0x020e0784 0x00000030 -wm 32 0x020e0788 0x00000030 -wm 32 0x020e0794 0x00000030 -wm 32 0x020e079c 0x00000030 -wm 32 0x020e07a0 0x00000030 -wm 32 0x020e07a4 0x00000030 -wm 32 0x020e07a8 0x00000030 -wm 32 0x020e0748 0x00000030 +wm 32 MX6_IOM_GRP_B0DS 0x00000030 +wm 32 MX6_IOM_GRP_B1DS 0x00000030 +wm 32 MX6_IOM_GRP_B2DS 0x00000030 +wm 32 MX6_IOM_GRP_B3DS 0x00000030 +wm 32 MX6_IOM_GRP_B4DS 0x00000030 +wm 32 MX6_IOM_GRP_B5DS 0x00000030 +wm 32 MX6_IOM_GRP_B6DS 0x00000030 +wm 32 MX6_IOM_GRP_B7DS 0x00000030 /***************************************/ -wm 32 0x020e074c 0x00000030 /* MX6_IOM_GRP_ADDDS */ -wm 32 0x020e0750 0x00020000 -wm 32 0x020e0758 0x00000000 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e078c 0x00000030 /* MX6_IOM_GRP_CTLDS */ -wm 32 0x020e0798 0x000c0000 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 /* MX6_IOM_GRP_ADDDS */ +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 /* MX6_IOM_GRP_CTLDS */ +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 -wm 32 0x021b0004 0x00020036 -wm 32 0x021b0008 0x09444040 -wm 32 0x021b000c 0x54597955 -wm 32 0x021b0010 0xFF328F64 -wm 32 0x021b0014 0x01FF00DB -wm 32 0x021b0018 0x00001740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b002c 0x000026D2 -wm 32 0x021b0030 0x00591023 -wm 32 0x021b0040 0x00000027 -wm 32 0x021b0000 0x831A0000 -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x00048031 -wm 32 0x021b001c 0x09408030 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b0800 0xA1380003 -wm 32 0x021b4800 0xA1380003 -wm 32 0x021b0020 0x00005800 -wm 32 0x021b0818 0x00011117 -wm 32 0x021b4818 0x00011117 -wm 32 0x021b083c 0x43510360 -wm 32 0x021b0840 0x0342033F -wm 32 0x021b483c 0x033F033F -wm 32 0x021b4840 0x03290266 -wm 32 0x021b0848 0x4B3E4141 -wm 32 0x021b4848 0x47413B4A -wm 32 0x021b0850 0x42404843 -wm 32 0x021b4850 0x4C3F4C45 -wm 32 0x021b080c 0x00350035 -wm 32 0x021b0810 0x001F001F -wm 32 0x021b480c 0x00010001 -wm 32 0x021b4810 0x00010001 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0404 0x00011006 -wm 32 0x021b001c 0x00000000 +wm 32 MX6_MMDC_P0_MDPDC 0x00020036 +wm 32 MX6_MMDC_P0_MDOTC 0x09444040 +wm 32 MX6_MMDC_P0_MDCFG0 0x54597955 +wm 32 MX6_MMDC_P0_MDCFG1 0xFF328F64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01FF00DB +wm 32 MX6_MMDC_P0_MDMISC 0x00001740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDRWD 0x000026D2 +wm 32 MX6_MMDC_P0_MDOR 0x00591023 +wm 32 MX6_MMDC_P0_MDASP 0x00000027 +wm 32 MX6_MMDC_P0_MDCTL 0x831A0000 +wm 32 MX6_MMDC_P0_MDSCR 0x04088032 +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x00048031 +wm 32 MX6_MMDC_P0_MDSCR 0x09408030 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1380003 +wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xA1380003 +wm 32 MX6_MMDC_P0_MDREF 0x00005800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x43510360 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x0342033F +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x033F033F +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x03290266 +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x4B3E4141 +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x47413B4A +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x42404843 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x4C3F4C45 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x00350035 +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001F001F +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x00010001 +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x00010001 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 diff --git a/arch/arm/boards/variscite-mx6/Makefile b/arch/arm/boards/variscite-mx6/Makefile index 35b114b8dd..01c7a259e9 100644 --- a/arch/arm/boards/variscite-mx6/Makefile +++ b/arch/arm/boards/variscite-mx6/Makefile @@ -1,3 +1,2 @@ -obj-y += board.o flash-header-variscite.dcd.o -extra-y += flash-header-variscite.dcd.S flash-header-variscite.dcd +obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg b/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg index ed2105792e..2c82f2316f 100644 --- a/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg +++ b/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg @@ -1,86 +1,90 @@ loadaddr 0x10000000 soc imx6 dcdofs 0x400 -wm 32 0x020e0798 0x000C0000 -wm 32 0x020e0758 0x00000000 -wm 32 0x020e0588 0x00000030 -wm 32 0x020e0594 0x00000030 -wm 32 0x020e056c 0x00000030 -wm 32 0x020e0578 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e057c 0x00000030 -wm 32 0x020e058c 0x00000000 -wm 32 0x020e059c 0x00000030 -wm 32 0x020e05a0 0x00000030 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e05a8 0x00000030 -wm 32 0x020e05b0 0x00000030 -wm 32 0x020e0524 0x00000030 -wm 32 0x020e051c 0x00000030 -wm 32 0x020e0518 0x00000030 -wm 32 0x020e050c 0x00000030 -wm 32 0x020e05b8 0x00000030 -wm 32 0x020e05c0 0x00000030 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e0784 0x00000030 -wm 32 0x020e0788 0x00000030 -wm 32 0x020e0794 0x00000030 -wm 32 0x020e079c 0x00000030 -wm 32 0x020e07a0 0x00000030 -wm 32 0x020e07a4 0x00000030 -wm 32 0x020e07a8 0x00000030 -wm 32 0x020e0748 0x00000030 -wm 32 0x020e05ac 0x00000030 -wm 32 0x020e05b4 0x00000030 -wm 32 0x020e0528 0x00000030 -wm 32 0x020e0520 0x00000030 -wm 32 0x020e0514 0x00000030 -wm 32 0x020e0510 0x00000030 -wm 32 0x020e05bc 0x00000030 -wm 32 0x020e05c4 0x00000030 -wm 32 0x021b0800 0xA1390003 -wm 32 0x021b080c 0x001F001F -wm 32 0x021b0810 0x001F001F -wm 32 0x021b480c 0x001F001F -wm 32 0x021b4810 0x001F001F -wm 32 0x021b083c 0x4333033F -wm 32 0x021b0840 0x032C031D -wm 32 0x021b483c 0x43200332 -wm 32 0x021b4840 0x031A026A -wm 32 0x021b0848 0x4D464746 -wm 32 0x021b4848 0x47453F4D -wm 32 0x021b0850 0x3E434440 -wm 32 0x021b4850 0x47384839 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b0004 0x00020036 -wm 32 0x021b0008 0x09444040 -wm 32 0x021b000c 0x555A7975 -wm 32 0x021b0010 0xFF538F64 -wm 32 0x021b0014 0x01FF00DB -wm 32 0x021b0018 0x00001740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b002c 0x000026D2 -wm 32 0x021b0030 0x005A1023 -wm 32 0x021b0040 0x00000027 -wm 32 0x021b0000 0x831A0000 -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x00048031 -wm 32 0x021b001c 0x09408030 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b0020 0x00005800 -wm 32 0x021b0818 0x00011117 -wm 32 0x021b4818 0x00011117 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0404 0x00011006 -wm 32 0x021b001c 0x00000000 + +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6q-ddr-regs.h> + +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00000030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00000030 +wm 32 MX6_IOM_DRAM_CAS 0x00000030 +wm 32 MX6_IOM_DRAM_RAS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_DRAM_RESET 0x00000030 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00000030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00000030 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_B0DS 0x00000030 +wm 32 MX6_IOM_GRP_B1DS 0x00000030 +wm 32 MX6_IOM_GRP_B2DS 0x00000030 +wm 32 MX6_IOM_GRP_B3DS 0x00000030 +wm 32 MX6_IOM_GRP_B4DS 0x00000030 +wm 32 MX6_IOM_GRP_B5DS 0x00000030 +wm 32 MX6_IOM_GRP_B6DS 0x00000030 +wm 32 MX6_IOM_GRP_B7DS 0x00000030 +wm 32 MX6_IOM_DRAM_DQM0 0x00000030 +wm 32 MX6_IOM_DRAM_DQM1 0x00000030 +wm 32 MX6_IOM_DRAM_DQM2 0x00000030 +wm 32 MX6_IOM_DRAM_DQM3 0x00000030 +wm 32 MX6_IOM_DRAM_DQM4 0x00000030 +wm 32 MX6_IOM_DRAM_DQM5 0x00000030 +wm 32 MX6_IOM_DRAM_DQM6 0x00000030 +wm 32 MX6_IOM_DRAM_DQM7 0x00000030 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1390003 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001F001F +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001F001F +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x001F001F +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x001F001F +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x4333033F +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x032C031D +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x43200332 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x031A026A +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x4D464746 +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x47453F4D +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x3E434440 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x47384839 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDPDC 0x00020036 +wm 32 MX6_MMDC_P0_MDOTC 0x09444040 +wm 32 MX6_MMDC_P0_MDCFG0 0x555A7975 +wm 32 MX6_MMDC_P0_MDCFG1 0xFF538F64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01FF00DB +wm 32 MX6_MMDC_P0_MDMISC 0x00001740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDRWD 0x000026D2 +wm 32 MX6_MMDC_P0_MDOR 0x005A1023 +wm 32 MX6_MMDC_P0_MDASP 0x00000027 +wm 32 MX6_MMDC_P0_MDCTL 0x831A0000 +wm 32 MX6_MMDC_P0_MDSCR 0x04088032 +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x00048031 +wm 32 MX6_MMDC_P0_MDSCR 0x09408030 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDREF 0x00005800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 diff --git a/arch/arm/boards/zii-imx6q-rdu2/Makefile b/arch/arm/boards/zii-imx6q-rdu2/Makefile index 01c7a259e9..c6285362f2 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/Makefile +++ b/arch/arm/boards/zii-imx6q-rdu2/Makefile @@ -1,2 +1,3 @@ obj-y += board.o lwl-y += lowlevel.o +bbenv-y += defaultenv-rdu2 diff --git a/arch/arm/boards/zii-imx6q-rdu2/board.c b/arch/arm/boards/zii-imx6q-rdu2/board.c index ee04517d29..265f97e2f4 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/board.c +++ b/arch/arm/boards/zii-imx6q-rdu2/board.c @@ -14,26 +14,11 @@ */ #include <common.h> -#include <init.h> -#include <environment.h> -#include <mach/imx6-regs.h> +#include <envfs.h> #include <gpio.h> -#include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> -#include <linux/phy.h> -#include <asm/io.h> -#include <asm/mmu.h> -#include <mach/generic.h> -#include <linux/sizes.h> -#include <net.h> -#include <mach/imx6.h> -#include <mach/devices-imx6.h> -#include <mach/iomux-mx6.h> -#include <spi/spi.h> -#include <mach/spi.h> -#include <mach/usb.h> +#include <init.h> #include <mach/bbu.h> +#include <mach/imx6.h> #define RDU2_DAC1_RESET IMX_GPIO_NR(1, 0) #define RDU2_DAC2_RESET IMX_GPIO_NR(1, 2) @@ -122,11 +107,6 @@ static const struct gpio rdu2_front_panel_usb_gpios[] = { .label = "usb-mode1", }, { - .gpio = IMX_GPIO_NR(3, 22), - .flags = GPIOF_OUT_INIT_LOW, - .label = "usb-pwr-ctrl-enn", - }, - { .gpio = IMX_GPIO_NR(3, 23), .flags = GPIOF_OUT_INIT_HIGH, .label = "usb-mode2", @@ -166,6 +146,8 @@ static int rdu2_devices_init(void) imx6_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc3", 0); + defaultenv_append_directory(defaultenv_rdu2); + return 0; } device_initcall(rdu2_devices_init); diff --git a/arch/arm/boards/zii-imx6q-rdu2/flash-header-imx6q-rdu2.imxcfg b/arch/arm/boards/zii-imx6q-rdu2/flash-header-imx6q-rdu2.imxcfg index e37db503b4..3ab35e4304 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/flash-header-imx6q-rdu2.imxcfg +++ b/arch/arm/boards/zii-imx6q-rdu2/flash-header-imx6q-rdu2.imxcfg @@ -2,86 +2,89 @@ loadaddr 0x10000000 soc imx6 dcdofs 0x400 -wm 32 0x020e0798 0x000C0000 -wm 32 0x020e0758 0x00000000 -wm 32 0x020e0588 0x00000030 -wm 32 0x020e0594 0x00000030 -wm 32 0x020e056c 0x00000030 -wm 32 0x020e0578 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e057c 0x00000030 -wm 32 0x020e058c 0x00000000 -wm 32 0x020e059c 0x00000030 -wm 32 0x020e05a0 0x00000030 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e05a8 0x00000028 -wm 32 0x020e05b0 0x00000028 -wm 32 0x020e0524 0x00000028 -wm 32 0x020e051c 0x00000028 -wm 32 0x020e0518 0x00000028 -wm 32 0x020e050c 0x00000028 -wm 32 0x020e05b8 0x00000028 -wm 32 0x020e05c0 0x00000028 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e0784 0x00000028 -wm 32 0x020e0788 0x00000028 -wm 32 0x020e0794 0x00000028 -wm 32 0x020e079c 0x00000028 -wm 32 0x020e07a0 0x00000028 -wm 32 0x020e07a4 0x00000028 -wm 32 0x020e07a8 0x00000028 -wm 32 0x020e0748 0x00000028 -wm 32 0x020e05ac 0x00000028 -wm 32 0x020e05b4 0x00000028 -wm 32 0x020e0528 0x00000028 -wm 32 0x020e0520 0x00000028 -wm 32 0x020e0514 0x00000028 -wm 32 0x020e0510 0x00000028 -wm 32 0x020e05bc 0x00000028 -wm 32 0x020e05c4 0x00000028 -wm 32 0x021b0800 0xa1390003 -wm 32 0x021b080c 0x001F001F -wm 32 0x021b0810 0x001F001F -wm 32 0x021b480c 0x001F001F -wm 32 0x021b4810 0x001F001F -wm 32 0x021b083c 0x43260335 -wm 32 0x021b0840 0x031A030B -wm 32 0x021b483c 0x4323033B -wm 32 0x021b4840 0x0323026F -wm 32 0x021b0848 0x483D4545 -wm 32 0x021b4848 0x44433E48 -wm 32 0x021b0850 0x41444840 -wm 32 0x021b4850 0x4835483E -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b0004 0x00020036 -wm 32 0x021b0008 0x09444040 -wm 32 0x021b000c 0x8A8F7955 -wm 32 0x021b0010 0xFF328F64 -wm 32 0x021b0014 0x01FF00DB -wm 32 0x021b0018 0x00001740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x008F1023 -wm 32 0x021b0040 0x00000047 -wm 32 0x021b0000 0x841A0000 -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x00048031 -wm 32 0x021b001c 0x09408030 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b0020 0x00005800 -wm 32 0x021b0818 0x00011117 -wm 32 0x021b4818 0x00011117 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0404 0x00011006 -wm 32 0x021b001c 0x00000000 +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6q-ddr-regs.h> + +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00000030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00000030 +wm 32 MX6_IOM_DRAM_CAS 0x00000030 +wm 32 MX6_IOM_DRAM_RAS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_DRAM_RESET 0x00000030 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00000030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00000030 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_DRAM_SDQS0 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000028 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_B0DS 0x00000028 +wm 32 MX6_IOM_GRP_B1DS 0x00000028 +wm 32 MX6_IOM_GRP_B2DS 0x00000028 +wm 32 MX6_IOM_GRP_B3DS 0x00000028 +wm 32 MX6_IOM_GRP_B4DS 0x00000028 +wm 32 MX6_IOM_GRP_B5DS 0x00000028 +wm 32 MX6_IOM_GRP_B6DS 0x00000028 +wm 32 MX6_IOM_GRP_B7DS 0x00000028 +wm 32 MX6_IOM_DRAM_DQM0 0x00000028 +wm 32 MX6_IOM_DRAM_DQM1 0x00000028 +wm 32 MX6_IOM_DRAM_DQM2 0x00000028 +wm 32 MX6_IOM_DRAM_DQM3 0x00000028 +wm 32 MX6_IOM_DRAM_DQM4 0x00000028 +wm 32 MX6_IOM_DRAM_DQM5 0x00000028 +wm 32 MX6_IOM_DRAM_DQM6 0x00000028 +wm 32 MX6_IOM_DRAM_DQM7 0x00000028 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001F001F +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001F001F +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x001F001F +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x001F001F +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x43260335 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x031A030B +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x4323033B +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x0323026F +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x483D4545 +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x44433E48 +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x41444840 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x4835483E +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDPDC 0x00020036 +wm 32 MX6_MMDC_P0_MDOTC 0x09444040 +wm 32 MX6_MMDC_P0_MDCFG0 0x8A8F7955 +wm 32 MX6_MMDC_P0_MDCFG1 0xFF328F64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01FF00DB +wm 32 MX6_MMDC_P0_MDMISC 0x00001740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x008F1023 +wm 32 MX6_MMDC_P0_MDASP 0x00000047 +wm 32 MX6_MMDC_P0_MDCTL 0x841A0000 +wm 32 MX6_MMDC_P0_MDSCR 0x04088032 +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x00048031 +wm 32 MX6_MMDC_P0_MDSCR 0x09408030 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDREF 0x00005800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00011117 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 diff --git a/arch/arm/boards/zii-imx6q-rdu2/flash-header-imx6qp-rdu2.imxcfg b/arch/arm/boards/zii-imx6q-rdu2/flash-header-imx6qp-rdu2.imxcfg index 03e764b3b3..e99ab19fdf 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/flash-header-imx6qp-rdu2.imxcfg +++ b/arch/arm/boards/zii-imx6q-rdu2/flash-header-imx6qp-rdu2.imxcfg @@ -2,31 +2,34 @@ loadaddr 0x10000000 soc imx6 dcdofs 0x400 -wm 32 0x020e0798 0x000C0000 -wm 32 0x020e0758 0x00000000 - -wm 32 0x020e0588 0x00020030 -wm 32 0x020e0594 0x00020030 - -wm 32 0x020e056c 0x00020030 -wm 32 0x020e0578 0x00020030 -wm 32 0x020e074c 0x00020030 - -wm 32 0x020e057c 0x00020030 -wm 32 0x020e058c 0x00000000 -wm 32 0x020e059c 0x00020030 -wm 32 0x020e05a0 0x00020030 -wm 32 0x020e078c 0x00020030 - -wm 32 0x020e0750 0x00020000 -wm 32 0x020e05a8 0x00020030 -wm 32 0x020e05b0 0x00020030 -wm 32 0x020e0524 0x00020030 -wm 32 0x020e051c 0x00020030 -wm 32 0x020e0518 0x00020030 -wm 32 0x020e050c 0x00020030 -wm 32 0x020e05b8 0x00020030 -wm 32 0x020e05c0 0x00020030 +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6q-ddr-regs.h> + +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 + +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00020030 + +wm 32 MX6_IOM_DRAM_CAS 0x00020030 +wm 32 MX6_IOM_DRAM_RAS 0x00020030 +wm 32 MX6_IOM_GRP_ADDDS 0x00020030 + +wm 32 MX6_IOM_DRAM_RESET 0x00020030 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00020030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00020030 +wm 32 MX6_IOM_GRP_CTLDS 0x00020030 + +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_DRAM_SDQS0 0x00020030 +wm 32 MX6_IOM_DRAM_SDQS1 0x00020030 +wm 32 MX6_IOM_DRAM_SDQS2 0x00020030 +wm 32 MX6_IOM_DRAM_SDQS3 0x00020030 +wm 32 MX6_IOM_DRAM_SDQS4 0x00020030 +wm 32 MX6_IOM_DRAM_SDQS5 0x00020030 +wm 32 MX6_IOM_DRAM_SDQS6 0x00020030 +wm 32 MX6_IOM_DRAM_SDQS7 0x00020030 wm 32 0x020e0534 0x00018200 wm 32 0x020e0538 0x00008000 @@ -37,75 +40,75 @@ wm 32 0x020e0548 0x00018200 wm 32 0x020e054c 0x00018200 wm 32 0x020e0550 0x00018200 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e0784 0x00020030 -wm 32 0x020e0788 0x00020030 -wm 32 0x020e0794 0x00020030 -wm 32 0x020e079c 0x00020030 -wm 32 0x020e07a0 0x00020030 -wm 32 0x020e07a4 0x00020030 -wm 32 0x020e07a8 0x00020030 -wm 32 0x020e0748 0x00020030 - -wm 32 0x020e05ac 0x00020030 -wm 32 0x020e05b4 0x00020030 -wm 32 0x020e0528 0x00020030 -wm 32 0x020e0520 0x00020030 -wm 32 0x020e0514 0x00020030 -wm 32 0x020e0510 0x00020030 -wm 32 0x020e05bc 0x00020030 -wm 32 0x020e05c4 0x00020030 - -wm 32 0x021b001c 0x00008000 - -wm 32 0x021b0800 0xA1390003 - -wm 32 0x021b080c 0x002A001F -wm 32 0x021b0810 0x002F002A -wm 32 0x021b480c 0x001F0031 -wm 32 0x021b4810 0x001B0022 - -wm 32 0x021b083c 0x433C0354 -wm 32 0x021b0840 0x03380330 -wm 32 0x021b483c 0x43440358 -wm 32 0x021b4840 0x03340300 - -wm 32 0x021b0848 0x483A4040 -wm 32 0x021b4848 0x3E383648 - -wm 32 0x021b0850 0x3C424048 -wm 32 0x021b4850 0x4C425042 - -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 - -wm 32 0x021b08c0 0x24912489 -wm 32 0x021b48c0 0x24914452 - -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 - -wm 32 0x021b0004 0x00020036 -wm 32 0x021b0008 0x09444040 -wm 32 0x021b000c 0x898E7955 -wm 32 0x021b0010 0xFF328F64 -wm 32 0x021b0014 0x01FF00DB - -wm 32 0x021b0018 0x00011740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b002c 0x000026D2 -wm 32 0x021b0030 0x008E1023 -wm 32 0x021b0040 0x00000047 - -wm 32 0x021b0400 0x14420000 -wm 32 0x021b0000 0x841A0000 -wm 32 0x021b0890 0x00400c58 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_B0DS 0x00020030 +wm 32 MX6_IOM_GRP_B1DS 0x00020030 +wm 32 MX6_IOM_GRP_B2DS 0x00020030 +wm 32 MX6_IOM_GRP_B3DS 0x00020030 +wm 32 MX6_IOM_GRP_B4DS 0x00020030 +wm 32 MX6_IOM_GRP_B5DS 0x00020030 +wm 32 MX6_IOM_GRP_B6DS 0x00020030 +wm 32 MX6_IOM_GRP_B7DS 0x00020030 + +wm 32 MX6_IOM_DRAM_DQM0 0x00020030 +wm 32 MX6_IOM_DRAM_DQM1 0x00020030 +wm 32 MX6_IOM_DRAM_DQM2 0x00020030 +wm 32 MX6_IOM_DRAM_DQM3 0x00020030 +wm 32 MX6_IOM_DRAM_DQM4 0x00020030 +wm 32 MX6_IOM_DRAM_DQM5 0x00020030 +wm 32 MX6_IOM_DRAM_DQM6 0x00020030 +wm 32 MX6_IOM_DRAM_DQM7 0x00020030 + +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 + +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1390003 + +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x002A001F +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x002F002A +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x001F0031 +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x001B0022 + +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x433C0354 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x03380330 +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x43440358 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x03340300 + +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x483A4040 +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x3E383648 + +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x3C424048 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x4C425042 + +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 + +wm 32 MX6_MMDC_P0_MPDCCR 0x24912489 +wm 32 MX6_MMDC_P1_MPDCCR 0x24914452 + +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 + +wm 32 MX6_MMDC_P0_MDPDC 0x00020036 +wm 32 MX6_MMDC_P0_MDOTC 0x09444040 +wm 32 MX6_MMDC_P0_MDCFG0 0x898E7955 +wm 32 MX6_MMDC_P0_MDCFG1 0xFF328F64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01FF00DB + +wm 32 MX6_MMDC_P0_MDMISC 0x00011740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDRWD 0x000026D2 +wm 32 MX6_MMDC_P0_MDOR 0x008E1023 +wm 32 MX6_MMDC_P0_MDASP 0x00000047 + +wm 32 MX6_MMDC_P0_MAARCR 0x14420000 +wm 32 MX6_MMDC_P0_MDCTL 0x841A0000 +wm 32 MX6_MMDC_P0_MPPDCMPR2 0x00400c58 wm 32 0x00bb0008 0x00000000 wm 32 0x00bb000c 0x2891E41A @@ -114,19 +117,19 @@ wm 32 0x00bb0014 0x00000040 wm 32 0x00bb0028 0x00000020 wm 32 0x00bb002c 0x00000020 -wm 32 0x021b001c 0x02088032 -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x00048031 -wm 32 0x021b001c 0x19408030 -wm 32 0x021b001c 0x04008040 +wm 32 MX6_MMDC_P0_MDSCR 0x02088032 +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x00048031 +wm 32 MX6_MMDC_P0_MDSCR 0x19408030 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 -wm 32 0x021b0020 0x00007800 +wm 32 MX6_MMDC_P0_MDREF 0x00007800 -wm 32 0x021b0818 0x00022227 -wm 32 0x021b4818 0x00022227 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00022227 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00022227 -wm 32 0x021b0004 0x00025576 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 -wm 32 0x021b0404 0x00011006 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 -wm 32 0x021b001c 0x00000000 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index 7bbd93240d..62d623806c 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -1,7 +1,7 @@ CONFIG_ARCH_IMX=y CONFIG_IMX_MULTI_BOARDS=y -CONFIG_MACH_EFIKA_MX_SMARTBOOK=y CONFIG_MACH_KINDLE_MX50=y +CONFIG_MACH_EFIKA_MX_SMARTBOOK=y CONFIG_MACH_EMBEDSKY_E9=y CONFIG_MACH_FREESCALE_MX51_PDK=y CONFIG_MACH_CCMX53=y @@ -30,12 +30,14 @@ CONFIG_MACH_UDOO=y CONFIG_MACH_VARISCITE_MX6=y CONFIG_MACH_GW_VENTANA=y CONFIG_MACH_CM_FX6=y +CONFIG_MACH_PHYTEC_PHYCORE_IMX7=y CONFIG_IMX_IIM=y CONFIG_IMX_IIM_FUSE_BLOW=y CONFIG_IMX_OCOTP=y CONFIG_THUMB2_BAREBOX=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_ARM_UNWIND=y +CONFIG_ARM_PSCI=y CONFIG_MMU=y CONFIG_TEXT_BASE=0x0 CONFIG_MALLOC_SIZE=0x0 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d8abe452b4..0ec03bc810 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -21,6 +21,7 @@ pbl-dtb-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o pbl-dtb-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o pbl-dtb-$(CONFIG_MACH_CCMX53) += imx53-ccxmx53.dtb.o pbl-dtb-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o +pbl-dtb-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += imx7d-sdb.dtb.o pbl-dtb-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o pbl-dtb-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += kirkwood-guruplug-server-plus-bb.dtb.o pbl-dtb-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += armada-370-mirabox-bb.dtb.o @@ -55,6 +56,7 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \ imx6dl-phytec-phycore-som-emmc.dtb.o \ imx6ul-phytec-phycore-som.dtb.o \ imx6ull-phytec-phycore-som.dtb.o +pbl-dtb-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o pbl-dtb-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o @@ -100,5 +102,4 @@ pbl-dtb-$(CONFIG_MACH_ZII_VF610_DEV) += \ pbl-dtb-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o - clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.lzo diff --git a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi index 5b255e9aaa..7586afe2fe 100644 --- a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2016 Zodiac Inflight Innovations + * Copyright (C) 2016-2017 Zodiac Inflight Innovations * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -7,9 +7,8 @@ * whole. * * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. * * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -30,7 +29,7 @@ * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT @@ -40,502 +39,121 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> +#include <arm/imx6qdl-zii-rdu2.dtsi> / { chosen { - linux,stdout-path = &uart1; - environment@0 { compatible = "barebox,environment"; device-path = &nor_flash, "partname:barebox-environment"; }; }; - mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mdio1>; - gpios = <&gpio6 5 GPIO_ACTIVE_HIGH - &gpio6 4 GPIO_ACTIVE_HIGH>; - }; - - reg_28p0v: 28p0v { - /* main power in */ - compatible = "regulator-fixed"; - regulator-name = "28P0V"; - regulator-min-microvolt = <28000000>; - regulator-max-microvolt = <28000000>; - regulator-always-on; - }; - - reg_12p0v: 12p0v { - /* main internal power */ - compatible = "regulator-fixed"; - vin-supply = <®_28p0v>; - regulator-name = "12P0V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - reg_12p0v_periph: 12p0vperiph { - compatible = "regulator-fixed"; - vin-supply = <®_28p0v>; - regulator-name = "12P0V-PERIPH"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - /* controlled via "environment processor" */ - regulator-always-on; - }; - - reg_5p0v_main: 5p0vmain { - compatible = "regulator-fixed"; - vin-supply = <®_12p0v>; - regulator-name = "5P0MAIN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - /* controlled via "environment processor" */ - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@0 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg_supply>; - vin-supply = <®_5p0v_main>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; - startup-delay-us = <1000>; - }; - - reg_usb_h1_vbus: regulator@1 { - compatible = "regulator-fixed"; - vin-supply = <®_5p0v_main>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + aliases { + ethernet0 = &fec; + ethernet1 = &i210; }; }; -&iomuxc { - pinctrl-names = "default"; - - imx6qdl-sabresd { - pinctrl_hog: hoggrp { - fsl,pins = < - /* USB Charging Controller */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /*USB_ATT_DETn*/ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /*USB_EMULATION*/ - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 /*USB_MODE1*/ - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /*USB_ALERTn*/ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /*USB_PWR_CTRL_ENn*/ - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /*USB_MODE2*/ - - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13020 /*USB_OTG_ID*/ - - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /*INT_TOUCH_N*/ - - /* DAC */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /*DAC1_RESET*/ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 /*DAC2_RESET*/ - - /* Need to Place */ - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 /*RMII_INTRPT*/ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b8b0 /*SD_CARD_RESET - Open Drain Output*/ - - /* Test Points */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 /*TP20*/ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /*TP21*/ - MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /*TP22*/ - MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x1b0b0 /*TP23*/ - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 /*TP19*/ - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /*TP26*/ - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 /*TP27*/ - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b0 /*TP28*/ - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /*TP29*/ - MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 /*TP30*/ - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 /*TP25*/ - MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 /*TP39*/ - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 /*TP40*/ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 /*TP42*/ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 /*TP43*/ - MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x1b0b0 /*TP44*/ - MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x1b0b0 /*TP45*/ - MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x1b0b0 /*TP46*/ - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /*TP41*/ - - /* System Type */ - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /*SYS_TYPE_3*/ - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 /*SYS_TYPE_2*/ - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b0 /*SYS_TYPE_1*/ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 /*SYS_TYPE_0*/ - - /* Boot Mode Selection Pins */ - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 /*BT_CFG1_0*/ - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 /*BT_CFG1_1*/ - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 /*BT_CFG1_2*/ - MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 /*BT_CFG1_3*/ - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 /*BT_CFG1_4*/ - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 /*BT_CFG1_5*/ - MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 /*BT_CFG1_6*/ - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 /*BT_CFG1_7*/ - - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b0 /*BT_CFG2_0*/ - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b0 /*BT_CFG2_1*/ - MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b0 /*BT_CFG2_2*/ - MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b0 /*BT_CFG2_3*/ - MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b0 /*BT_CFG2_4*/ - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 /*BT_CFG2_5*/ - MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b0 /*BT_CFG2_6*/ - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b0 /*BT_CFG2_7*/ - - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /*BT_CFG3_0*/ - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /*BT_CFG3_1*/ - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 /*BT_CFG3_2*/ - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 /*BT_CFG3_3*/ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 /*BT_CFG3_4*/ - MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b0b0 /*BT_CFG3_5*/ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b0 /*BT_CFG3_6*/ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 /*BT_CFG3_7*/ - - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /*BT_CFG4_0*/ - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 /*BT_CFG4_1*/ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 /*BT_CFG4_2*/ - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 /*BT_CFG4_3*/ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 /*BT_CFG4_4*/ - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 /*BT_CFG4_5*/ - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 /*BT_CFG4_7*/ - - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* HPA1_SDn */ - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* HPA2_SDn */ - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* RST_TOUCH# */ - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 /* NFC_RESET */ - >; - }; - - pinctrl_usb_otg_supply: usbotggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x40000038 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - /*MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0*/ - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - /*MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x100b1*/ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b1 - /*MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x1b0b1 - MX6QDL_PAD_KEY_COL2__GPIO4_IO10*/ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - - MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 - >; - }; - - pinctrl_ssi2: ssi3grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_gpio: i2c3grp_gpio { - fsl,pins = < - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b1 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b1 - >; - }; +&uart4 { + pic { + compatible = "zii,pic-rdu2"; + current-speed = <1000000>; + status = "okay"; - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - >; - }; + main_eeprom { + compatible = "zii,pic-main-eeprom"; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; + boot_source: boot-source@83 { + reg = <0x83 1>; + }; + max_failed_boots: max-failed-boots@8E { + reg = <0x8E 2>; + }; }; - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; + dds_eeprom { + compatible = "zii,pic-dds-eeprom"; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; }; - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - >; + watchdog { + compatible = "zii,pic-watchdog"; + status = "okay"; }; - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x17069 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069 - >; + hwmon { + compatible = "zii,pic-hwmon"; + sensors = "RMB_3V3_PMIC", + "RMB_3V3_MCU", + "RMB_5V_MAIN", + "RMB_12V_MAIN", + "RMB_28V_FIL", + "RMB_28V_HOTSWAP", + "DEB_1V8", + "DEB_3V3", + "DEB_28V_DEB", + "DEB_28V_RDU", + "TEMPERATURE", + "TEMPERATURE_2", + "RMB_28V_CURRENT"; + status = "okay"; }; - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17069 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x17069 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17069 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17069 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17069 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17069 - >; + backlight { + compatible = "zii,pic-backlight"; + status = "okay"; }; - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x1b0b1 - >; + leds { + compatible = "zii,pic-leds"; + status = "okay"; }; - pinctrl_mdio1: bitbangmdiogrp { - fsl,pins = < - /* Bitbang MDIO for DEB Switch */ - MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x1b030 /*SWITCH_MDC*/ - MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x18830 /*SWITCH_MDIO*/ - >; + pwrbutton { + compatible = "zii,pic-pwrbutton"; + status = "okay"; }; }; }; -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - &ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio2 30 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - nor_flash: m25p128@0 { + nor_flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "m25p128"; - spi-max-frequency = <20000000>; - reg = <0>; partition@0 { label = "barebox"; reg = <0x0 0xc0000>; }; - partition@e0000 { + partition@c0000 { label = "barebox-environment"; reg = <0xc0000 0x40000>; }; }; }; -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&tempmon { - barebox,sensor-name = "TEMPMON"; -}; - &i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - lm75@48 { - compatible = "national,lm75"; - reg = <0x48>; + temp-sense@48 { barebox,sensor-name = "Temp Sensor 1"; }; - - rtc: ds1341@68 { - compatible = "dallas,ds1341"; - reg = <0x68>; - }; - - mx6_eeprom: at24@54 { - compatible = "at,24c128"; - pagesize = <32>; /* TODO: VERIFY PAGE SIZE */ - reg = <0x54>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - - display-timings { - native-mode = <&timing_innolux_10_1>; - timing_innolux_10_1: innolux_10_1 { - clock-frequency = <71100000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <40>; - hfront-porch = <40>; - vback-porch = <10>; - vfront-porch = <3>; - hsync-len = <80>; - vsync-len = <10>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; }; &pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio7 12 0>; - status = "okay"; -}; - - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - no-1-8-v; - status = "okay"; -}; + host@0 { + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0 0 0 0>; + device_type = "pci"; -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio1 23 0>; - status = "okay"; - - fixed-link { - speed = <100>; - full-duplex; + i210: i210@0 { + reg = <0 0 0 0 0>; + }; }; }; diff --git a/arch/arm/dts/imx6s-riotboard.dts b/arch/arm/dts/imx6s-riotboard.dts index 575887267e..ddd0d5ba2d 100644 --- a/arch/arm/dts/imx6s-riotboard.dts +++ b/arch/arm/dts/imx6s-riotboard.dts @@ -42,3 +42,10 @@ barebox,provide-mac-address = <&fec 0x620>; }; +&clks { + fsl,pmic-stby-poweroff; +}; + +&pmic { + fsl,pmic-stby-poweroff; +}; diff --git a/arch/arm/dts/imx7d-pba-c-09.dtsi b/arch/arm/dts/imx7d-pba-c-09.dtsi new file mode 100644 index 0000000000..c5e77a7072 --- /dev/null +++ b/arch/arm/dts/imx7d-pba-c-09.dtsi @@ -0,0 +1,272 @@ +/* + * Copyright (C) 2015 PHYTEC America, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + model = "Phytec i.MX7 phyBOARD-Zeta"; + compatible = "phytec,imx7d-pba-c-09", "phytec,imx7d-phycore-som", "fsl,imx7d"; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* Enable if R9 is populated. Conflicts with userbtn2 on PEB-EVAL-02 */ + /* + reg_can1_3v3: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + */ + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_2 &pinctrl_hog_lcd>; + + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* SD1 CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* PCIe Disable */ + MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x59 /* PCIe Reset */ + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* USB2 pwr */ + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 /* ETH2 Int_N */ + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x59 /* ETH2 Reset_n */ + MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x59 /* User Button */ + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x39 /* Boot Circuit Buffer Enable + 5K pull-up */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x59 + MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x59 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x5 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x5 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x5 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x5 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x5 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x5 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x5 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x5 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x5 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x5 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x5 + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x5 + >; + }; +}; + +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_lpsr_1 &pinctrl_hog_lpsr_lcd>; + + pinctrl_hog_lpsr_1: hoggrp-lpsr_1 { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 /* USB1 pwr */ + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO06__UART5_DCE_RX 0x79 + MX7D_PAD_LPSR_GPIO1_IO07__UART5_DCE_TX 0x79 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x74 + >; + }; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + no-1-8-v; /* Fixed voltage supply, doesn't support vsel */ + enable-sdio-wakeup; + keep-power-in-suspend; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + /* Enable the following if SD1_RESET_B is used to enable/disable CAN xceiver + * xceiver-supply = <®_can1_3v3>; + */ + status = "disabled"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,magic-packet; + phy-reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +/* same MDIO bus as PHY on phyCORE SOM */ +&mdio { + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <9 0>; + reg = <2>; + rxdv-skew-ps = <0>; + txen-skew-ps = <0>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + rxc-skew-ps = <1860>; + txc-skew-ps = <1860>; + }; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + dr_mode = "host"; + status = "disabled"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + status = "disabled"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,wdog_b; +}; + +/* DTS pinmuxing and bindings for LCD adapter PEB-AV-02 */ + +&iomuxc { + pinctrl_hog_lcd: hog_lcdgrp { + fsl,pins = < + MX7D_PAD_LCD_RESET__GPIO3_IO4 0x79 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + >; + }; + + pinctrl_edt_ts_irq: tsirqgrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_pwm3: pwmgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO03__PWM3_OUT 0x30 + >; + }; + + pinctrl_hog_lpsr_lcd: hoggrp_lpsr_lcd { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x59 + >; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "disabled"; + + ft5406: ft5406@38 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ts_irq>; + interrupt-parent = <&gpio2>; + interrupts = <14 0>; + reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; +}; + +#include "imx7d-peb-av-02.dtsi" + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "disabled"; +}; + +&backlight { + pwms = <&pwm3 0 5000000>; + enable-gpios = <&gpio1 1 0>; + status = "disabled"; +}; diff --git a/arch/arm/dts/imx7d-peb-av-02.dtsi b/arch/arm/dts/imx7d-peb-av-02.dtsi new file mode 100644 index 0000000000..dcf117c71a --- /dev/null +++ b/arch/arm/dts/imx7d-peb-av-02.dtsi @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2015 PHYTEC America, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <&lcd_3v3>; + status = "disabled"; + }; + + lcd_3v3: fixedregulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "lcd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; +}; + +&iomuxc { + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX7D_PAD_LCD_CLK__LCD_CLK 0x7e + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x7e + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x7e + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x7e + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x7e + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x7e + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x7e + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x7e + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x7e + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x7e + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x7e + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x7e + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x7e + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x7e + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x7e + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x7e + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x7e + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x7e + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x7e + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x7e + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x7e + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x7e + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x7e + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x7e + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x7e + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x7e + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x7e + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x7e + >; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + lcd-supply = <&lcd_3v3>; + status = "disabled"; + + display0: display { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: ETM0700G0DH6 { + clock-frequency = <33000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <216>; + hsync-len = <128>; + vback-porch = <35>; + vfront-porch = <10>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&ft5406 { + compatible = "edt,edt-ft5406", "edt,edt-ft5x06"; + reg = <0x38>; + status = "disabled"; +};
\ No newline at end of file diff --git a/arch/arm/dts/imx7d-peb-eval-02.dtsi b/arch/arm/dts/imx7d-peb-eval-02.dtsi new file mode 100644 index 0000000000..8bde5b13e7 --- /dev/null +++ b/arch/arm/dts/imx7d-peb-eval-02.dtsi @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2015 PHYTEC America, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + phytec_leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds_eval>; + status = "disabled"; + + led@0 { + label = "eval_led_1"; + gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + + led@1 { + label = "eval_led_2"; + gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + + led@2 { + label = "eval_led_3"; + gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + }; + + phytec_buttons: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_btns_eval>; + status = "disabled"; + + userbtn@0 { + label = "eval_button_1"; + gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + linux,code = <0x100>; /* BTN_MISC */ + }; + userbtn@1 { + label = "eval_button_2"; + gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; + linux,code = <0x100>; /* BTN_MISC */ + }; + + userbtn@2 { + label = "eval_button_3"; + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + linux,code = <0x100>; /* BTN_MISC */ + }; + }; +}; + +&iomuxc { + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + >; + }; + + pinctrl_leds_eval: leds_evalgrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x79 /* Labeled UART6_RX on schematic */ + MX7D_PAD_UART3_RX_DATA__GPIO4_IO4 0x79 + MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x79 /* Labeled EXP_CONN_MUX5 on schematic */ + >; + }; + + pinctrl_btns_eval: btns_evalgrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x79 /* Labeled UART6_TX on schematic */ + MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x79 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x79 /* Labeled EXP_CONN_MUX3 on schematic */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 + MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 + >; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "disabled"; + + i2c4_eeprom: eeprom@56 { + compatible = "onnn,24c32"; + reg = <0x56>; + pagesize = <32>; + status = "disabled"; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "disabled"; +};
\ No newline at end of file diff --git a/arch/arm/dts/imx7d-phyboard-zeta.dts b/arch/arm/dts/imx7d-phyboard-zeta.dts new file mode 100644 index 0000000000..28fd2dc445 --- /dev/null +++ b/arch/arm/dts/imx7d-phyboard-zeta.dts @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2015 PHYTEC America, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "imx7d-phycore-som.dtsi" +#include "imx7d-pba-c-09.dtsi" +#include "imx7d-peb-eval-02.dtsi" + +/ { + chosen { + stdout-path = &uart5; + + environment@0 { + compatible = "barebox,environment"; + device-path = &bareboxenv; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +/**** SOM - PCM-061 ****/ + +&fec1 { + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + status = "okay"; + + boot0-partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + barebox@0 { + label = "barebox"; + reg = <0x0 0x300000>; + }; + + bareboxenv: bareboxenv@300000 { + label = "bareboxenv"; + reg = <0x300000 0x0>; + }; + }; +}; + +&i2c_eeprom { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +/**** Carrier Board - PBA-C-09 ****/ + +&uart5 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&fec2 { + status = "okay"; +}; + +/* Host mode */ +&usbotg1 { + status = "okay"; +}; + +/* OTG mode */ +&usbotg2 { + status = "okay"; +}; + +&flexcan1 { + status = "okay"; +}; + +&wdog1 { + status = "okay"; +}; + +/**** PEB-AV-02: touch controller ft5406, LCD and PWM backlight control ****/ +&i2c2 { + status = "okay"; +}; + +&ft5406 { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +/**** Interfaces on PEB-EVAL-02 ****/ + +&i2c4 { + status = "okay"; +}; + +&i2c4_eeprom { + status = "okay"; +}; + +&phytec_leds { + status = "okay"; +}; + +&phytec_buttons { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +};
\ No newline at end of file diff --git a/arch/arm/dts/imx7d-phycore-som.dtsi b/arch/arm/dts/imx7d-phycore-som.dtsi new file mode 100644 index 0000000000..ea8c801f38 --- /dev/null +++ b/arch/arm/dts/imx7d-phycore-som.dtsi @@ -0,0 +1,272 @@ +/* + * Copyright (C) 2015 PHYTEC America, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <dt-bindings/input/input.h> +#include <arm/imx7d.dtsi> + +/ { + model = "Phytec i.MX7D phyCORE"; + compatible = "phytec,imx7d-phycore-som", "fsl,imx7d"; + + memory { + reg = <0x80000000 0x80000000>; + }; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + i2c_eeprom: eeprom@50 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x50>; + status = "disabled"; + }; + + i2c_rtc: rtc@68 { + compatible = "mc,rv4162"; + reg=<0x68>; + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* PMIC VSELECT */ + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* ENET1_RESET_B */ + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 /* ENET1_INT_B */ + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5d + MX7D_PAD_SD3_CLK__SD3_CLK 0x1d + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5e + MX7D_PAD_SD3_CLK__SD3_CLK 0x1e + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5f + MX7D_PAD_SD3_CLK__SD3_CLK 0x1f + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f + >; + }; + + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 + >; + }; +}; + +&sdma { + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + /*ETH1 PHY on SOM, 25MHz crystal */ + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio2>; + interrupts = <29 0>; + reg = <1>; + }; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + tuning-step = <2>; + non-removable; + status = "disabled"; +};
\ No newline at end of file diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts new file mode 100644 index 0000000000..2e48196f9f --- /dev/null +++ b/arch/arm/dts/imx7d-sdb.dts @@ -0,0 +1,70 @@ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <arm/imx7d-sdb.dts> +#include "imx7s.dtsi" + +/ { + chosen { + stdout-path = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + /* + * This definition is present in the latest kernel DTS file, + * and could be removed once Barebox catches up. + * + * Ditto for pinctrl_spi4 + */ + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + extended_io: gpio-expander@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + spi-max-frequency = <100000>; + }; + }; +}; + +&extended_io { + q5 { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "enet-rst-b"; + }; +}; + +&iomuxc { + imx7d-sdb { + pinctrl_spi4: spi4grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 + >; + }; + }; +}; diff --git a/arch/arm/dts/imx7s-warp.dts b/arch/arm/dts/imx7s-warp.dts index c2db0d8ae0..1a92e09d14 100644 --- a/arch/arm/dts/imx7s-warp.dts +++ b/arch/arm/dts/imx7s-warp.dts @@ -8,7 +8,6 @@ */ #include <arm/imx7s-warp.dts> -#include "imx7s.dtsi" / { chosen { diff --git a/arch/arm/dts/imx7s.dtsi b/arch/arm/dts/imx7s.dtsi deleted file mode 100644 index 95c790719f..0000000000 --- a/arch/arm/dts/imx7s.dtsi +++ /dev/null @@ -1,4 +0,0 @@ -&gpt1 { - clocks = <&clks IMX7D_GPT1_ROOT_CLK>, - <&clks IMX7D_GPT1_ROOT_CLK>; -};
\ No newline at end of file diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 6110924af6..f0d29ad3c0 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -168,6 +168,7 @@ config ARCH_IMX7 select PINCTRL_IMX_IOMUX_V3 select OFTREE select COMMON_CLK_OF_PROVIDER + select ARCH_HAS_FEC_IMX config ARCH_VF610 bool @@ -395,6 +396,22 @@ config MACH_ZII_VF610_DEV select ARCH_VF610 select CLKDEV_LOOKUP +config MACH_PHYTEC_PHYCORE_IMX7 + bool "Phytec phyCORE i.MX7" + select ARCH_IMX7 + +config MACH_FREESCALE_MX7_SABRESD + bool "NXP i.MX7 SabreSD Board" + select ARCH_IMX7 + # Nedded to de-assert reset on Ethernet PHY + select DRIVER_SPI_GPIO if DRIVER_NET_FEC_IMX + select GPIO_74164 if DRIVER_NET_FEC_IMX + help + Support for NXP i.MX7 SabreSD board - one of the official + i.MX7 evaluation boards from NXP. + + https://goo.gl/6EKGdk + endif # ---------------------------------------------------------- diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c index 8482abd691..4d6c6c2b0b 100644 --- a/arch/arm/mach-imx/clocksource.c +++ b/arch/arm/mach-imx/clocksource.c @@ -115,12 +115,16 @@ static int imx_gpt_probe(struct device_d *dev) for (i = 0; i < 100; i++) writel(0, timer_base + GPT_TCTL); /* We have no udelay by now */ - clk_gpt = clk_get(dev, NULL); + clk_gpt = clk_get(dev, "per"); if (IS_ERR(clk_gpt)) { rate = 20000000; - dev_err(dev, "failed to get clock\n"); + dev_err(dev, "failed to get clock, assume %lu Hz\n", rate); } else { rate = clk_get_rate(clk_gpt); + if (!rate) { + dev_err(dev, "clock reports rate == 0\n"); + return -EIO; + } } writel(0, timer_base + GPT_TPRER); diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index 5afbf6b30f..14a1cba5a4 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -25,7 +25,20 @@ #include <asm/mmu.h> #include <asm/cache-l2x0.h> -void imx6_init_lowlevel(void) +#include <poweroff.h> +#include <mach/imx6-regs.h> +#include <io.h> + +#define CLPCR 0x54 +#define BP_CLPCR_LPM(mode) ((mode) & 0x3) +#define BM_CLPCR_LPM (0x3 << 0) +#define BM_CLPCR_SBYOS (0x1 << 6) +#define BM_CLPCR_VSTBY (0x1 << 8) +#define BP_CLPCR_STBY_COUNT 9 +#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) +#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) + +static void imx6_init_lowlevel(void) { void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR; void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR; @@ -83,7 +96,7 @@ void imx6_init_lowlevel(void) } -void imx6_setup_ipu_qos(void) +static void imx6_setup_ipu_qos(void) { void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR; void __iomem *fast2 = (void *)MX6_FAST2_BASE_ADDR; @@ -121,11 +134,14 @@ void imx6_setup_ipu_qos(void) } } -void imx6ul_enet_clk_init(void) +static void imx6ul_enet_clk_init(void) { void __iomem *gprbase = IOMEM(MX6_IOMUXC_BASE_ADDR) + 0x4000; uint32_t val; + if (!cpu_mx6_is_mx6ul() && !cpu_mx6_is_mx6ull()) + return; + val = readl(gprbase + IOMUXC_GPR1); val |= (0x3 << 17); writel(val, gprbase + IOMUXC_GPR1); @@ -169,7 +185,6 @@ int imx6_init(void) break; case IMX6_CPUTYPE_IMX6UL: cputypestr = "i.MX6 UltraLite"; - imx6ul_enet_clk_init(); break; case IMX6_CPUTYPE_IMX6ULL: cputypestr = "i.MX6 ULL"; @@ -182,6 +197,7 @@ int imx6_init(void) imx_set_silicon_revision(cputypestr, mx6_silicon_revision); imx6_setup_ipu_qos(); + imx6ul_enet_clk_init(); return 0; } @@ -296,3 +312,39 @@ static int imx6_fixup_cpus_register(void) return of_register_fixup(imx6_fixup_cpus, NULL); } device_initcall(imx6_fixup_cpus_register); + +void __noreturn imx6_pm_stby_poweroff(void) +{ + void *ccm_base = IOMEM(MX6_CCM_BASE_ADDR); + void *gpc_base = IOMEM(MX6_GPC_BASE_ADDR); + u32 val; + + /* + * All this is done to get the PMIC_STBY_REQ line high which will + * cause the PMIC to turn off the i.MX6. + */ + + /* + * First mask all interrupts in the GPC. This is necessary for + * unknown reasons + */ + writel(0xffffffff, gpc_base + 0x8); + writel(0xffffffff, gpc_base + 0xc); + writel(0xffffffff, gpc_base + 0x10); + writel(0xffffffff, gpc_base + 0x14); + + val = readl(ccm_base + CLPCR); + + val &= ~BM_CLPCR_LPM; + val |= BP_CLPCR_LPM(2); + val |= 0x3 << BP_CLPCR_STBY_COUNT; + val |= BM_CLPCR_VSTBY; + val |= BM_CLPCR_SBYOS; + val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; + + writel(val, ccm_base + CLPCR); + + asm("wfi"); + + while(1); +} diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h index 39d710f7d8..b7c0690d81 100644 --- a/arch/arm/mach-imx/include/mach/debug_ll.h +++ b/arch/arm/mach-imx/include/mach/debug_ll.h @@ -81,6 +81,13 @@ static inline void imx6_uart_setup_ll(void) imx6_uart_setup(base); } +static inline void imx7_uart_setup_ll(void) +{ + void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT)); + + imx7_uart_setup(base); +} + static inline void vf610_uart_setup_ll(void) { void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT)); diff --git a/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h b/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h index fd1de8e074..39b3b55bb2 100644 --- a/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h +++ b/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h @@ -42,6 +42,7 @@ #define MX6_MMDC_P0_MPWRDLHWCTL 0x021b0864 #define MX6_MMDC_P0_MPPDCMPR2 0x021b0890 #define MX6_MMDC_P0_MPMUR0 0x021b08b8 +#define MX6_MMDC_P0_MPDCCR 0x021b08c0 #define MX6_MMDC_P1_MDCTL 0x021b4000 #define MX6_MMDC_P1_MDPDC 0x021b4004 @@ -72,3 +73,4 @@ #define MX6_MMDC_P1_MPWRDLHWCTL 0x021b4864 #define MX6_MMDC_P1_MPPDCMPR2 0x021b4890 #define MX6_MMDC_P1_MPMUR0 0x021b48b8 +#define MX6_MMDC_P1_MPDCCR 0x021b48c0 diff --git a/arch/arm/mach-imx/include/mach/imx6.h b/arch/arm/mach-imx/include/mach/imx6.h index 6ad53433cb..e0ced7edc6 100644 --- a/arch/arm/mach-imx/include/mach/imx6.h +++ b/arch/arm/mach-imx/include/mach/imx6.h @@ -6,7 +6,7 @@ #include <mach/imx6-regs.h> #include <mach/revision.h> -void imx6_init_lowlevel(void); +void __noreturn imx6_pm_stby_poweroff(void); #define IMX6_ANATOP_SI_REV 0x260 #define IMX6SL_ANATOP_SI_REV 0x280 diff --git a/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h new file mode 100644 index 0000000000..a4217cca5d --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h @@ -0,0 +1,32 @@ +#ifndef __MACH_IMX7_CCM_REGS_H__ +#define __MACH_IMX7_CCM_REGS_H__ + +/* 0 <= n <= 190 */ +#define CCM_CCGRn_SET(n) (0x4004 + 16 * (n)) +#define CCM_CCGRn_CLR(n) (0x4008 + 16 * (n)) + +#define CCM_CCGR_UART1 148 + +#define CCM_CCGR_SETTINGn(n, s) ((s) << ((n) * 4)) +#define CCM_CCGR_SETTINGn_NOT_NEEDED(n) CCM_CCGR_SETTINGn(n, 0b00) +#define CCM_CCGR_SETTINGn_NEEDED_RUN(n) CCM_CCGR_SETTINGn(n, 0b01) +#define CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) CCM_CCGR_SETTINGn(n, 0b10) +#define CCM_CCGR_SETTINGn_NEEDED(n) CCM_CCGR_SETTINGn(n, 0b11) + +/* 0 <= n <= 120 */ +#define CCM_TARGET_ROOTn(n) (0x8000 + 128 * (n)) + +#define CCM_TARGET_ROOTn_MUX(x) ((x) << 24) +#define CCM_TARGET_ROOTn_ENABLE BIT(28) + +#define CLOCK_ROOT_INDEX(x) (((x) - 0x8000) / 128) + +/* + * Taken from "Table 5-11. Clock Root Table" from i.MX7 Dual Processor + * Reference Manual + */ +#define UART1_CLK_ROOT CLOCK_ROOT_INDEX(0xaf80) +#define UART1_CLK_ROOT__OSC_24M CCM_TARGET_ROOTn_MUX(0b000) + + +#endif diff --git a/arch/arm/mach-imx/include/mach/imx7-ddr-regs.h b/arch/arm/mach-imx/include/mach/imx7-ddr-regs.h new file mode 100644 index 0000000000..e66b2da11e --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx7-ddr-regs.h @@ -0,0 +1,174 @@ +/* + * Copyright (C) 2017 Pengutronix, Fridolin Tux <kernel@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define MX7_DDRC_MSTR 0x307a0000 +#define MX7_DDRC_STAT 0x307a0004 +#define MX7_DDRC_MRCTRL0 0x307a0010 +#define MX7_DDRC_MRCTRL1 0x307a0014 +#define MX7_DDRC_MRSTAT 0x307a0018 +#define MX7_DDRC_DERATEEN 0x307a0020 +#define MX7_DDRC_DERATEINT 0x307a0024 +#define MX7_DDRC_PWRCTL 0x307a0030 +#define MX7_DDRC_PWRTMG 0x307a0034 +#define MX7_DDRC_HWLPCTL 0x307a0038 +#define MX7_DDRC_RFSHCTL0 0x307a0050 +#define MX7_DDRC_RFSHCTL1 0x307a0054 +#define MX7_DDRC_RFSHCTL3 0x307a0060 +#define MX7_DDRC_RFSHTMG 0x307a0064 +#define MX7_DDRC_INIT0 0x307a00d0 +#define MX7_DDRC_INIT1 0x307a00d4 +#define MX7_DDRC_INIT2 0x307a00d8 +#define MX7_DDRC_INIT3 0x307a00dc +#define MX7_DDRC_INIT4 0x307a00e0 +#define MX7_DDRC_INIT5 0x307a00e4 +#define MX7_DDRC_RANKCTL 0x307a00f4 +#define MX7_DDRC_DRAMTMG0 0x307a0100 +#define MX7_DDRC_DRAMTMG1 0x307a0104 +#define MX7_DDRC_DRAMTMG2 0x307a0108 +#define MX7_DDRC_DRAMTMG3 0x307a010c +#define MX7_DDRC_DRAMTMG4 0x307a0110 +#define MX7_DDRC_DRAMTMG5 0x307a0114 +#define MX7_DDRC_DRAMTMG6 0x307a0118 +#define MX7_DDRC_DRAMTMG7 0x307a011c +#define MX7_DDRC_DRAMTMG8 0x307a0120 +#define MX7_DDRC_ZQCTL0 0x307a0180 +#define MX7_DDRC_ZQCTL1 0x307a0184 +#define MX7_DDRC_ZQCTL2 0x307a0188 +#define MX7_DDRC_ZQSTAT 0x307a018c +#define MX7_DDRC_DFITMG0 0x307a0190 +#define MX7_DDRC_DFITMG1 0x307a0194 +#define MX7_DDRC_DFILPCFG0 0x307a0198 +#define MX7_DDRC_DFIUPD0 0x307a01a0 +#define MX7_DDRC_DFIUPD1 0x307a01a4 +#define MX7_DDRC_DFIUPD2 0x307a01a8 +#define MX7_DDRC_DFIUPD3 0x307a01ac +#define MX7_DDRC_DFIMISC 0x307a01b0 +#define MX7_DDRC_ADDRMAP0 0x307a0200 +#define MX7_DDRC_ADDRMAP1 0x307a0204 +#define MX7_DDRC_ADDRMAP2 0x307a0208 +#define MX7_DDRC_ADDRMAP3 0x307a020c +#define MX7_DDRC_ADDRMAP4 0x307a0210 +#define MX7_DDRC_ADDRMAP5 0x307a0214 +#define MX7_DDRC_ADDRMAP6 0x307a0218 +#define MX7_DDRC_ODTCFG 0x307a0240 +#define MX7_DDRC_ODTMAP 0x307a0244 +#define MX7_DDRC_SCHED 0x307a0250 +#define MX7_DDRC_SCHED1 0x307a0254 +#define MX7_DDRC_PERFHPR1 0x307a025c +#define MX7_DDRC_PERFLPR1 0x307a0264 +#define MX7_DDRC_PERFWR1 0x307a026c +#define MX7_DDRC_PERFVPR1 0x307a0274 +#define MX7_DDRC_PERFVPW1 0x307a0278 +#define MX7_DDRC_DBG0 0x307a0300 +#define MX7_DDRC_DBG1 0x307a0304 +#define MX7_DDRC_DBGCAM 0x307a0308 +#define MX7_DDRC_DBGCMD 0x307a030c +#define MX7_DDRC_DBGSTAT 0x307a0310 +#define MX7_DDRC_SWCTL 0x307a0320 +#define MX7_DDRC_SWSTAT 0x307a0324 + +#define MX7_DDRC_MP_PSTAT 0x307a03fc +#define MX7_DDRC_MP_PCCFG 0x307a0400 +#define MX7_DDRC_MP_PCFGR_0 0x307a0404 +#define MX7_DDRC_MP_PCFGW_0 0x307a0408 +#define MX7_DDRC_MP_PCFGIDMASKCH_00 0x307a0410 +#define MX7_DDRC_MP_PCFGIDVALUECH_00 0x307a0414 +#define MX7_DDRC_MP_PCFGIDMASKCH_10 0x307a0418 +#define MX7_DDRC_MP_PCFGIDVALUECH_10 0x307a041c +#define MX7_DDRC_MP_PCFGIDMASKCH_20 0x307a0420 +#define MX7_DDRC_MP_PCFGIDVALUECH_20 0x307a0424 +#define MX7_DDRC_MP_PCFGIDMASKCH_30 0x307a0428 +#define MX7_DDRC_MP_PCFGIDVALUECH_30 0x307a042c +#define MX7_DDRC_MP_PCFGIDMASKCH_40 0x307a0430 +#define MX7_DDRC_MP_PCFGIDVALUECH_40 0x307a0434 +#define MX7_DDRC_MP_PCFGIDMASKCH_50 0x307a0438 +#define MX7_DDRC_MP_PCFGIDVALUECH_50 0x307a043c +#define MX7_DDRC_MP_PCFGIDMASKCH_60 0x307a0440 +#define MX7_DDRC_MP_PCFGIDVALUECH_60 0x307a0444 +#define MX7_DDRC_MP_PCFGIDMASKCH_70 0x307a0448 +#define MX7_DDRC_MP_PCFGIDVALUECH_70 0x307a044c +#define MX7_DDRC_MP_PCFGIDMASKCH_80 0x307a0450 +#define MX7_DDRC_MP_PCFGIDVALUECH_80 0x307a0454 +#define MX7_DDRC_MP_PCFGIDMASKCH_90 0x307a0458 +#define MX7_DDRC_MP_PCFGIDVALUECH_90 0x307a045c +#define MX7_DDRC_MP_PCFGIDMASKCH_100 0x307a0460 +#define MX7_DDRC_MP_PCFGIDVALUECH_100 0x307a0464 +#define MX7_DDRC_MP_PCFGIDMASKCH_110 0x307a0468 +#define MX7_DDRC_MP_PCFGIDVALUECH_110 0x307a046c +#define MX7_DDRC_MP_PCFGIDMASKCH_120 0x307a0470 +#define MX7_DDRC_MP_PCFGIDVALUECH_120 0x307a0474 +#define MX7_DDRC_MP_PCFGIDMASKCH_130 0x307a0478 +#define MX7_DDRC_MP_PCFGIDVALUECH_130 0x307a047c +#define MX7_DDRC_MP_PCFGIDMASKCH_140 0x307a0480 +#define MX7_DDRC_MP_PCFGIDVALUECH_140 0x307a0484 +#define MX7_DDRC_MP_PCFGIDMASKCH_150 0x307a0488 +#define MX7_DDRC_MP_PCFGIDVALUECH_150 0x307a048c +#define MX7_DDRC_MP_PCTRL_0 0x307a0490 +#define MX7_DDRC_MP_PCFGQOS0_0 0x307a0494 +#define MX7_DDRC_MP_PCFGQOS1_0 0x307a0498 +#define MX7_DDRC_MP_PCFGWQOS0_0 0x307a049c +#define MX7_DDRC_MP_PCFGWQOS1_0 0x307a04a0 +#define MX7_DDRC_MP_SARBASE0 0x307a0f04 +#define MX7_DDRC_MP_SARSIZE0 0x307a0f08 +#define MX7_DDRC_MP_SARBASE1 0x307a0f0c +#define MX7_DDRC_MP_SARSIZE1 0x307a0f10 +#define MX7_DDRC_MP_SARBASE2 0x307a0f14 +#define MX7_DDRC_MP_SARSIZE2 0x307a0f18 +#define MX7_DDRC_MP_SARBASE3 0x307a0f1c +#define MX7_DDRC_MP_SARSIZE3 0x307a0f20 + +#define MX7_DDR_PHY_PHY_CON0 0x30790000 +#define MX7_DDR_PHY_PHY_CON1 0x30790004 +#define MX7_DDR_PHY_PHY_CON2 0x30790008 +#define MX7_DDR_PHY_PHY_CON3 0x3079000c +#define MX7_DDR_PHY_PHY_CON4 0x30790010 +#define MX7_DDR_PHY_PHY_CON5 0x30790014 +#define MX7_DDR_PHY_LP_CON0 0x30790018 +#define MX7_DDR_PHY_RODT_CON0 0x3079001c +#define MX7_DDR_PHY_OFFSET_RD_CON0 0x30790020 +#define MX7_DDR_PHY_OFFSET_WR_CON0 0x30790030 +#define MX7_DDR_PHY_GATE_CODE_CON0 0x30790040 +#define MX7_DDR_PHY_SHIFTC_CON0 0x3079004c +#define MX7_DDR_PHY_CMD_SDLL_CON0 0x30790050 +#define MX7_DDR_PHY_LVL_CON0 0x3079006c +#define MX7_DDR_PHY_LVL_CON3 0x30790078 +#define MX7_DDR_PHY_CMD_DESKEW_CON0 0x3079007c +#define MX7_DDR_PHY_CMD_DESKEW_CON1 0x30790080 +#define MX7_DDR_PHY_CMD_DESKEW_CON2 0x30790084 +#define MX7_DDR_PHY_CMD_DESKEW_CON3 0x30790088 +#define MX7_DDR_PHY_CMD_DESKEW_CON4 0x30790094 +#define MX7_DDR_PHY_DRVDS_CON0 0x3079009c +#define MX7_DDR_PHY_MDLL_CON0 0x307900b0 +#define MX7_DDR_PHY_MDLL_CON1 0x307900b4 +#define MX7_DDR_PHY_ZQ_CON0 0x307900c0 +#define MX7_DDR_PHY_ZQ_CON1 0x307900c4 +#define MX7_DDR_PHY_ZQ_CON2 0x307900c8 +#define MX7_DDR_PHY_RD_DESKEW_CON0 0x30790190 +#define MX7_DDR_PHY_RD_DESKEW_CON3 0x3079019c +#define MX7_DDR_PHY_RD_DESKEW_CON6 0x307901a8 +#define MX7_DDR_PHY_RD_DESKEW_CON9 0x307901b4 +#define MX7_DDR_PHY_RD_DESKEW_CON12 0x307901c0 +#define MX7_DDR_PHY_RD_DESKEW_CON15 0x307901cc +#define MX7_DDR_PHY_RD_DESKEW_CON18 0x307901d8 +#define MX7_DDR_PHY_RD_DESKEW_CON21 0x307901e4 +#define MX7_DDR_PHY_WR_DESKEW_CON0 0x307901f0 +#define MX7_DDR_PHY_WR_DESKEW_CON3 0x307901fc +#define MX7_DDR_PHY_WR_DESKEW_CON6 0x30790208 +#define MX7_DDR_PHY_WR_DESKEW_CON9 0x30790214 +#define MX7_DDR_PHY_WR_DESKEW_CON12 0x30790220 +#define MX7_DDR_PHY_WR_DESKEW_CON15 0x3079022c +#define MX7_DDR_PHY_WR_DESKEW_CON18 0x30790238 +#define MX7_DDR_PHY_WR_DESKEW_CON21 0x30790244 +#define MX7_DDR_PHY_DM_DESKEW_CON 0x30790250 +#define MX7_DDR_PHY_RDATA0 0x307903a0 +#define MX7_DDR_PHY_STAT0 0x307903ac diff --git a/arch/arm/mach-imx/include/mach/iomux-mx7.h b/arch/arm/mach-imx/include/mach/iomux-mx7.h new file mode 100644 index 0000000000..2667dc3eb3 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/iomux-mx7.h @@ -0,0 +1,1328 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MACH_IOMUX_IMX7D_H__ +#define __MACH_IOMUX_IMX7D_H__ + +#include <mach/iomux-v3.h> + +enum { + MX7D_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO00__PWM4_OUT = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO01__SAI1_MCLK = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO02__GPIO1_IO2 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO02__PWM2_OUT = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 2, 0x0564, 3, 0), + MX7D_PAD_GPIO1_IO02__SAI2_MCLK = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO02__CCM_CLKO1 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO02__USB_OTG1_ID = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 7, 0x0734, 3, 0), + + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO03__PWM3_OUT = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 2, 0x0570, 3, 0), + MX7D_PAD_GPIO1_IO03__SAI3_MCLK = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO03__CCM_CLKO2 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO03__USB_OTG2_ID = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 7, 0x0730, 3, 0), + + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO04__USB_OTG1_OC = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 1, 0x072C, 1, 0), + MX7D_PAD_GPIO1_IO04__FLEXTIMER_CH4 = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 2, 0x0594, 1, 0), + MX7D_PAD_GPIO1_IO04__UART5_CTS_B = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 3, 0x0710, 4, 0), + MX7D_PAD_GPIO1_IO04__I2C1_SCL = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05D4, 2, 0), + + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 2, 0x0598, 1, 0), + MX7D_PAD_GPIO1_IO05__UART5_RTS_B = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 3, 0x0710, 5, 0), + MX7D_PAD_GPIO1_IO05__I2C1_SDA = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05D8, 2, 0), + + MX7D_PAD_GPIO1_IO06__GPIO1_IO6 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO06__USB_OTG2_OC = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 1, 0x0728, 1, 0), + MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 2, 0x059C, 1, 0), + MX7D_PAD_GPIO1_IO06__UART5_RX_DATA = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 3, 0x0714, 4, 0), + MX7D_PAD_GPIO1_IO06__I2C2_SCL = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05DC, 2, 0), + MX7D_PAD_GPIO1_IO06__CCM_WAIT = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO06__KPP_ROW4 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 6, 0x0624, 1, 0), + + MX7D_PAD_GPIO1_IO07__GPIO1_IO7 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 2, 0x05A0, 1, 0), + MX7D_PAD_GPIO1_IO07__UART5_TX_DATA = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 3, 0x0714, 5, 0), + MX7D_PAD_GPIO1_IO07__I2C2_SDA = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05E0, 2, 0), + MX7D_PAD_GPIO1_IO07__CCM_STOP = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO07__KPP_COL4 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 6, 0x0604, 1, 0), +}; + +enum { + MX7D_PAD_GPIO1_IO08__GPIO1_IO8 = IOMUX_PAD(0x026C, 0x0014, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO08__SD1_VSELECT = IOMUX_PAD(0x026C, 0x0014, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B = IOMUX_PAD(0x026C, 0x0014, 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO08__UART3_DCE_RX = IOMUX_PAD(0x026C, 0x0014, 3, 0x0704, 0, 0), + MX7D_PAD_GPIO1_IO08__UART3_DTE_TX = IOMUX_PAD(0x026C, 0x0014, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO08__I2C3_SCL = IOMUX_PAD(0x026C, 0x0014, IOMUX_CONFIG_SION | 4, 0x05E4, 0, 0), + MX7D_PAD_GPIO1_IO08__KPP_COL5 = IOMUX_PAD(0x026C, 0x0014, 6, 0x0608, 0, 0), + MX7D_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x026C, 0x0014, 7, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 = IOMUX_PAD(0x0270, 0x0018, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO09__SD1_LCTL = IOMUX_PAD(0x0270, 0x0018, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x0270, 0x0018, 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO09__UART3_DCE_TX = IOMUX_PAD(0x0270, 0x0018, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO09__UART3_DTE_RX = IOMUX_PAD(0x0270, 0x0018, 3, 0x0704, 1, 0), + MX7D_PAD_GPIO1_IO09__I2C3_SDA = IOMUX_PAD(0x0270, 0x0018, IOMUX_CONFIG_SION | 4, 0x05E8, 0, 0), + MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY = IOMUX_PAD(0x0270, 0x0018, 5, 0x04F4, 0, 0), + MX7D_PAD_GPIO1_IO09__KPP_ROW5 = IOMUX_PAD(0x0270, 0x0018, 6, 0x0628, 0, 0), + MX7D_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x0270, 0x0018, 7, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x0274, 0x001C, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO10__SD2_LCTL = IOMUX_PAD(0x0274, 0x001C, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO10__ENET1_MDIO = IOMUX_PAD(0x0274, 0x001C, 2, 0x0568, 0, 0), + MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS = IOMUX_PAD(0x0274, 0x001C, 3, 0x0700, 0, 0), + MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS = IOMUX_PAD(0x0274, 0x001C, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO10__I2C4_SCL = IOMUX_PAD(0x0274, 0x001C, IOMUX_CONFIG_SION | 4, 0x05EC, 0, 0), + MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA = IOMUX_PAD(0x0274, 0x001C, 5, 0x05A4, 0, 0), + MX7D_PAD_GPIO1_IO10__KPP_COL6 = IOMUX_PAD(0x0274, 0x001C, 6, 0x060C, 0, 0), + MX7D_PAD_GPIO1_IO10__PWM3_OUT = IOMUX_PAD(0x0274, 0x001C, 7, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x0278, 0x0020, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO11__SD3_LCTL = IOMUX_PAD(0x0278, 0x0020, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO11__ENET1_MDC = IOMUX_PAD(0x0278, 0x0020, 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS = IOMUX_PAD(0x0278, 0x0020, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS = IOMUX_PAD(0x0278, 0x0020, 3, 0x0700, 1, 0), + MX7D_PAD_GPIO1_IO11__I2C4_SDA = IOMUX_PAD(0x0278, 0x0020, IOMUX_CONFIG_SION | 4, 0x05F0, 0, 0), + MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB = IOMUX_PAD(0x0278, 0x0020, 5, 0x05A8, 0, 0), + MX7D_PAD_GPIO1_IO11__KPP_ROW6 = IOMUX_PAD(0x0278, 0x0020, 6, 0x062C, 0, 0), + MX7D_PAD_GPIO1_IO11__PWM4_OUT = IOMUX_PAD(0x0278, 0x0020, 7, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x027C, 0x0024, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO12__SD2_VSELECT = IOMUX_PAD(0x027C, 0x0024, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x027C, 0x0024, 2, 0x0564, 0, 0), + MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX = IOMUX_PAD(0x027C, 0x0024, 3, 0x04DC, 0, 0), + MX7D_PAD_GPIO1_IO12__CM4_NMI = IOMUX_PAD(0x027C, 0x0024, 4, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 = IOMUX_PAD(0x027C, 0x0024, 5, 0x04E4, 0, 0), + MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 = IOMUX_PAD(0x027C, 0x0024, 6, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO12__USB_OTG1_ID = IOMUX_PAD(0x027C, 0x0024, 7, 0x0734, 0, 0), + + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x0280, 0x0028, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO13__SD3_VSELECT = IOMUX_PAD(0x0280, 0x0028, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x0280, 0x0028, 2, 0x0570, 0, 0), + MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX = IOMUX_PAD(0x0280, 0x0028, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY = IOMUX_PAD(0x0280, 0x0028, 4, 0x04F4, 1, 0), + MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 = IOMUX_PAD(0x0280, 0x0028, 5, 0x04E8, 0, 0), + MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL = IOMUX_PAD(0x0280, 0x0028, 6, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO13__USB_OTG2_ID = IOMUX_PAD(0x0280, 0x0028, 7, 0x0730, 0, 0), + + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x0284, 0x002C, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO14__SD3_CD_B = IOMUX_PAD(0x0284, 0x002C, 1, 0x0738, 0, 0), + MX7D_PAD_GPIO1_IO14__ENET2_MDIO = IOMUX_PAD(0x0284, 0x002C, 2, 0x0574, 0, 0), + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX = IOMUX_PAD(0x0284, 0x002C, 3, 0x04E0, 0, 0), + MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B = IOMUX_PAD(0x0284, 0x002C, 4, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 = IOMUX_PAD(0x0284, 0x002C, 5, 0x04EC, 0, 0), + MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 = IOMUX_PAD(0x0284, 0x002C, 6, 0x06D8, 0, 0), + + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x0288, 0x0030, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO15__SD3_WP = IOMUX_PAD(0x0288, 0x0030, 1, 0x073C, 0, 0), + MX7D_PAD_GPIO1_IO15__ENET2_MDC = IOMUX_PAD(0x0288, 0x0030, 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX = IOMUX_PAD(0x0288, 0x0030, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B = IOMUX_PAD(0x0288, 0x0030, 4, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 = IOMUX_PAD(0x0288, 0x0030, 5, 0x04F0, 0, 0), + MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0288, 0x0030, 6, 0x06DC, 0, 0), + + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD = IOMUX_PAD(0x02A4, 0x0034, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__KPP_ROW3 = IOMUX_PAD(0x02A4, 0x0034, 3, 0x0620, 0, 0), + MX7D_PAD_EPDC_DATA00__EIM_AD0 = IOMUX_PAD(0x02A4, 0x0034, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 = IOMUX_PAD(0x02A4, 0x0034, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__LCD_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 6, 0x0638, 0, 0), + MX7D_PAD_EPDC_DATA00__LCD_CLK = IOMUX_PAD(0x02A4, 0x0034, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK = IOMUX_PAD(0x02A8, 0x0038, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__KPP_COL3 = IOMUX_PAD(0x02A8, 0x0038, 3, 0x0600, 0, 0), + MX7D_PAD_EPDC_DATA01__EIM_AD1 = IOMUX_PAD(0x02A8, 0x0038, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 = IOMUX_PAD(0x02A8, 0x0038, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__LCD_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 6, 0x063C, 0, 0), + MX7D_PAD_EPDC_DATA01__LCD_ENABLE = IOMUX_PAD(0x02A8, 0x0038, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B = IOMUX_PAD(0x02AC, 0x003C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__KPP_ROW2 = IOMUX_PAD(0x02AC, 0x003C, 3, 0x061C, 0, 0), + MX7D_PAD_EPDC_DATA02__EIM_AD2 = IOMUX_PAD(0x02AC, 0x003C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 = IOMUX_PAD(0x02AC, 0x003C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__LCD_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 6, 0x0640, 0, 0), + MX7D_PAD_EPDC_DATA02__LCD_VSYNC = IOMUX_PAD(0x02AC, 0x003C, 7, 0x0698, 0, 0), + + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN = IOMUX_PAD(0x02B0, 0x0040, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__KPP_COL2 = IOMUX_PAD(0x02B0, 0x0040, 3, 0x05FC, 0, 0), + MX7D_PAD_EPDC_DATA03__EIM_AD3 = IOMUX_PAD(0x02B0, 0x0040, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 = IOMUX_PAD(0x02B0, 0x0040, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__LCD_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 6, 0x0644, 0, 0), + MX7D_PAD_EPDC_DATA03__LCD_HSYNC = IOMUX_PAD(0x02B0, 0x0040, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 = IOMUX_PAD(0x02B4, 0x0044, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD = IOMUX_PAD(0x02B4, 0x0044, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS = IOMUX_PAD(0x02B4, 0x0044, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__KPP_ROW1 = IOMUX_PAD(0x02B4, 0x0044, 3, 0x0618, 0, 0), + MX7D_PAD_EPDC_DATA04__EIM_AD4 = IOMUX_PAD(0x02B4, 0x0044, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 = IOMUX_PAD(0x02B4, 0x0044, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__LCD_DATA4 = IOMUX_PAD(0x02B4, 0x0044, 6, 0x0648, 0, 0), + MX7D_PAD_EPDC_DATA04__JTAG_FAIL = IOMUX_PAD(0x02B4, 0x0044, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 = IOMUX_PAD(0x02B8, 0x0048, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD = IOMUX_PAD(0x02B8, 0x0048, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK = IOMUX_PAD(0x02B8, 0x0048, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__KPP_COL1 = IOMUX_PAD(0x02B8, 0x0048, 3, 0x05F8, 0, 0), + MX7D_PAD_EPDC_DATA05__EIM_AD5 = IOMUX_PAD(0x02B8, 0x0048, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 = IOMUX_PAD(0x02B8, 0x0048, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__LCD_DATA5 = IOMUX_PAD(0x02B8, 0x0048, 6, 0x064C, 0, 0), + MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE = IOMUX_PAD(0x02B8, 0x0048, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 = IOMUX_PAD(0x02BC, 0x004C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK = IOMUX_PAD(0x02BC, 0x004C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B = IOMUX_PAD(0x02BC, 0x004C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__KPP_ROW0 = IOMUX_PAD(0x02BC, 0x004C, 3, 0x0614, 0, 0), + MX7D_PAD_EPDC_DATA06__EIM_AD6 = IOMUX_PAD(0x02BC, 0x004C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__GPIO2_IO6 = IOMUX_PAD(0x02BC, 0x004C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__LCD_DATA6 = IOMUX_PAD(0x02BC, 0x004C, 6, 0x0650, 0, 0), + MX7D_PAD_EPDC_DATA06__JTAG_DE_B = IOMUX_PAD(0x02BC, 0x004C, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 = IOMUX_PAD(0x02C0, 0x0050, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B = IOMUX_PAD(0x02C0, 0x0050, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B = IOMUX_PAD(0x02C0, 0x0050, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__KPP_COL0 = IOMUX_PAD(0x02C0, 0x0050, 3, 0x05F4, 0, 0), + MX7D_PAD_EPDC_DATA07__EIM_AD7 = IOMUX_PAD(0x02C0, 0x0050, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 = IOMUX_PAD(0x02C0, 0x0050, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__LCD_DATA7 = IOMUX_PAD(0x02C0, 0x0050, 6, 0x0654, 0, 0), + MX7D_PAD_EPDC_DATA07__JTAG_DONE = IOMUX_PAD(0x02C0, 0x0050, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA08__EPDC_DATA8 = IOMUX_PAD(0x02C4, 0x0054, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD = IOMUX_PAD(0x02C4, 0x0054, 1, 0x06E4, 0, 0), + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 = IOMUX_PAD(0x02C4, 0x0054, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__UART6_DCE_RX = IOMUX_PAD(0x02C4, 0x0054, 3, 0x071C, 0, 0), + MX7D_PAD_EPDC_DATA08__UART6_DTE_TX = IOMUX_PAD(0x02C4, 0x0054, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__EIM_OE = IOMUX_PAD(0x02C4, 0x0054, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__GPIO2_IO8 = IOMUX_PAD(0x02C4, 0x0054, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__LCD_DATA8 = IOMUX_PAD(0x02C4, 0x0054, 6, 0x0658, 0, 0), + MX7D_PAD_EPDC_DATA08__LCD_BUSY = IOMUX_PAD(0x02C4, 0x0054, 7, 0x0634, 0, 0), + MX7D_PAD_EPDC_DATA08__EPDC_SDCLK = IOMUX_PAD(0x02C4, 0x0054, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA09__EPDC_DATA9 = IOMUX_PAD(0x02C8, 0x0058, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK = IOMUX_PAD(0x02C8, 0x0058, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 = IOMUX_PAD(0x02C8, 0x0058, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__UART6_DCE_TX = IOMUX_PAD(0x02C8, 0x0058, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__UART6_DTE_RX = IOMUX_PAD(0x02C8, 0x0058, 3, 0x071C, 1, 0), + MX7D_PAD_EPDC_DATA09__EIM_RW = IOMUX_PAD(0x02C8, 0x0058, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__GPIO2_IO9 = IOMUX_PAD(0x02C8, 0x0058, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__LCD_DATA9 = IOMUX_PAD(0x02C8, 0x0058, 6, 0x065C, 0, 0), + MX7D_PAD_EPDC_DATA09__LCD_DATA0 = IOMUX_PAD(0x02C8, 0x0058, 7, 0x0638, 1, 0), + MX7D_PAD_EPDC_DATA09__EPDC_SDLE = IOMUX_PAD(0x02C8, 0x0058, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA10__EPDC_DATA10 = IOMUX_PAD(0x02CC, 0x005C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B = IOMUX_PAD(0x02CC, 0x005C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 = IOMUX_PAD(0x02CC, 0x005C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS = IOMUX_PAD(0x02CC, 0x005C, 3, 0x0718, 0, 0), + MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS = IOMUX_PAD(0x02CC, 0x005C, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__EIM_CS0_B = IOMUX_PAD(0x02CC, 0x005C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__GPIO2_IO10 = IOMUX_PAD(0x02CC, 0x005C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__LCD_DATA10 = IOMUX_PAD(0x02CC, 0x005C, 6, 0x0660, 0, 0), + MX7D_PAD_EPDC_DATA10__LCD_DATA9 = IOMUX_PAD(0x02CC, 0x005C, 7, 0x065C, 1, 0), + MX7D_PAD_EPDC_DATA10__EPDC_SDOE = IOMUX_PAD(0x02CC, 0x005C, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA11__EPDC_DATA11 = IOMUX_PAD(0x02D0, 0x0060, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN = IOMUX_PAD(0x02D0, 0x0060, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 = IOMUX_PAD(0x02D0, 0x0060, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS = IOMUX_PAD(0x02D0, 0x0060, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS = IOMUX_PAD(0x02D0, 0x0060, 3, 0x0718, 1, 0), + MX7D_PAD_EPDC_DATA11__EIM_BCLK = IOMUX_PAD(0x02D0, 0x0060, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__GPIO2_IO11 = IOMUX_PAD(0x02D0, 0x0060, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__LCD_DATA11 = IOMUX_PAD(0x02D0, 0x0060, 6, 0x0664, 0, 0), + MX7D_PAD_EPDC_DATA11__LCD_DATA1 = IOMUX_PAD(0x02D0, 0x0060, 7, 0x063C, 1, 0), + MX7D_PAD_EPDC_DATA11__EPDC_SDCE0 = IOMUX_PAD(0x02D0, 0x0060, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA12__EPDC_DATA12 = IOMUX_PAD(0x02D4, 0x0064, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD = IOMUX_PAD(0x02D4, 0x0064, 1, 0x06E0, 0, 0), + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS = IOMUX_PAD(0x02D4, 0x0064, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__UART7_DCE_RX = IOMUX_PAD(0x02D4, 0x0064, 3, 0x0724, 0, 0), + MX7D_PAD_EPDC_DATA12__UART7_DTE_TX = IOMUX_PAD(0x02D4, 0x0064, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__EIM_LBA_B = IOMUX_PAD(0x02D4, 0x0064, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__GPIO2_IO12 = IOMUX_PAD(0x02D4, 0x0064, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__LCD_DATA12 = IOMUX_PAD(0x02D4, 0x0064, 6, 0x0668, 0, 0), + MX7D_PAD_EPDC_DATA12__LCD_DATA21 = IOMUX_PAD(0x02D4, 0x0064, 7, 0x068C, 0, 0), + MX7D_PAD_EPDC_DATA12__EPDC_GDCLK = IOMUX_PAD(0x02D4, 0x0064, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA13__EPDC_DATA13 = IOMUX_PAD(0x02D8, 0x0068, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD = IOMUX_PAD(0x02D8, 0x0068, 1, 0x06EC, 0, 0), + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK = IOMUX_PAD(0x02D8, 0x0068, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__UART7_DCE_TX = IOMUX_PAD(0x02D8, 0x0068, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__UART7_DTE_RX = IOMUX_PAD(0x02D8, 0x0068, 3, 0x0724, 1, 0), + MX7D_PAD_EPDC_DATA13__EIM_WAIT = IOMUX_PAD(0x02D8, 0x0068, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 = IOMUX_PAD(0x02D8, 0x0068, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__LCD_DATA13 = IOMUX_PAD(0x02D8, 0x0068, 6, 0x066C, 0, 0), + MX7D_PAD_EPDC_DATA13__LCD_CS = IOMUX_PAD(0x02D8, 0x0068, 7, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__EPDC_GDOE = IOMUX_PAD(0x02D8, 0x0068, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA14__EPDC_DATA14 = IOMUX_PAD(0x02DC, 0x006C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK = IOMUX_PAD(0x02DC, 0x006C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B = IOMUX_PAD(0x02DC, 0x006C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS = IOMUX_PAD(0x02DC, 0x006C, 3, 0x0720, 0, 0), + MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS = IOMUX_PAD(0x02DC, 0x006C, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__EIM_EB_B0 = IOMUX_PAD(0x02DC, 0x006C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__GPIO2_IO14 = IOMUX_PAD(0x02DC, 0x006C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__LCD_DATA14 = IOMUX_PAD(0x02DC, 0x006C, 6, 0x0670, 0, 0), + MX7D_PAD_EPDC_DATA14__LCD_DATA22 = IOMUX_PAD(0x02DC, 0x006C, 7, 0x0690, 0, 0), + MX7D_PAD_EPDC_DATA14__EPDC_GDSP = IOMUX_PAD(0x02DC, 0x006C, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA15__EPDC_DATA15 = IOMUX_PAD(0x02E0, 0x0070, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B = IOMUX_PAD(0x02E0, 0x0070, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B = IOMUX_PAD(0x02E0, 0x0070, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS = IOMUX_PAD(0x02E0, 0x0070, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS = IOMUX_PAD(0x02E0, 0x0070, 3, 0x0720, 1, 0), + MX7D_PAD_EPDC_DATA15__EIM_CS1_B = IOMUX_PAD(0x02E0, 0x0070, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__GPIO2_IO15 = IOMUX_PAD(0x02E0, 0x0070, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__LCD_DATA15 = IOMUX_PAD(0x02E0, 0x0070, 6, 0x0674, 0, 0), + MX7D_PAD_EPDC_DATA15__LCD_WR_RWN = IOMUX_PAD(0x02E0, 0x0070, 7, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM = IOMUX_PAD(0x02E0, 0x0070, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK = IOMUX_PAD(0x02E4, 0x0074, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN = IOMUX_PAD(0x02E4, 0x0074, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 = IOMUX_PAD(0x02E4, 0x0074, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__KPP_ROW4 = IOMUX_PAD(0x02E4, 0x0074, 3, 0x0624, 0, 0), + MX7D_PAD_EPDC_SDCLK__EIM_AD10 = IOMUX_PAD(0x02E4, 0x0074, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 = IOMUX_PAD(0x02E4, 0x0074, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__LCD_CLK = IOMUX_PAD(0x02E4, 0x0074, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__LCD_DATA20 = IOMUX_PAD(0x02E4, 0x0074, 7, 0x0688, 0, 0), + + MX7D_PAD_EPDC_SDLE__EPDC_SDLE = IOMUX_PAD(0x02E8, 0x0078, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD = IOMUX_PAD(0x02E8, 0x0078, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 = IOMUX_PAD(0x02E8, 0x0078, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__KPP_COL4 = IOMUX_PAD(0x02E8, 0x0078, 3, 0x0604, 0, 0), + MX7D_PAD_EPDC_SDLE__EIM_AD11 = IOMUX_PAD(0x02E8, 0x0078, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__GPIO2_IO17 = IOMUX_PAD(0x02E8, 0x0078, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__LCD_DATA16 = IOMUX_PAD(0x02E8, 0x0078, 6, 0x0678, 0, 0), + MX7D_PAD_EPDC_SDLE__LCD_DATA8 = IOMUX_PAD(0x02E8, 0x0078, 7, 0x0658, 1, 0), + + MX7D_PAD_EPDC_SDOE__EPDC_SDOE = IOMUX_PAD(0x02EC, 0x007C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0 = IOMUX_PAD(0x02EC, 0x007C, 1, 0x0584, 0, 0), + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 = IOMUX_PAD(0x02EC, 0x007C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDOE__KPP_COL5 = IOMUX_PAD(0x02EC, 0x007C, 3, 0x0608, 1, 0), + MX7D_PAD_EPDC_SDOE__EIM_AD12 = IOMUX_PAD(0x02EC, 0x007C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDOE__GPIO2_IO18 = IOMUX_PAD(0x02EC, 0x007C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDOE__LCD_DATA17 = IOMUX_PAD(0x02EC, 0x007C, 6, 0x067C, 0, 0), + MX7D_PAD_EPDC_SDOE__LCD_DATA23 = IOMUX_PAD(0x02EC, 0x007C, 7, 0x0694, 0, 0), + + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR = IOMUX_PAD(0x02F0, 0x0080, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1 = IOMUX_PAD(0x02F0, 0x0080, 1, 0x0588, 0, 0), + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 = IOMUX_PAD(0x02F0, 0x0080, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDSHR__KPP_ROW5 = IOMUX_PAD(0x02F0, 0x0080, 3, 0x0628, 1, 0), + MX7D_PAD_EPDC_SDSHR__EIM_AD13 = IOMUX_PAD(0x02F0, 0x0080, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 = IOMUX_PAD(0x02F0, 0x0080, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDSHR__LCD_DATA18 = IOMUX_PAD(0x02F0, 0x0080, 6, 0x0680, 0, 0), + MX7D_PAD_EPDC_SDSHR__LCD_DATA10 = IOMUX_PAD(0x02F0, 0x0080, 7, 0x0660, 1, 0), + + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 = IOMUX_PAD(0x02F4, 0x0084, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2 = IOMUX_PAD(0x02F4, 0x0084, 1, 0x058C, 0, 0), + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL = IOMUX_PAD(0x02F4, 0x0084, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE0__EIM_AD14 = IOMUX_PAD(0x02F4, 0x0084, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 = IOMUX_PAD(0x02F4, 0x0084, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE0__LCD_DATA19 = IOMUX_PAD(0x02F4, 0x0084, 6, 0x0684, 0, 0), + MX7D_PAD_EPDC_SDCE0__LCD_DATA5 = IOMUX_PAD(0x02F4, 0x0084, 7, 0x064C, 1, 0), + + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 = IOMUX_PAD(0x02F8, 0x0088, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3 = IOMUX_PAD(0x02F8, 0x0088, 1, 0x0590, 0, 0), + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC = IOMUX_PAD(0x02F8, 0x0088, 2, 0x0578, 0, 0), + MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER = IOMUX_PAD(0x02F8, 0x0088, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE1__EIM_AD15 = IOMUX_PAD(0x02F8, 0x0088, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 = IOMUX_PAD(0x02F8, 0x0088, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE1__LCD_DATA20 = IOMUX_PAD(0x02F8, 0x0088, 6, 0x0688, 1, 0), + MX7D_PAD_EPDC_SDCE1__LCD_DATA4 = IOMUX_PAD(0x02F8, 0x0088, 7, 0x0648, 1, 0), + + MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 = IOMUX_PAD(0x02FC, 0x008C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN = IOMUX_PAD(0x02FC, 0x008C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 = IOMUX_PAD(0x02FC, 0x008C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__KPP_COL6 = IOMUX_PAD(0x02FC, 0x008C, 3, 0x060C, 1, 0), + MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 = IOMUX_PAD(0x02FC, 0x008C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 = IOMUX_PAD(0x02FC, 0x008C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__LCD_DATA21 = IOMUX_PAD(0x02FC, 0x008C, 6, 0x068C, 1, 0), + MX7D_PAD_EPDC_SDCE2__LCD_DATA3 = IOMUX_PAD(0x02FC, 0x008C, 7, 0x0644, 1, 0), + + MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 = IOMUX_PAD(0x0300, 0x0090, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD = IOMUX_PAD(0x0300, 0x0090, 1, 0x06E8, 0, 0), + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 = IOMUX_PAD(0x0300, 0x0090, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE3__KPP_ROW6 = IOMUX_PAD(0x0300, 0x0090, 3, 0x062C, 1, 0), + MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 = IOMUX_PAD(0x0300, 0x0090, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 = IOMUX_PAD(0x0300, 0x0090, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE3__LCD_DATA22 = IOMUX_PAD(0x0300, 0x0090, 6, 0x0690, 1, 0), + MX7D_PAD_EPDC_SDCE3__LCD_DATA2 = IOMUX_PAD(0x0300, 0x0090, 7, 0x0640, 1, 0), + + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK = IOMUX_PAD(0x0304, 0x0094, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0 = IOMUX_PAD(0x0304, 0x0094, 1, 0x05AC, 0, 0), + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 = IOMUX_PAD(0x0304, 0x0094, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDCLK__KPP_COL7 = IOMUX_PAD(0x0304, 0x0094, 3, 0x0610, 0, 0), + MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 = IOMUX_PAD(0x0304, 0x0094, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 = IOMUX_PAD(0x0304, 0x0094, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDCLK__LCD_DATA23 = IOMUX_PAD(0x0304, 0x0094, 6, 0x0694, 1, 0), + MX7D_PAD_EPDC_GDCLK__LCD_DATA16 = IOMUX_PAD(0x0304, 0x0094, 7, 0x0678, 1, 0), + + MX7D_PAD_EPDC_GDOE__EPDC_GDOE = IOMUX_PAD(0x0308, 0x0098, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1 = IOMUX_PAD(0x0308, 0x0098, 1, 0x05B0, 0, 0), + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 = IOMUX_PAD(0x0308, 0x0098, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__KPP_ROW7 = IOMUX_PAD(0x0308, 0x0098, 3, 0x0630, 0, 0), + MX7D_PAD_EPDC_GDOE__EIM_ADDR19 = IOMUX_PAD(0x0308, 0x0098, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__GPIO2_IO25 = IOMUX_PAD(0x0308, 0x0098, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__LCD_WR_RWN = IOMUX_PAD(0x0308, 0x0098, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__LCD_DATA18 = IOMUX_PAD(0x0308, 0x0098, 7, 0x0680, 1, 0), + + MX7D_PAD_EPDC_GDRL__EPDC_GDRL = IOMUX_PAD(0x030C, 0x009C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2 = IOMUX_PAD(0x030C, 0x009C, 1, 0x05B4, 0, 0), + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL = IOMUX_PAD(0x030C, 0x009C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__EIM_ADDR20 = IOMUX_PAD(0x030C, 0x009C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__GPIO2_IO26 = IOMUX_PAD(0x030C, 0x009C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__LCD_RD_E = IOMUX_PAD(0x030C, 0x009C, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__LCD_DATA19 = IOMUX_PAD(0x030C, 0x009C, 7, 0x0684, 1, 0), + + MX7D_PAD_EPDC_GDSP__EPDC_GDSP = IOMUX_PAD(0x0310, 0x00A0, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3 = IOMUX_PAD(0x0310, 0x00A0, 1, 0x05B8, 0, 0), + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC = IOMUX_PAD(0x0310, 0x00A0, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__ENET2_TX_ER = IOMUX_PAD(0x0310, 0x00A0, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__EIM_ADDR21 = IOMUX_PAD(0x0310, 0x00A0, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__GPIO2_IO27 = IOMUX_PAD(0x0310, 0x00A0, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__LCD_BUSY = IOMUX_PAD(0x0310, 0x00A0, 6, 0x0634, 1, 0), + MX7D_PAD_EPDC_GDSP__LCD_DATA17 = IOMUX_PAD(0x0310, 0x00A0, 7, 0x067C, 1, 0), + + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 = IOMUX_PAD(0x0314, 0x00A4, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK = IOMUX_PAD(0x0314, 0x00A4, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x0314, 0x00A4, 3, 0x0570, 1, 0), + MX7D_PAD_EPDC_BDR0__EIM_ADDR22 = IOMUX_PAD(0x0314, 0x00A4, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 = IOMUX_PAD(0x0314, 0x00A4, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__LCD_CS = IOMUX_PAD(0x0314, 0x00A4, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__LCD_DATA7 = IOMUX_PAD(0x0314, 0x00A4, 7, 0x0654, 1, 0), + + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 = IOMUX_PAD(0x0318, 0x00A8, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN = IOMUX_PAD(0x0318, 0x00A8, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK = IOMUX_PAD(0x0318, 0x00A8, 2, 0x0578, 1, 0), + MX7D_PAD_EPDC_BDR1__EIM_AD8 = IOMUX_PAD(0x0318, 0x00A8, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 = IOMUX_PAD(0x0318, 0x00A8, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__LCD_ENABLE = IOMUX_PAD(0x0318, 0x00A8, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__LCD_DATA6 = IOMUX_PAD(0x0318, 0x00A8, 7, 0x0650, 1, 0), + + MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM = IOMUX_PAD(0x031C, 0x00AC, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA = IOMUX_PAD(0x031C, 0x00AC, 1, 0x05CC, 0, 0), + MX7D_PAD_EPDC_PWR_COM__ENET2_CRS = IOMUX_PAD(0x031C, 0x00AC, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__EIM_AD9 = IOMUX_PAD(0x031C, 0x00AC, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 = IOMUX_PAD(0x031C, 0x00AC, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC = IOMUX_PAD(0x031C, 0x00AC, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__LCD_DATA11 = IOMUX_PAD(0x031C, 0x00AC, 7, 0x0664, 1, 0), + + MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT = IOMUX_PAD(0x0320, 0x00B0, 0, 0x0580, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB = IOMUX_PAD(0x0320, 0x00B0, 1, 0x05D0, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__ENET2_COL = IOMUX_PAD(0x0320, 0x00B0, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1 = IOMUX_PAD(0x0320, 0x00B0, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 = IOMUX_PAD(0x0320, 0x00B0, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC = IOMUX_PAD(0x0320, 0x00B0, 6, 0x0698, 1, 0), + MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12 = IOMUX_PAD(0x0320, 0x00B0, 7, 0x0668, 1, 0), + + MX7D_PAD_LCD_CLK__LCD_CLK = IOMUX_PAD(0x0324, 0x00B4, 0, 0x0000, 0, 0), + MX7D_PAD_LCD_CLK__ECSPI4_MISO = IOMUX_PAD(0x0324, 0x00B4, 1, 0x0558, 0, 0), + MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x0324, 0x00B4, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_CLK__CSI_DATA16 = IOMUX_PAD(0x0324, 0x00B4, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_CLK__UART2_DCE_RX = IOMUX_PAD(0x0324, 0x00B4, 4, 0x06FC, 0, 0), + MX7D_PAD_LCD_CLK__UART2_DTE_TX = IOMUX_PAD(0x0324, 0x00B4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_CLK__GPIO3_IO0 = IOMUX_PAD(0x0324, 0x00B4, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_ENABLE__LCD_ENABLE = IOMUX_PAD(0x0328, 0x00B8, 0, 0x0000, 0, 0), + MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI = IOMUX_PAD(0x0328, 0x00B8, 1, 0x055C, 0, 0), + MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x0328, 0x00B8, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_ENABLE__CSI_DATA17 = IOMUX_PAD(0x0328, 0x00B8, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_ENABLE__UART2_DCE_TX = IOMUX_PAD(0x0328, 0x00B8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_ENABLE__UART2_DTE_RX = IOMUX_PAD(0x0328, 0x00B8, 4, 0x06FC, 1, 0), + MX7D_PAD_LCD_ENABLE__GPIO3_IO1 = IOMUX_PAD(0x0328, 0x00B8, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_HSYNC__LCD_HSYNC = IOMUX_PAD(0x032C, 0x00BC, 0, 0x0000, 0, 0), + MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK = IOMUX_PAD(0x032C, 0x00BC, 1, 0x0554, 0, 0), + MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x032C, 0x00BC, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_HSYNC__CSI_DATA18 = IOMUX_PAD(0x032C, 0x00BC, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS = IOMUX_PAD(0x032C, 0x00BC, 4, 0x06F8, 0, 0), + MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS = IOMUX_PAD(0x032C, 0x00BC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_HSYNC__GPIO3_IO2 = IOMUX_PAD(0x032C, 0x00BC, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_VSYNC__LCD_VSYNC = IOMUX_PAD(0x0330, 0x00C0, 0, 0x0698, 2, 0), + MX7D_PAD_LCD_VSYNC__ECSPI4_SS0 = IOMUX_PAD(0x0330, 0x00C0, 1, 0x0560, 0, 0), + MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x0330, 0x00C0, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_VSYNC__CSI_DATA19 = IOMUX_PAD(0x0330, 0x00C0, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS = IOMUX_PAD(0x0330, 0x00C0, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS = IOMUX_PAD(0x0330, 0x00C0, 4, 0x06F8, 1, 0), + MX7D_PAD_LCD_VSYNC__GPIO3_IO3 = IOMUX_PAD(0x0330, 0x00C0, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_RESET__LCD_RESET = IOMUX_PAD(0x0334, 0x00C4, 0, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__GPT1_COMPARE1 = IOMUX_PAD(0x0334, 0x00C4, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI = IOMUX_PAD(0x0334, 0x00C4, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__CSI_FIELD = IOMUX_PAD(0x0334, 0x00C4, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__EIM_DTACK_B = IOMUX_PAD(0x0334, 0x00C4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__GPIO3_IO4 = IOMUX_PAD(0x0334, 0x00C4, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA00__LCD_DATA0 = IOMUX_PAD(0x0338, 0x00C8, 0, 0x0638, 2, 0), + MX7D_PAD_LCD_DATA00__GPT1_COMPARE2 = IOMUX_PAD(0x0338, 0x00C8, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA00__CSI_DATA20 = IOMUX_PAD(0x0338, 0x00C8, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA00__EIM_DATA0 = IOMUX_PAD(0x0338, 0x00C8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA00__GPIO3_IO5 = IOMUX_PAD(0x0338, 0x00C8, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0 = IOMUX_PAD(0x0338, 0x00C8, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA01__LCD_DATA1 = IOMUX_PAD(0x033C, 0x00CC, 0, 0x063C, 2, 0), + MX7D_PAD_LCD_DATA01__GPT1_COMPARE3 = IOMUX_PAD(0x033C, 0x00CC, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA01__CSI_DATA21 = IOMUX_PAD(0x033C, 0x00CC, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA01__EIM_DATA1 = IOMUX_PAD(0x033C, 0x00CC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA01__GPIO3_IO6 = IOMUX_PAD(0x033C, 0x00CC, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1 = IOMUX_PAD(0x033C, 0x00CC, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA02__LCD_DATA2 = IOMUX_PAD(0x0340, 0x00D0, 0, 0x0640, 2, 0), + MX7D_PAD_LCD_DATA02__GPT1_CLK = IOMUX_PAD(0x0340, 0x00D0, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA02__CSI_DATA22 = IOMUX_PAD(0x0340, 0x00D0, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA02__EIM_DATA2 = IOMUX_PAD(0x0340, 0x00D0, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA02__GPIO3_IO7 = IOMUX_PAD(0x0340, 0x00D0, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2 = IOMUX_PAD(0x0340, 0x00D0, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA03__LCD_DATA3 = IOMUX_PAD(0x0344, 0x00D4, 0, 0x0644, 2, 0), + MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1 = IOMUX_PAD(0x0344, 0x00D4, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA03__CSI_DATA23 = IOMUX_PAD(0x0344, 0x00D4, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA03__EIM_DATA3 = IOMUX_PAD(0x0344, 0x00D4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA03__GPIO3_IO8 = IOMUX_PAD(0x0344, 0x00D4, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3 = IOMUX_PAD(0x0344, 0x00D4, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA04__LCD_DATA4 = IOMUX_PAD(0x0348, 0x00D8, 0, 0x0648, 2, 0), + MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2 = IOMUX_PAD(0x0348, 0x00D8, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA04__CSI_VSYNC = IOMUX_PAD(0x0348, 0x00D8, 3, 0x0520, 0, 0), + MX7D_PAD_LCD_DATA04__EIM_DATA4 = IOMUX_PAD(0x0348, 0x00D8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA04__GPIO3_IO9 = IOMUX_PAD(0x0348, 0x00D8, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4 = IOMUX_PAD(0x0348, 0x00D8, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA05__LCD_DATA5 = IOMUX_PAD(0x034C, 0x00DC, 0, 0x064C, 2, 0), + MX7D_PAD_LCD_DATA05__CSI_HSYNC = IOMUX_PAD(0x034C, 0x00DC, 3, 0x0518, 0, 0), + MX7D_PAD_LCD_DATA05__EIM_DATA5 = IOMUX_PAD(0x034C, 0x00DC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x034C, 0x00DC, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5 = IOMUX_PAD(0x034C, 0x00DC, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA06__LCD_DATA6 = IOMUX_PAD(0x0350, 0x00E0, 0, 0x0650, 2, 0), + MX7D_PAD_LCD_DATA06__CSI_PIXCLK = IOMUX_PAD(0x0350, 0x00E0, 3, 0x051C, 0, 0), + MX7D_PAD_LCD_DATA06__EIM_DATA6 = IOMUX_PAD(0x0350, 0x00E0, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x0350, 0x00E0, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6 = IOMUX_PAD(0x0350, 0x00E0, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA07__LCD_DATA7 = IOMUX_PAD(0x0354, 0x00E4, 0, 0x0654, 2, 0), + MX7D_PAD_LCD_DATA07__CSI_MCLK = IOMUX_PAD(0x0354, 0x00E4, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA07__EIM_DATA7 = IOMUX_PAD(0x0354, 0x00E4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x0354, 0x00E4, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7 = IOMUX_PAD(0x0354, 0x00E4, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA08__LCD_DATA8 = IOMUX_PAD(0x0358, 0x00E8, 0, 0x0658, 2, 0), + MX7D_PAD_LCD_DATA08__CSI_DATA9 = IOMUX_PAD(0x0358, 0x00E8, 3, 0x0514, 0, 0), + MX7D_PAD_LCD_DATA08__EIM_DATA8 = IOMUX_PAD(0x0358, 0x00E8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA08__GPIO3_IO13 = IOMUX_PAD(0x0358, 0x00E8, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8 = IOMUX_PAD(0x0358, 0x00E8, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA09__LCD_DATA9 = IOMUX_PAD(0x035C, 0x00EC, 0, 0x065C, 2, 0), + MX7D_PAD_LCD_DATA09__CSI_DATA8 = IOMUX_PAD(0x035C, 0x00EC, 3, 0x0510, 0, 0), + MX7D_PAD_LCD_DATA09__EIM_DATA9 = IOMUX_PAD(0x035C, 0x00EC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA09__GPIO3_IO14 = IOMUX_PAD(0x035C, 0x00EC, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9 = IOMUX_PAD(0x035C, 0x00EC, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA10__LCD_DATA10 = IOMUX_PAD(0x0360, 0x00F0, 0, 0x0660, 2, 0), + MX7D_PAD_LCD_DATA10__CSI_DATA7 = IOMUX_PAD(0x0360, 0x00F0, 3, 0x050C, 0, 0), + MX7D_PAD_LCD_DATA10__EIM_DATA10 = IOMUX_PAD(0x0360, 0x00F0, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA10__GPIO3_IO15 = IOMUX_PAD(0x0360, 0x00F0, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x0360, 0x00F0, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA11__LCD_DATA11 = IOMUX_PAD(0x0364, 0x00F4, 0, 0x0664, 2, 0), + MX7D_PAD_LCD_DATA11__CSI_DATA6 = IOMUX_PAD(0x0364, 0x00F4, 3, 0x0508, 0, 0), + MX7D_PAD_LCD_DATA11__EIM_DATA11 = IOMUX_PAD(0x0364, 0x00F4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA11__GPIO3_IO16 = IOMUX_PAD(0x0364, 0x00F4, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0364, 0x00F4, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA12__LCD_DATA12 = IOMUX_PAD(0x0368, 0x00F8, 0, 0x0668, 2, 0), + MX7D_PAD_LCD_DATA12__CSI_DATA5 = IOMUX_PAD(0x0368, 0x00F8, 3, 0x0504, 0, 0), + MX7D_PAD_LCD_DATA12__EIM_DATA12 = IOMUX_PAD(0x0368, 0x00F8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA12__GPIO3_IO17 = IOMUX_PAD(0x0368, 0x00F8, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0368, 0x00F8, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA13__LCD_DATA13 = IOMUX_PAD(0x036C, 0x00FC, 0, 0x066C, 1, 0), + MX7D_PAD_LCD_DATA13__CSI_DATA4 = IOMUX_PAD(0x036C, 0x00FC, 3, 0x0500, 0, 0), + MX7D_PAD_LCD_DATA13__EIM_DATA13 = IOMUX_PAD(0x036C, 0x00FC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA13__GPIO3_IO18 = IOMUX_PAD(0x036C, 0x00FC, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x036C, 0x00FC, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA14__LCD_DATA14 = IOMUX_PAD(0x0370, 0x0100, 0, 0x0670, 1, 0), + MX7D_PAD_LCD_DATA14__CSI_DATA3 = IOMUX_PAD(0x0370, 0x0100, 3, 0x04FC, 0, 0), + MX7D_PAD_LCD_DATA14__EIM_DATA14 = IOMUX_PAD(0x0370, 0x0100, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x0370, 0x0100, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x0370, 0x0100, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA15__LCD_DATA15 = IOMUX_PAD(0x0374, 0x0104, 0, 0x0674, 1, 0), + MX7D_PAD_LCD_DATA15__CSI_DATA2 = IOMUX_PAD(0x0374, 0x0104, 3, 0x04F8, 0, 0), + MX7D_PAD_LCD_DATA15__EIM_DATA15 = IOMUX_PAD(0x0374, 0x0104, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x0374, 0x0104, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0374, 0x0104, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA16__LCD_DATA16 = IOMUX_PAD(0x0378, 0x0108, 0, 0x0678, 2, 0), + MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4 = IOMUX_PAD(0x0378, 0x0108, 1, 0x0594, 0, 0), + MX7D_PAD_LCD_DATA16__CSI_DATA1 = IOMUX_PAD(0x0378, 0x0108, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA16__EIM_CRE = IOMUX_PAD(0x0378, 0x0108, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x0378, 0x0108, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16 = IOMUX_PAD(0x0378, 0x0108, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA17__LCD_DATA17 = IOMUX_PAD(0x037C, 0x010C, 0, 0x067C, 2, 0), + MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5 = IOMUX_PAD(0x037C, 0x010C, 1, 0x0598, 0, 0), + MX7D_PAD_LCD_DATA17__CSI_DATA0 = IOMUX_PAD(0x037C, 0x010C, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN = IOMUX_PAD(0x037C, 0x010C, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x037C, 0x010C, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17 = IOMUX_PAD(0x037C, 0x010C, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA18__LCD_DATA18 = IOMUX_PAD(0x0380, 0x0110, 0, 0x0680, 2, 0), + MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6 = IOMUX_PAD(0x0380, 0x0110, 1, 0x059C, 0, 0), + MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO = IOMUX_PAD(0x0380, 0x0110, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA18__CSI_DATA15 = IOMUX_PAD(0x0380, 0x0110, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA18__EIM_CS2_B = IOMUX_PAD(0x0380, 0x0110, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA18__GPIO3_IO23 = IOMUX_PAD(0x0380, 0x0110, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18 = IOMUX_PAD(0x0380, 0x0110, 6, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA19__EIM_CS3_B = IOMUX_PAD(0x0384, 0x0114, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA19__GPIO3_IO24 = IOMUX_PAD(0x0384, 0x0114, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19 = IOMUX_PAD(0x0384, 0x0114, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA19__LCD_DATA19 = IOMUX_PAD(0x0384, 0x0114, 0, 0x0684, 2, 0), + MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7 = IOMUX_PAD(0x0384, 0x0114, 1, 0x05A0, 0, 0), + MX7D_PAD_LCD_DATA19__CSI_DATA14 = IOMUX_PAD(0x0384, 0x0114, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA20__EIM_ADDR23 = IOMUX_PAD(0x0388, 0x0118, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA20__GPIO3_IO25 = IOMUX_PAD(0x0388, 0x0118, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA20__I2C3_SCL = IOMUX_PAD(0x0388, 0x0118, IOMUX_CONFIG_SION | 6, 0x05E4, 1, 0), + + MX7D_PAD_LCD_DATA20__LCD_DATA20 = IOMUX_PAD(0x0388, 0x0118, 0, 0x0688, 2, 0), + MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4 = IOMUX_PAD(0x0388, 0x0118, 1, 0x05BC, 0, 0), + MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x0388, 0x0118, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA20__CSI_DATA13 = IOMUX_PAD(0x0388, 0x0118, 3, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA21__LCD_DATA21 = IOMUX_PAD(0x038C, 0x011C, 0, 0x068C, 2, 0), + MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5 = IOMUX_PAD(0x038C, 0x011C, 1, 0x05C0, 0, 0), + MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x038C, 0x011C, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA21__CSI_DATA12 = IOMUX_PAD(0x038C, 0x011C, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA21__EIM_ADDR24 = IOMUX_PAD(0x038C, 0x011C, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA21__GPIO3_IO26 = IOMUX_PAD(0x038C, 0x011C, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA21__I2C3_SDA = IOMUX_PAD(0x038C, 0x011C, IOMUX_CONFIG_SION | 6, 0x05E8, 1, 0), + + MX7D_PAD_LCD_DATA22__LCD_DATA22 = IOMUX_PAD(0x0390, 0x0120, 0, 0x0690, 2, 0), + MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6 = IOMUX_PAD(0x0390, 0x0120, 1, 0x05C4, 0, 0), + MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x0390, 0x0120, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA22__CSI_DATA11 = IOMUX_PAD(0x0390, 0x0120, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA22__EIM_ADDR25 = IOMUX_PAD(0x0390, 0x0120, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA22__GPIO3_IO27 = IOMUX_PAD(0x0390, 0x0120, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA22__I2C4_SCL = IOMUX_PAD(0x0390, 0x0120, IOMUX_CONFIG_SION | 6, 0x05EC, 1, 0), + + MX7D_PAD_LCD_DATA23__LCD_DATA23 = IOMUX_PAD(0x0394, 0x0124, 0, 0x0694, 2, 0), + MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7 = IOMUX_PAD(0x0394, 0x0124, 1, 0x05C8, 0, 0), + MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x0394, 0x0124, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA23__CSI_DATA10 = IOMUX_PAD(0x0394, 0x0124, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA23__EIM_ADDR26 = IOMUX_PAD(0x0394, 0x0124, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA23__GPIO3_IO28 = IOMUX_PAD(0x0394, 0x0124, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA23__I2C4_SDA = IOMUX_PAD(0x0394, 0x0124, IOMUX_CONFIG_SION | 6, 0x05F0, 1, 0), + + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0398, 0x0128, 0, 0x06F4, 0, 0), + + MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__I2C1_SCL = IOMUX_PAD(0x0398, 0x0128, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY = IOMUX_PAD(0x0398, 0x0128, 2, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 = IOMUX_PAD(0x0398, 0x0128, 3, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x0398, 0x0128, 4, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 = IOMUX_PAD(0x0398, 0x0128, 5, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__ENET1_MDIO = IOMUX_PAD(0x0398, 0x0128, 6, 0x0000, 0, 0), + + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX = IOMUX_PAD(0x039C, 0x012C, 0, 0x0000, 0, 0), + + MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX = IOMUX_PAD(0x039C, 0x012C, 0, 0x06F4, 1, 0), + MX7D_PAD_UART1_TX_DATA__I2C1_SDA = IOMUX_PAD(0x039C, 0x012C, IOMUX_CONFIG_SION | 1, 0x05D8, 0, 0), + MX7D_PAD_UART1_TX_DATA__SAI3_MCLK = IOMUX_PAD(0x039C, 0x012C, 2, 0x0000, 0, 0), + MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2 = IOMUX_PAD(0x039C, 0x012C, 3, 0x0000, 0, 0), + MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x039C, 0x012C, 4, 0x0000, 0, 0), + MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 = IOMUX_PAD(0x039C, 0x012C, 5, 0x0000, 0, 0), + MX7D_PAD_UART1_TX_DATA__ENET1_MDC = IOMUX_PAD(0x039C, 0x012C, 6, 0x0000, 0, 0), + + MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x06FC, 2, 0), + + MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__I2C2_SCL = IOMUX_PAD(0x03A0, 0x0130, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK = IOMUX_PAD(0x03A0, 0x0130, 2, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 = IOMUX_PAD(0x03A0, 0x0130, 3, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x03A0, 0x0130, 4, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 = IOMUX_PAD(0x03A0, 0x0130, 5, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__ENET2_MDIO = IOMUX_PAD(0x03A0, 0x0130, 6, 0x0000, 0, 0), + + MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0), + + MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x06FC, 3, 0), + MX7D_PAD_UART2_TX_DATA__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0134, IOMUX_CONFIG_SION | 1, 0x05E0, 0, 0), + MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 = IOMUX_PAD(0x03A4, 0x0134, 2, 0x06C8, 0, 0), + MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY = IOMUX_PAD(0x03A4, 0x0134, 3, 0x0000, 0, 0), + MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x03A4, 0x0134, 4, 0x0000, 0, 0), + MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 = IOMUX_PAD(0x03A4, 0x0134, 5, 0x0000, 0, 0), + MX7D_PAD_UART2_TX_DATA__ENET2_MDC = IOMUX_PAD(0x03A4, 0x0134, 6, 0x0000, 0, 0), + + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX = IOMUX_PAD(0x03A8, 0x0138, 0, 0x0704, 2, 0), + + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX = IOMUX_PAD(0x03A8, 0x0138, 0, 0x0000, 0, 0), + MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC = IOMUX_PAD(0x03A8, 0x0138, 1, 0x072C, 0, 0), + MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC = IOMUX_PAD(0x03A8, 0x0138, 2, 0x06CC, 0, 0), + MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0138, 3, 0x0528, 0, 0), + MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x03A8, 0x0138, 4, 0x0000, 0, 0), + MX7D_PAD_UART3_RX_DATA__GPIO4_IO4 = IOMUX_PAD(0x03A8, 0x0138, 5, 0x0000, 0, 0), + MX7D_PAD_UART3_RX_DATA__SD1_LCTL = IOMUX_PAD(0x03A8, 0x0138, 6, 0x0000, 0, 0), + + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX = IOMUX_PAD(0x03AC, 0x013C, 0, 0x0000, 0, 0), + + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX = IOMUX_PAD(0x03AC, 0x013C, 0, 0x0704, 3, 0), + MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR = IOMUX_PAD(0x03AC, 0x013C, 1, 0x0000, 0, 0), + MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK = IOMUX_PAD(0x03AC, 0x013C, 2, 0x06D0, 0, 0), + MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x013C, 3, 0x052C, 0, 0), + MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x03AC, 0x013C, 4, 0x0000, 0, 0), + MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 = IOMUX_PAD(0x03AC, 0x013C, 5, 0x0000, 0, 0), + MX7D_PAD_UART3_TX_DATA__SD2_LCTL = IOMUX_PAD(0x03AC, 0x013C, 6, 0x0000, 0, 0), + + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0700, 2, 0), + + MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__USB_OTG2_OC = IOMUX_PAD(0x03B0, 0x0140, 1, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 = IOMUX_PAD(0x03B0, 0x0140, 2, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK = IOMUX_PAD(0x03B0, 0x0140, 3, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x03B0, 0x0140, 4, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__GPIO4_IO6 = IOMUX_PAD(0x03B0, 0x0140, 5, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__SD3_LCTL = IOMUX_PAD(0x03B0, 0x0140, 6, 0x0000, 0, 0), + + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS = IOMUX_PAD(0x03B4, 0x0144, 0, 0x0000, 0, 0), + + MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS = IOMUX_PAD(0x03B4, 0x0144, 0, 0x0700, 3, 0), + MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR = IOMUX_PAD(0x03B4, 0x0144, 1, 0x0000, 0, 0), + MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC = IOMUX_PAD(0x03B4, 0x0144, 2, 0x06D4, 0, 0), + MX7D_PAD_UART3_CTS_B__ECSPI1_SS0 = IOMUX_PAD(0x03B4, 0x0144, 3, 0x0530, 0, 0), + MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x03B4, 0x0144, 4, 0x0000, 0, 0), + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 = IOMUX_PAD(0x03B4, 0x0144, 5, 0x0000, 0, 0), + MX7D_PAD_UART3_CTS_B__SD1_VSELECT = IOMUX_PAD(0x03B4, 0x0144, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x03B8, 0x0148, IOMUX_CONFIG_SION | 0, 0x05D4, 1, 0), + MX7D_PAD_I2C1_SCL__UART4_DCE_CTS = IOMUX_PAD(0x03B8, 0x0148, 1, 0x0000, 0, 0), + MX7D_PAD_I2C1_SCL__UART4_DTE_RTS = IOMUX_PAD(0x03B8, 0x0148, 1, 0x0708, 0, 0), + MX7D_PAD_I2C1_SCL__FLEXCAN1_RX = IOMUX_PAD(0x03B8, 0x0148, 2, 0x04DC, 1, 0), + MX7D_PAD_I2C1_SCL__ECSPI3_MISO = IOMUX_PAD(0x03B8, 0x0148, 3, 0x0548, 0, 0), + MX7D_PAD_I2C1_SCL__GPIO4_IO8 = IOMUX_PAD(0x03B8, 0x0148, 5, 0x0000, 0, 0), + MX7D_PAD_I2C1_SCL__SD2_VSELECT = IOMUX_PAD(0x03B8, 0x0148, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x03BC, 0x014C, IOMUX_CONFIG_SION | 0, 0x05D8, 1, 0), + MX7D_PAD_I2C1_SDA__UART4_DCE_RTS = IOMUX_PAD(0x03BC, 0x014C, 1, 0x0708, 1, 0), + MX7D_PAD_I2C1_SDA__UART4_DTE_CTS = IOMUX_PAD(0x03BC, 0x014C, 1, 0x0000, 0, 0), + MX7D_PAD_I2C1_SDA__FLEXCAN1_TX = IOMUX_PAD(0x03BC, 0x014C, 2, 0x0000, 0, 0), + MX7D_PAD_I2C1_SDA__ECSPI3_MOSI = IOMUX_PAD(0x03BC, 0x014C, 3, 0x054C, 0, 0), + MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x03BC, 0x014C, 4, 0x0564, 1, 0), + MX7D_PAD_I2C1_SDA__GPIO4_IO9 = IOMUX_PAD(0x03BC, 0x014C, 5, 0x0000, 0, 0), + MX7D_PAD_I2C1_SDA__SD3_VSELECT = IOMUX_PAD(0x03BC, 0x014C, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x03C0, 0x0150, IOMUX_CONFIG_SION | 0, 0x05DC, 1, 0), + MX7D_PAD_I2C2_SCL__UART4_DCE_RX = IOMUX_PAD(0x03C0, 0x0150, 1, 0x070C, 0, 0), + MX7D_PAD_I2C2_SCL__UART4_DTE_TX = IOMUX_PAD(0x03C0, 0x0150, 1, 0x0000, 0, 0), + MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B = IOMUX_PAD(0x03C0, 0x0150, 2, 0x0000, 0, 0), + MX7D_PAD_I2C2_SCL__ECSPI3_SCLK = IOMUX_PAD(0x03C0, 0x0150, 3, 0x0544, 0, 0), + MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x03C0, 0x0150, 4, 0x0570, 2, 0), + MX7D_PAD_I2C2_SCL__GPIO4_IO10 = IOMUX_PAD(0x03C0, 0x0150, 5, 0x0000, 0, 0), + MX7D_PAD_I2C2_SCL__SD3_CD_B = IOMUX_PAD(0x03C0, 0x0150, 6, 0x0738, 1, 0), + + MX7D_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x03C4, 0x0154, IOMUX_CONFIG_SION | 0, 0x05E0, 1, 0), + MX7D_PAD_I2C2_SDA__UART4_DCE_TX = IOMUX_PAD(0x03C4, 0x0154, 1, 0x0000, 0, 0), + MX7D_PAD_I2C2_SDA__UART4_DTE_RX = IOMUX_PAD(0x03C4, 0x0154, 1, 0x070C, 1, 0), + MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x03C4, 0x0154, 2, 0x0000, 0, 0), + MX7D_PAD_I2C2_SDA__ECSPI3_SS0 = IOMUX_PAD(0x03C4, 0x0154, 3, 0x0550, 0, 0), + MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x03C4, 0x0154, 4, 0x0000, 0, 0), + MX7D_PAD_I2C2_SDA__GPIO4_IO11 = IOMUX_PAD(0x03C4, 0x0154, 5, 0x0000, 0, 0), + MX7D_PAD_I2C2_SDA__SD3_WP = IOMUX_PAD(0x03C4, 0x0154, 6, 0x073C, 1, 0), + + MX7D_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x03C8, 0x0158, IOMUX_CONFIG_SION | 0, 0x05E4, 2, 0), + MX7D_PAD_I2C3_SCL__UART5_DCE_CTS = IOMUX_PAD(0x03C8, 0x0158, 1, 0x0000, 0, 0), + MX7D_PAD_I2C3_SCL__UART5_DTE_RTS = IOMUX_PAD(0x03C8, 0x0158, 1, 0x0710, 0, 0), + MX7D_PAD_I2C3_SCL__FLEXCAN2_RX = IOMUX_PAD(0x03C8, 0x0158, 2, 0x04E0, 1, 0), + MX7D_PAD_I2C3_SCL__CSI_VSYNC = IOMUX_PAD(0x03C8, 0x0158, 3, 0x0520, 1, 0), + MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0 = IOMUX_PAD(0x03C8, 0x0158, 4, 0x06D8, 1, 0), + MX7D_PAD_I2C3_SCL__GPIO4_IO12 = IOMUX_PAD(0x03C8, 0x0158, 5, 0x0000, 0, 0), + MX7D_PAD_I2C3_SCL__EPDC_BDR0 = IOMUX_PAD(0x03C8, 0x0158, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x03CC, 0x015C, IOMUX_CONFIG_SION | 0, 0x05E8, 2, 0), + MX7D_PAD_I2C3_SDA__UART5_DCE_RTS = IOMUX_PAD(0x03CC, 0x015C, 1, 0x0710, 1, 0), + MX7D_PAD_I2C3_SDA__UART5_DTE_CTS = IOMUX_PAD(0x03CC, 0x015C, 1, 0x0000, 0, 0), + MX7D_PAD_I2C3_SDA__FLEXCAN2_TX = IOMUX_PAD(0x03CC, 0x015C, 2, 0x0000, 0, 0), + MX7D_PAD_I2C3_SDA__CSI_HSYNC = IOMUX_PAD(0x03CC, 0x015C, 3, 0x0518, 1, 0), + MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1 = IOMUX_PAD(0x03CC, 0x015C, 4, 0x06DC, 1, 0), + MX7D_PAD_I2C3_SDA__GPIO4_IO13 = IOMUX_PAD(0x03CC, 0x015C, 5, 0x0000, 0, 0), + MX7D_PAD_I2C3_SDA__EPDC_BDR1 = IOMUX_PAD(0x03CC, 0x015C, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x03D0, 0x0160, IOMUX_CONFIG_SION | 0, 0x05EC, 2, 0), + MX7D_PAD_I2C4_SCL__UART5_DCE_RX = IOMUX_PAD(0x03D0, 0x0160, 1, 0x0714, 0, 0), + MX7D_PAD_I2C4_SCL__UART5_DTE_TX = IOMUX_PAD(0x03D0, 0x0160, 1, 0x0000, 0, 0), + MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B = IOMUX_PAD(0x03D0, 0x0160, 2, 0x0000, 0, 0), + MX7D_PAD_I2C4_SCL__CSI_PIXCLK = IOMUX_PAD(0x03D0, 0x0160, 3, 0x051C, 1, 0), + MX7D_PAD_I2C4_SCL__USB_OTG1_ID = IOMUX_PAD(0x03D0, 0x0160, 4, 0x0734, 1, 0), + MX7D_PAD_I2C4_SCL__GPIO4_IO14 = IOMUX_PAD(0x03D0, 0x0160, 5, 0x0000, 0, 0), + MX7D_PAD_I2C4_SCL__EPDC_VCOM0 = IOMUX_PAD(0x03D0, 0x0160, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x03D4, 0x0164, IOMUX_CONFIG_SION | 0, 0x05F0, 2, 0), + MX7D_PAD_I2C4_SDA__UART5_DCE_TX = IOMUX_PAD(0x03D4, 0x0164, 1, 0x0000, 0, 0), + MX7D_PAD_I2C4_SDA__UART5_DTE_RX = IOMUX_PAD(0x03D4, 0x0164, 1, 0x0714, 1, 0), + MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB = IOMUX_PAD(0x03D4, 0x0164, 2, 0x0000, 0, 0), + MX7D_PAD_I2C4_SDA__CSI_MCLK = IOMUX_PAD(0x03D4, 0x0164, 3, 0x0000, 0, 0), + MX7D_PAD_I2C4_SDA__USB_OTG2_ID = IOMUX_PAD(0x03D4, 0x0164, 4, 0x0730, 1, 0), + MX7D_PAD_I2C4_SDA__GPIO4_IO15 = IOMUX_PAD(0x03D4, 0x0164, 5, 0x0000, 0, 0), + MX7D_PAD_I2C4_SDA__EPDC_VCOM1 = IOMUX_PAD(0x03D4, 0x0164, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x03D8, 0x0168, 0, 0x0524, 1, 0), + MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX = IOMUX_PAD(0x03D8, 0x0168, 1, 0x071C, 2, 0), + MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX = IOMUX_PAD(0x03D8, 0x0168, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 = IOMUX_PAD(0x03D8, 0x0168, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SCLK__CSI_DATA2 = IOMUX_PAD(0x03D8, 0x0168, 3, 0x04F8, 1, 0), + MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 = IOMUX_PAD(0x03D8, 0x0168, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM = IOMUX_PAD(0x03D8, 0x0168, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x03DC, 0x016C, 0, 0x052C, 1, 0), + MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX = IOMUX_PAD(0x03DC, 0x016C, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX = IOMUX_PAD(0x03DC, 0x016C, 1, 0x071C, 3, 0), + MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 = IOMUX_PAD(0x03DC, 0x016C, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MOSI__CSI_DATA3 = IOMUX_PAD(0x03DC, 0x016C, 3, 0x04FC, 1, 0), + MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 = IOMUX_PAD(0x03DC, 0x016C, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT = IOMUX_PAD(0x03DC, 0x016C, 6, 0x0580, 1, 0), + + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x03E0, 0x0170, 0, 0x0528, 1, 0), + MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS = IOMUX_PAD(0x03E0, 0x0170, 1, 0x0718, 2, 0), + MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS = IOMUX_PAD(0x03E0, 0x0170, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MISO__SD2_DATA6 = IOMUX_PAD(0x03E0, 0x0170, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MISO__CSI_DATA4 = IOMUX_PAD(0x03E0, 0x0170, 3, 0x0500, 1, 0), + MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 = IOMUX_PAD(0x03E0, 0x0170, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ = IOMUX_PAD(0x03E0, 0x0170, 6, 0x057C, 0, 0), + + MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x03E4, 0x0174, 0, 0x0530, 1, 0), + MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS = IOMUX_PAD(0x03E4, 0x0174, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS = IOMUX_PAD(0x03E4, 0x0174, 1, 0x0718, 3, 0), + MX7D_PAD_ECSPI1_SS0__SD2_DATA7 = IOMUX_PAD(0x03E4, 0x0174, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SS0__CSI_DATA5 = IOMUX_PAD(0x03E4, 0x0174, 3, 0x0504, 1, 0), + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 = IOMUX_PAD(0x03E4, 0x0174, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3 = IOMUX_PAD(0x03E4, 0x0174, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x03E8, 0x0178, 0, 0x0534, 0, 0), + MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x0178, 1, 0x0724, 2, 0), + MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX = IOMUX_PAD(0x03E8, 0x0178, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 = IOMUX_PAD(0x03E8, 0x0178, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SCLK__CSI_DATA6 = IOMUX_PAD(0x03E8, 0x0178, 3, 0x0508, 1, 0), + MX7D_PAD_ECSPI2_SCLK__LCD_DATA13 = IOMUX_PAD(0x03E8, 0x0178, 4, 0x066C, 2, 0), + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 = IOMUX_PAD(0x03E8, 0x0178, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0 = IOMUX_PAD(0x03E8, 0x0178, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x03EC, 0x017C, 0, 0x053C, 0, 0), + MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX = IOMUX_PAD(0x03EC, 0x017C, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX = IOMUX_PAD(0x03EC, 0x017C, 1, 0x0724, 3, 0), + MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 = IOMUX_PAD(0x03EC, 0x017C, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MOSI__CSI_DATA7 = IOMUX_PAD(0x03EC, 0x017C, 3, 0x050C, 1, 0), + MX7D_PAD_ECSPI2_MOSI__LCD_DATA14 = IOMUX_PAD(0x03EC, 0x017C, 4, 0x0670, 2, 0), + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 = IOMUX_PAD(0x03EC, 0x017C, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1 = IOMUX_PAD(0x03EC, 0x017C, 6, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 = IOMUX_PAD(0x03F0, 0x0180, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2 = IOMUX_PAD(0x03F0, 0x0180, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x03F0, 0x0180, 0, 0x0538, 0, 0), + MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS = IOMUX_PAD(0x03F0, 0x0180, 1, 0x0720, 2, 0), + MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS = IOMUX_PAD(0x03F0, 0x0180, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MISO__SD1_DATA6 = IOMUX_PAD(0x03F0, 0x0180, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MISO__CSI_DATA8 = IOMUX_PAD(0x03F0, 0x0180, 3, 0x0510, 1, 0), + MX7D_PAD_ECSPI2_MISO__LCD_DATA15 = IOMUX_PAD(0x03F0, 0x0180, 4, 0x0674, 2, 0), + + MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x03F4, 0x0184, 0, 0x0540, 0, 0), + MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS = IOMUX_PAD(0x03F4, 0x0184, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS = IOMUX_PAD(0x03F4, 0x0184, 1, 0x0720, 3, 0), + MX7D_PAD_ECSPI2_SS0__SD1_DATA7 = IOMUX_PAD(0x03F4, 0x0184, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SS0__CSI_DATA9 = IOMUX_PAD(0x03F4, 0x0184, 3, 0x0514, 1, 0), + MX7D_PAD_ECSPI2_SS0__LCD_RESET = IOMUX_PAD(0x03F4, 0x0184, 4, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 = IOMUX_PAD(0x03F4, 0x0184, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE = IOMUX_PAD(0x03F4, 0x0184, 6, 0x0000, 0, 0), + + MX7D_PAD_SD1_CD_B__SD1_CD_B = IOMUX_PAD(0x03F8, 0x0188, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_CD_B__UART6_DCE_RX = IOMUX_PAD(0x03F8, 0x0188, 2, 0x071C, 4, 0), + MX7D_PAD_SD1_CD_B__UART6_DTE_TX = IOMUX_PAD(0x03F8, 0x0188, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_CD_B__ECSPI4_MISO = IOMUX_PAD(0x03F8, 0x0188, 3, 0x0558, 1, 0), + MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0 = IOMUX_PAD(0x03F8, 0x0188, 4, 0x0584, 1, 0), + MX7D_PAD_SD1_CD_B__GPIO5_IO0 = IOMUX_PAD(0x03F8, 0x0188, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_CD_B__CCM_CLKO1 = IOMUX_PAD(0x03F8, 0x0188, 6, 0x0000, 0, 0), + + MX7D_PAD_SD1_WP__SD1_WP = IOMUX_PAD(0x03FC, 0x018C, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_WP__UART6_DCE_TX = IOMUX_PAD(0x03FC, 0x018C, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_WP__UART6_DTE_RX = IOMUX_PAD(0x03FC, 0x018C, 2, 0x071C, 5, 0), + MX7D_PAD_SD1_WP__ECSPI4_MOSI = IOMUX_PAD(0x03FC, 0x018C, 3, 0x055C, 1, 0), + MX7D_PAD_SD1_WP__FLEXTIMER1_CH1 = IOMUX_PAD(0x03FC, 0x018C, 4, 0x0588, 1, 0), + MX7D_PAD_SD1_WP__GPIO5_IO1 = IOMUX_PAD(0x03FC, 0x018C, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_WP__CCM_CLKO2 = IOMUX_PAD(0x03FC, 0x018C, 6, 0x0000, 0, 0), + + MX7D_PAD_SD1_RESET_B__SD1_RESET_B = IOMUX_PAD(0x0400, 0x0190, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_RESET_B__SAI3_MCLK = IOMUX_PAD(0x0400, 0x0190, 1, 0x0000, 0, 0), + MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS = IOMUX_PAD(0x0400, 0x0190, 2, 0x0718, 4, 0), + MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS = IOMUX_PAD(0x0400, 0x0190, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK = IOMUX_PAD(0x0400, 0x0190, 3, 0x0554, 1, 0), + MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2 = IOMUX_PAD(0x0400, 0x0190, 4, 0x058C, 1, 0), + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 = IOMUX_PAD(0x0400, 0x0190, 5, 0x0000, 0, 0), + + MX7D_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x0404, 0x0194, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_CLK__SAI3_RX_SYNC = IOMUX_PAD(0x0404, 0x0194, 1, 0x06CC, 1, 0), + MX7D_PAD_SD1_CLK__UART6_DCE_CTS = IOMUX_PAD(0x0404, 0x0194, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_CLK__UART6_DTE_RTS = IOMUX_PAD(0x0404, 0x0194, 2, 0x0718, 5, 0), + MX7D_PAD_SD1_CLK__ECSPI4_SS0 = IOMUX_PAD(0x0404, 0x0194, 3, 0x0560, 1, 0), + MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3 = IOMUX_PAD(0x0404, 0x0194, 4, 0x0590, 1, 0), + MX7D_PAD_SD1_CLK__GPIO5_IO3 = IOMUX_PAD(0x0404, 0x0194, 5, 0x0000, 0, 0), + + MX7D_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x0408, 0x0198, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_CMD__SAI3_RX_BCLK = IOMUX_PAD(0x0408, 0x0198, 1, 0x06C4, 1, 0), + MX7D_PAD_SD1_CMD__ECSPI4_SS1 = IOMUX_PAD(0x0408, 0x0198, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0 = IOMUX_PAD(0x0408, 0x0198, 4, 0x05AC, 1, 0), + MX7D_PAD_SD1_CMD__GPIO5_IO4 = IOMUX_PAD(0x0408, 0x0198, 5, 0x0000, 0, 0), + + MX7D_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x040C, 0x019C, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0 = IOMUX_PAD(0x040C, 0x019C, 1, 0x06C8, 1, 0), + MX7D_PAD_SD1_DATA0__UART7_DCE_RX = IOMUX_PAD(0x040C, 0x019C, 2, 0x0724, 4, 0), + MX7D_PAD_SD1_DATA0__UART7_DTE_TX = IOMUX_PAD(0x040C, 0x019C, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA0__ECSPI4_SS2 = IOMUX_PAD(0x040C, 0x019C, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1 = IOMUX_PAD(0x040C, 0x019C, 4, 0x05B0, 1, 0), + MX7D_PAD_SD1_DATA0__GPIO5_IO5 = IOMUX_PAD(0x040C, 0x019C, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1 = IOMUX_PAD(0x040C, 0x019C, 6, 0x04E4, 1, 0), + + MX7D_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x0410, 0x01A0, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK = IOMUX_PAD(0x0410, 0x01A0, 1, 0x06D0, 1, 0), + MX7D_PAD_SD1_DATA1__UART7_DCE_TX = IOMUX_PAD(0x0410, 0x01A0, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA1__UART7_DTE_RX = IOMUX_PAD(0x0410, 0x01A0, 2, 0x0724, 5, 0), + MX7D_PAD_SD1_DATA1__ECSPI4_SS3 = IOMUX_PAD(0x0410, 0x01A0, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2 = IOMUX_PAD(0x0410, 0x01A0, 4, 0x05B4, 1, 0), + MX7D_PAD_SD1_DATA1__GPIO5_IO6 = IOMUX_PAD(0x0410, 0x01A0, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2 = IOMUX_PAD(0x0410, 0x01A0, 6, 0x04E8, 1, 0), + + MX7D_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x0414, 0x01A4, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC = IOMUX_PAD(0x0414, 0x01A4, 1, 0x06D4, 1, 0), + MX7D_PAD_SD1_DATA2__UART7_DCE_CTS = IOMUX_PAD(0x0414, 0x01A4, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA2__UART7_DTE_RTS = IOMUX_PAD(0x0414, 0x01A4, 2, 0x0720, 4, 0), + MX7D_PAD_SD1_DATA2__ECSPI4_RDY = IOMUX_PAD(0x0414, 0x01A4, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3 = IOMUX_PAD(0x0414, 0x01A4, 4, 0x05B8, 1, 0), + MX7D_PAD_SD1_DATA2__GPIO5_IO7 = IOMUX_PAD(0x0414, 0x01A4, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3 = IOMUX_PAD(0x0414, 0x01A4, 6, 0x04EC, 1, 0), + + MX7D_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x0418, 0x01A8, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0 = IOMUX_PAD(0x0418, 0x01A8, 1, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__UART7_DCE_RTS = IOMUX_PAD(0x0418, 0x01A8, 2, 0x0720, 5, 0), + MX7D_PAD_SD1_DATA3__UART7_DTE_CTS = IOMUX_PAD(0x0418, 0x01A8, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__ECSPI3_SS1 = IOMUX_PAD(0x0418, 0x01A8, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA = IOMUX_PAD(0x0418, 0x01A8, 4, 0x05A4, 1, 0), + MX7D_PAD_SD1_DATA3__GPIO5_IO8 = IOMUX_PAD(0x0418, 0x01A8, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4 = IOMUX_PAD(0x0418, 0x01A8, 6, 0x04F0, 1, 0), + + MX7D_PAD_SD2_CD_B__SD2_CD_B = IOMUX_PAD(0x041C, 0x01AC, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_CD_B__ENET1_MDIO = IOMUX_PAD(0x041C, 0x01AC, 1, 0x0568, 2, 0), + MX7D_PAD_SD2_CD_B__ENET2_MDIO = IOMUX_PAD(0x041C, 0x01AC, 2, 0x0574, 2, 0), + MX7D_PAD_SD2_CD_B__ECSPI3_SS2 = IOMUX_PAD(0x041C, 0x01AC, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB = IOMUX_PAD(0x041C, 0x01AC, 4, 0x05A8, 1, 0), + MX7D_PAD_SD2_CD_B__GPIO5_IO9 = IOMUX_PAD(0x041C, 0x01AC, 5, 0x0000, 0, 0), + MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0 = IOMUX_PAD(0x041C, 0x01AC, 6, 0x06D8, 2, 0), + + MX7D_PAD_SD2_WP__SD2_WP = IOMUX_PAD(0x0420, 0x01B0, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__ENET1_MDC = IOMUX_PAD(0x0420, 0x01B0, 1, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__ENET2_MDC = IOMUX_PAD(0x0420, 0x01B0, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__ECSPI3_SS3 = IOMUX_PAD(0x0420, 0x01B0, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__USB_OTG1_ID = IOMUX_PAD(0x0420, 0x01B0, 4, 0x0734, 2, 0), + MX7D_PAD_SD2_WP__GPIO5_IO10 = IOMUX_PAD(0x0420, 0x01B0, 5, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0420, 0x01B0, 6, 0x06DC, 2, 0), + + MX7D_PAD_SD2_RESET_B__SD2_RESET_B = IOMUX_PAD(0x0424, 0x01B4, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_RESET_B__SAI2_MCLK = IOMUX_PAD(0x0424, 0x01B4, 1, 0x0000, 0, 0), + MX7D_PAD_SD2_RESET_B__SD2_RESET = IOMUX_PAD(0x0424, 0x01B4, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_RESET_B__ECSPI3_RDY = IOMUX_PAD(0x0424, 0x01B4, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_RESET_B__USB_OTG2_ID = IOMUX_PAD(0x0424, 0x01B4, 4, 0x0730, 2, 0), + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 = IOMUX_PAD(0x0424, 0x01B4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x0428, 0x01B8, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_CLK__SAI2_RX_SYNC = IOMUX_PAD(0x0428, 0x01B8, 1, 0x06B8, 0, 0), + MX7D_PAD_SD2_CLK__MQS_RIGHT = IOMUX_PAD(0x0428, 0x01B8, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_CLK__GPT4_CLK = IOMUX_PAD(0x0428, 0x01B8, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_CLK__GPIO5_IO12 = IOMUX_PAD(0x0428, 0x01B8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x042C, 0x01BC, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_CMD__SAI2_RX_BCLK = IOMUX_PAD(0x042C, 0x01BC, 1, 0x06B0, 0, 0), + MX7D_PAD_SD2_CMD__MQS_LEFT = IOMUX_PAD(0x042C, 0x01BC, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_CMD__GPT4_CAPTURE1 = IOMUX_PAD(0x042C, 0x01BC, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD = IOMUX_PAD(0x042C, 0x01BC, 4, 0x06EC, 1, 0), + MX7D_PAD_SD2_CMD__GPIO5_IO13 = IOMUX_PAD(0x042C, 0x01BC, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x0430, 0x01C0, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0 = IOMUX_PAD(0x0430, 0x01C0, 1, 0x06B4, 0, 0), + MX7D_PAD_SD2_DATA0__UART4_DCE_RX = IOMUX_PAD(0x0430, 0x01C0, 2, 0x070C, 2, 0), + MX7D_PAD_SD2_DATA0__UART4_DTE_TX = IOMUX_PAD(0x0430, 0x01C0, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2 = IOMUX_PAD(0x0430, 0x01C0, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK = IOMUX_PAD(0x0430, 0x01C0, 4, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA0__GPIO5_IO14 = IOMUX_PAD(0x0430, 0x01C0, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x0434, 0x01C4, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK = IOMUX_PAD(0x0434, 0x01C4, 1, 0x06BC, 0, 0), + MX7D_PAD_SD2_DATA1__UART4_DCE_TX = IOMUX_PAD(0x0434, 0x01C4, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA1__UART4_DTE_RX = IOMUX_PAD(0x0434, 0x01C4, 2, 0x070C, 3, 0), + MX7D_PAD_SD2_DATA1__GPT4_COMPARE1 = IOMUX_PAD(0x0434, 0x01C4, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B = IOMUX_PAD(0x0434, 0x01C4, 4, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA1__GPIO5_IO15 = IOMUX_PAD(0x0434, 0x01C4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x0438, 0x01C8, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC = IOMUX_PAD(0x0438, 0x01C8, 1, 0x06C0, 0, 0), + MX7D_PAD_SD2_DATA2__UART4_DCE_CTS = IOMUX_PAD(0x0438, 0x01C8, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA2__UART4_DTE_RTS = IOMUX_PAD(0x0438, 0x01C8, 2, 0x0708, 2, 0), + MX7D_PAD_SD2_DATA2__GPT4_COMPARE2 = IOMUX_PAD(0x0438, 0x01C8, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN = IOMUX_PAD(0x0438, 0x01C8, 4, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA2__GPIO5_IO16 = IOMUX_PAD(0x0438, 0x01C8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x043C, 0x01CC, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0 = IOMUX_PAD(0x043C, 0x01CC, 1, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA3__UART4_DCE_RTS = IOMUX_PAD(0x043C, 0x01CC, 2, 0x0708, 3, 0), + MX7D_PAD_SD2_DATA3__UART4_DTE_CTS = IOMUX_PAD(0x043C, 0x01CC, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA3__GPT4_COMPARE3 = IOMUX_PAD(0x043C, 0x01CC, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD = IOMUX_PAD(0x043C, 0x01CC, 4, 0x06E8, 1, 0), + MX7D_PAD_SD2_DATA3__GPIO5_IO17 = IOMUX_PAD(0x043C, 0x01CC, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x0440, 0x01D0, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_CLK__NAND_CLE = IOMUX_PAD(0x0440, 0x01D0, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_CLK__ECSPI4_MISO = IOMUX_PAD(0x0440, 0x01D0, 2, 0x0558, 2, 0), + MX7D_PAD_SD3_CLK__SAI3_RX_SYNC = IOMUX_PAD(0x0440, 0x01D0, 3, 0x06CC, 2, 0), + MX7D_PAD_SD3_CLK__GPT3_CLK = IOMUX_PAD(0x0440, 0x01D0, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_CLK__GPIO6_IO0 = IOMUX_PAD(0x0440, 0x01D0, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x0444, 0x01D4, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_CMD__NAND_ALE = IOMUX_PAD(0x0444, 0x01D4, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_CMD__ECSPI4_MOSI = IOMUX_PAD(0x0444, 0x01D4, 2, 0x055C, 2, 0), + MX7D_PAD_SD3_CMD__SAI3_RX_BCLK = IOMUX_PAD(0x0444, 0x01D4, 3, 0x06C4, 2, 0), + MX7D_PAD_SD3_CMD__GPT3_CAPTURE1 = IOMUX_PAD(0x0444, 0x01D4, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_CMD__GPIO6_IO1 = IOMUX_PAD(0x0444, 0x01D4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA0__SD3_DATA0 = IOMUX_PAD(0x0448, 0x01D8, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA0__NAND_DATA00 = IOMUX_PAD(0x0448, 0x01D8, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA0__ECSPI4_SS0 = IOMUX_PAD(0x0448, 0x01D8, 2, 0x0560, 2, 0), + MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0 = IOMUX_PAD(0x0448, 0x01D8, 3, 0x06C8, 2, 0), + MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2 = IOMUX_PAD(0x0448, 0x01D8, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA0__GPIO6_IO2 = IOMUX_PAD(0x0448, 0x01D8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA1__SD3_DATA1 = IOMUX_PAD(0x044C, 0x01DC, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA1__NAND_DATA01 = IOMUX_PAD(0x044C, 0x01DC, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA1__ECSPI4_SCLK = IOMUX_PAD(0x044C, 0x01DC, 2, 0x0554, 2, 0), + MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK = IOMUX_PAD(0x044C, 0x01DC, 3, 0x06D0, 2, 0), + MX7D_PAD_SD3_DATA1__GPT3_COMPARE1 = IOMUX_PAD(0x044C, 0x01DC, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA1__GPIO6_IO3 = IOMUX_PAD(0x044C, 0x01DC, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA2__SD3_DATA2 = IOMUX_PAD(0x0450, 0x01E0, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA2__NAND_DATA02 = IOMUX_PAD(0x0450, 0x01E0, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA2__I2C3_SDA = IOMUX_PAD(0x0450, 0x01E0, IOMUX_CONFIG_SION | 2, 0x05E8, 3, 0), + MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC = IOMUX_PAD(0x0450, 0x01E0, 3, 0x06D4, 2, 0), + MX7D_PAD_SD3_DATA2__GPT3_COMPARE2 = IOMUX_PAD(0x0450, 0x01E0, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA2__GPIO6_IO4 = IOMUX_PAD(0x0450, 0x01E0, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA3__SD3_DATA3 = IOMUX_PAD(0x0454, 0x01E4, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA3__NAND_DATA03 = IOMUX_PAD(0x0454, 0x01E4, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA3__I2C3_SCL = IOMUX_PAD(0x0454, 0x01E4, IOMUX_CONFIG_SION | 2, 0x05E4, 3, 0), + MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0 = IOMUX_PAD(0x0454, 0x01E4, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA3__GPT3_COMPARE3 = IOMUX_PAD(0x0454, 0x01E4, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA3__GPIO6_IO5 = IOMUX_PAD(0x0454, 0x01E4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA4__SD3_DATA4 = IOMUX_PAD(0x0458, 0x01E8, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA4__NAND_DATA04 = IOMUX_PAD(0x0458, 0x01E8, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA4__UART3_DCE_RX = IOMUX_PAD(0x0458, 0x01E8, 3, 0x0704, 4, 0), + MX7D_PAD_SD3_DATA4__UART3_DTE_TX = IOMUX_PAD(0x0458, 0x01E8, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA4__FLEXCAN2_RX = IOMUX_PAD(0x0458, 0x01E8, 4, 0x04E0, 2, 0), + MX7D_PAD_SD3_DATA4__GPIO6_IO6 = IOMUX_PAD(0x0458, 0x01E8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA5__SD3_DATA5 = IOMUX_PAD(0x045C, 0x01EC, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA5__NAND_DATA05 = IOMUX_PAD(0x045C, 0x01EC, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA5__UART3_DCE_TX = IOMUX_PAD(0x045C, 0x01EC, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA5__UART3_DTE_RX = IOMUX_PAD(0x045C, 0x01EC, 3, 0x0704, 5, 0), + MX7D_PAD_SD3_DATA5__FLEXCAN1_TX = IOMUX_PAD(0x045C, 0x01EC, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA5__GPIO6_IO7 = IOMUX_PAD(0x045C, 0x01EC, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA6__SD3_DATA6 = IOMUX_PAD(0x0460, 0x01F0, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA6__NAND_DATA06 = IOMUX_PAD(0x0460, 0x01F0, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA6__SD3_WP = IOMUX_PAD(0x0460, 0x01F0, 2, 0x073C, 2, 0), + MX7D_PAD_SD3_DATA6__UART3_DCE_RTS = IOMUX_PAD(0x0460, 0x01F0, 3, 0x0700, 4, 0), + MX7D_PAD_SD3_DATA6__UART3_DTE_CTS = IOMUX_PAD(0x0460, 0x01F0, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA6__FLEXCAN2_TX = IOMUX_PAD(0x0460, 0x01F0, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA6__GPIO6_IO8 = IOMUX_PAD(0x0460, 0x01F0, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA7__SD3_DATA7 = IOMUX_PAD(0x0464, 0x01F4, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA7__NAND_DATA07 = IOMUX_PAD(0x0464, 0x01F4, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA7__SD3_CD_B = IOMUX_PAD(0x0464, 0x01F4, 2, 0x0738, 2, 0), + MX7D_PAD_SD3_DATA7__UART3_DCE_CTS = IOMUX_PAD(0x0464, 0x01F4, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA7__UART3_DTE_RTS = IOMUX_PAD(0x0464, 0x01F4, 3, 0x0700, 5, 0), + MX7D_PAD_SD3_DATA7__FLEXCAN1_RX = IOMUX_PAD(0x0464, 0x01F4, 4, 0x04DC, 2, 0), + MX7D_PAD_SD3_DATA7__GPIO6_IO9 = IOMUX_PAD(0x0464, 0x01F4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_STROBE__SD3_STROBE = IOMUX_PAD(0x0468, 0x01F8, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_STROBE__NAND_RE_B = IOMUX_PAD(0x0468, 0x01F8, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_STROBE__GPIO6_IO10 = IOMUX_PAD(0x0468, 0x01F8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_RESET_B__SD3_RESET_B = IOMUX_PAD(0x046C, 0x01FC, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_RESET_B__NAND_WE_B = IOMUX_PAD(0x046C, 0x01FC, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_RESET_B__SD3_RESET = IOMUX_PAD(0x046C, 0x01FC, 2, 0x0000, 0, 0), + MX7D_PAD_SD3_RESET_B__SAI3_MCLK = IOMUX_PAD(0x046C, 0x01FC, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 = IOMUX_PAD(0x046C, 0x01FC, 5, 0x0000, 0, 0), + + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 = IOMUX_PAD(0x0470, 0x0200, 0, 0x06A0, 0, 0), + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B = IOMUX_PAD(0x0470, 0x0200, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX = IOMUX_PAD(0x0470, 0x0200, 2, 0x0714, 2, 0), + MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX = IOMUX_PAD(0x0470, 0x0200, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX = IOMUX_PAD(0x0470, 0x0200, 3, 0x04DC, 3, 0), + MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD = IOMUX_PAD(0x0470, 0x0200, 4, 0x06E4, 1, 0), + MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 = IOMUX_PAD(0x0470, 0x0200, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET = IOMUX_PAD(0x0470, 0x0200, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK = IOMUX_PAD(0x0474, 0x0204, 0, 0x06A8, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B = IOMUX_PAD(0x0474, 0x0204, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX = IOMUX_PAD(0x0474, 0x0204, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX = IOMUX_PAD(0x0474, 0x0204, 2, 0x0714, 3, 0), + MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX = IOMUX_PAD(0x0474, 0x0204, 3, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK = IOMUX_PAD(0x0474, 0x0204, 4, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 = IOMUX_PAD(0x0474, 0x0204, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET = IOMUX_PAD(0x0474, 0x0204, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC = IOMUX_PAD(0x0478, 0x0208, 0, 0x06AC, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__NAND_DQS = IOMUX_PAD(0x0478, 0x0208, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS = IOMUX_PAD(0x0478, 0x0208, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS = IOMUX_PAD(0x0478, 0x0208, 2, 0x0710, 2, 0), + MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX = IOMUX_PAD(0x0478, 0x0208, 3, 0x04E0, 3, 0), + MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B = IOMUX_PAD(0x0478, 0x0208, 4, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 = IOMUX_PAD(0x0478, 0x0208, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT = IOMUX_PAD(0x0478, 0x0208, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 = IOMUX_PAD(0x047C, 0x020C, 0, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B = IOMUX_PAD(0x047C, 0x020C, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS = IOMUX_PAD(0x047C, 0x020C, 2, 0x0710, 3, 0), + MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS = IOMUX_PAD(0x047C, 0x020C, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX = IOMUX_PAD(0x047C, 0x020C, 3, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN = IOMUX_PAD(0x047C, 0x020C, 4, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 = IOMUX_PAD(0x047C, 0x020C, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET = IOMUX_PAD(0x047C, 0x020C, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC = IOMUX_PAD(0x0480, 0x0210, 0, 0x06A4, 0, 0), + MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B = IOMUX_PAD(0x0480, 0x0210, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC = IOMUX_PAD(0x0480, 0x0210, 2, 0x06B8, 1, 0), + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL = IOMUX_PAD(0x0480, 0x0210, IOMUX_CONFIG_SION | 3, 0x05EC, 3, 0), + MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD = IOMUX_PAD(0x0480, 0x0210, 4, 0x06E0, 1, 0), + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 = IOMUX_PAD(0x0480, 0x0210, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT = IOMUX_PAD(0x0480, 0x0210, 6, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0 = IOMUX_PAD(0x0480, 0x0210, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK = IOMUX_PAD(0x0484, 0x0214, 0, 0x069C, 0, 0), + MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B = IOMUX_PAD(0x0484, 0x0214, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK = IOMUX_PAD(0x0484, 0x0214, 2, 0x06B0, 1, 0), + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA = IOMUX_PAD(0x0484, 0x0214, IOMUX_CONFIG_SION | 3, 0x05F0, 3, 0), + MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA = IOMUX_PAD(0x0484, 0x0214, 4, 0x05CC, 1, 0), + MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 = IOMUX_PAD(0x0484, 0x0214, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT = IOMUX_PAD(0x0484, 0x0214, 6, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1 = IOMUX_PAD(0x0484, 0x0214, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_MCLK__SAI1_MCLK = IOMUX_PAD(0x0488, 0x0218, 0, 0x0000, 0, 0), + MX7D_PAD_SAI1_MCLK__NAND_WP_B = IOMUX_PAD(0x0488, 0x0218, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_MCLK__SAI2_MCLK = IOMUX_PAD(0x0488, 0x0218, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY = IOMUX_PAD(0x0488, 0x0218, 3, 0x04F4, 3, 0), + MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB = IOMUX_PAD(0x0488, 0x0218, 4, 0x05D0, 1, 0), + MX7D_PAD_SAI1_MCLK__GPIO6_IO18 = IOMUX_PAD(0x0488, 0x0218, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK = IOMUX_PAD(0x0488, 0x0218, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC = IOMUX_PAD(0x048C, 0x021C, 0, 0x06C0, 1, 0), + MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x021C, 1, 0x0548, 1, 0), + MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX = IOMUX_PAD(0x048C, 0x021C, 2, 0x070C, 4, 0), + MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX = IOMUX_PAD(0x048C, 0x021C, 2, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS = IOMUX_PAD(0x048C, 0x021C, 3, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS = IOMUX_PAD(0x048C, 0x021C, 3, 0x06F0, 0, 0), + MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4 = IOMUX_PAD(0x048C, 0x021C, 4, 0x05BC, 1, 0), + MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 = IOMUX_PAD(0x048C, 0x021C, 5, 0x0000, 0, 0), + + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK = IOMUX_PAD(0x0490, 0x0220, 0, 0x06BC, 1, 0), + MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI = IOMUX_PAD(0x0490, 0x0220, 1, 0x054C, 1, 0), + MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX = IOMUX_PAD(0x0490, 0x0220, 2, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX = IOMUX_PAD(0x0490, 0x0220, 2, 0x070C, 5, 0), + MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS = IOMUX_PAD(0x0490, 0x0220, 3, 0x06F0, 1, 0), + MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS = IOMUX_PAD(0x0490, 0x0220, 3, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5 = IOMUX_PAD(0x0490, 0x0220, 4, 0x05C0, 1, 0), + MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 = IOMUX_PAD(0x0490, 0x0220, 5, 0x0000, 0, 0), + + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 = IOMUX_PAD(0x0494, 0x0224, 0, 0x06B4, 1, 0), + MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK = IOMUX_PAD(0x0494, 0x0224, 1, 0x0544, 1, 0), + MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS = IOMUX_PAD(0x0494, 0x0224, 2, 0x0000, 0, 0), + MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS = IOMUX_PAD(0x0494, 0x0224, 2, 0x0708, 4, 0), + MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS = IOMUX_PAD(0x0494, 0x0224, 3, 0x0000, 0, 0), + MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS = IOMUX_PAD(0x0494, 0x0224, 3, 0x06F8, 2, 0), + MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6 = IOMUX_PAD(0x0494, 0x0224, 4, 0x05C4, 1, 0), + MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 = IOMUX_PAD(0x0494, 0x0224, 5, 0x0000, 0, 0), + MX7D_PAD_SAI2_RX_DATA__KPP_COL7 = IOMUX_PAD(0x0494, 0x0224, 6, 0x0610, 1, 0), + + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 = IOMUX_PAD(0x0498, 0x0228, 0, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 = IOMUX_PAD(0x0498, 0x0228, 1, 0x0550, 1, 0), + MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS = IOMUX_PAD(0x0498, 0x0228, 2, 0x0708, 5, 0), + MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS = IOMUX_PAD(0x0498, 0x0228, 2, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS = IOMUX_PAD(0x0498, 0x0228, 3, 0x06F8, 3, 0), + MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS = IOMUX_PAD(0x0498, 0x0228, 3, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7 = IOMUX_PAD(0x0498, 0x0228, 4, 0x05C8, 1, 0), + MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 = IOMUX_PAD(0x0498, 0x0228, 5, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_DATA__KPP_ROW7 = IOMUX_PAD(0x0498, 0x0228, 6, 0x0630, 1, 0), + + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 = IOMUX_PAD(0x049C, 0x022C, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT = IOMUX_PAD(0x049C, 0x022C, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL = IOMUX_PAD(0x049C, 0x022C, IOMUX_CONFIG_SION | 2, 0x05E4, 4, 0), + MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS = IOMUX_PAD(0x049C, 0x022C, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS = IOMUX_PAD(0x049C, 0x022C, 3, 0x06F0, 2, 0), + MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0 = IOMUX_PAD(0x049C, 0x022C, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 = IOMUX_PAD(0x049C, 0x022C, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3 = IOMUX_PAD(0x049C, 0x022C, 6, 0x0620, 1, 0), + + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 = IOMUX_PAD(0x04A0, 0x0230, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT = IOMUX_PAD(0x04A0, 0x0230, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA = IOMUX_PAD(0x04A0, 0x0230, IOMUX_CONFIG_SION | 2, 0x05E8, 4, 0), + MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS = IOMUX_PAD(0x04A0, 0x0230, 3, 0x06F0, 3, 0), + MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS = IOMUX_PAD(0x04A0, 0x0230, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1 = IOMUX_PAD(0x04A0, 0x0230, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 = IOMUX_PAD(0x04A0, 0x0230, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3 = IOMUX_PAD(0x04A0, 0x0230, 6, 0x0600, 1, 0), + + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 = IOMUX_PAD(0x04A4, 0x0234, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX = IOMUX_PAD(0x04A4, 0x0234, 1, 0x04DC, 4, 0), + MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK = IOMUX_PAD(0x04A4, 0x0234, 2, 0x0534, 1, 0), + MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX = IOMUX_PAD(0x04A4, 0x0234, 3, 0x06F4, 2, 0), + MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX = IOMUX_PAD(0x04A4, 0x0234, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4 = IOMUX_PAD(0x04A4, 0x0234, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 = IOMUX_PAD(0x04A4, 0x0234, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2 = IOMUX_PAD(0x04A4, 0x0234, 6, 0x061C, 1, 0), + + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 = IOMUX_PAD(0x04A8, 0x0238, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX = IOMUX_PAD(0x04A8, 0x0238, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI = IOMUX_PAD(0x04A8, 0x0238, 2, 0x053C, 1, 0), + MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX = IOMUX_PAD(0x04A8, 0x0238, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX = IOMUX_PAD(0x04A8, 0x0238, 3, 0x06F4, 3, 0), + MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5 = IOMUX_PAD(0x04A8, 0x0238, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 = IOMUX_PAD(0x04A8, 0x0238, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2 = IOMUX_PAD(0x04A8, 0x0238, 6, 0x05FC, 1, 0), + + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x04AC, 0x023C, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1 = IOMUX_PAD(0x04AC, 0x023C, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6 = IOMUX_PAD(0x04AC, 0x023C, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 = IOMUX_PAD(0x04AC, 0x023C, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1 = IOMUX_PAD(0x04AC, 0x023C, 6, 0x0618, 1, 0), + + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC = IOMUX_PAD(0x04B0, 0x0240, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER = IOMUX_PAD(0x04B0, 0x0240, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2 = IOMUX_PAD(0x04B0, 0x0240, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7 = IOMUX_PAD(0x04B0, 0x0240, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 = IOMUX_PAD(0x04B0, 0x0240, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1 = IOMUX_PAD(0x04B0, 0x0240, 6, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 = IOMUX_PAD(0x04B4, 0x0244, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT = IOMUX_PAD(0x04B4, 0x0244, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3 = IOMUX_PAD(0x04B4, 0x0244, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8 = IOMUX_PAD(0x04B4, 0x0244, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 = IOMUX_PAD(0x04B4, 0x0244, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0 = IOMUX_PAD(0x04B4, 0x0244, 6, 0x0614, 1, 0), + + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x04B8, 0x0248, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT = IOMUX_PAD(0x04B8, 0x0248, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY = IOMUX_PAD(0x04B8, 0x0248, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9 = IOMUX_PAD(0x04B8, 0x0248, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 = IOMUX_PAD(0x04B8, 0x0248, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0 = IOMUX_PAD(0x04B8, 0x0248, 6, 0x05F4, 1, 0), + + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 = IOMUX_PAD(0x04BC, 0x024C, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX = IOMUX_PAD(0x04BC, 0x024C, 1, 0x04E0, 4, 0), + MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO = IOMUX_PAD(0x04BC, 0x024C, 2, 0x0538, 1, 0), + MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL = IOMUX_PAD(0x04BC, 0x024C, IOMUX_CONFIG_SION | 3, 0x05EC, 4, 0), + MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED = IOMUX_PAD(0x04BC, 0x024C, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 = IOMUX_PAD(0x04BC, 0x024C, 5, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 = IOMUX_PAD(0x04C0, 0x0250, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX = IOMUX_PAD(0x04C0, 0x0250, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0 = IOMUX_PAD(0x04C0, 0x0250, 2, 0x0540, 1, 0), + MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA = IOMUX_PAD(0x04C0, 0x0250, IOMUX_CONFIG_SION | 3, 0x05F0, 4, 0), + MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ = IOMUX_PAD(0x04C0, 0x0250, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 = IOMUX_PAD(0x04C0, 0x0250, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x04C0, 0x0250, 7, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x04C4, 0x0254, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC = IOMUX_PAD(0x04C4, 0x0254, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 = IOMUX_PAD(0x04C4, 0x0254, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 = IOMUX_PAD(0x04C4, 0x0254, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 = IOMUX_PAD(0x04C4, 0x0254, 5, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC = IOMUX_PAD(0x04C8, 0x0258, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER = IOMUX_PAD(0x04C8, 0x0258, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK = IOMUX_PAD(0x04C8, 0x0258, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 = IOMUX_PAD(0x04C8, 0x0258, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 = IOMUX_PAD(0x04C8, 0x0258, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 = IOMUX_PAD(0x04C8, 0x0258, 5, 0x0000, 0, 0), + + MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK = IOMUX_PAD(0x04CC, 0x025C, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x04CC, 0x025C, 1, 0x0564, 2, 0), + MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 = IOMUX_PAD(0x04CC, 0x025C, 2, 0x06A0, 1, 0), + MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3 = IOMUX_PAD(0x04CC, 0x025C, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ = IOMUX_PAD(0x04CC, 0x025C, 4, 0x057C, 1, 0), + MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 = IOMUX_PAD(0x04CC, 0x025C, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1 = IOMUX_PAD(0x04CC, 0x025C, 6, 0x04E4, 2, 0), + MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0 = IOMUX_PAD(0x04CC, 0x025C, 7, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK = IOMUX_PAD(0x04D0, 0x0260, 0, 0x056C, 0, 0), + MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B = IOMUX_PAD(0x04D0, 0x0260, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK = IOMUX_PAD(0x04D0, 0x0260, 2, 0x06A8, 1, 0), + MX7D_PAD_ENET1_RX_CLK__GPT2_CLK = IOMUX_PAD(0x04D0, 0x0260, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE = IOMUX_PAD(0x04D0, 0x0260, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 = IOMUX_PAD(0x04D0, 0x0260, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2 = IOMUX_PAD(0x04D0, 0x0260, 6, 0x04E8, 2, 0), + MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1 = IOMUX_PAD(0x04D0, 0x0260, 7, 0x0000, 0, 0), + + MX7D_PAD_ENET1_CRS__ENET1_CRS = IOMUX_PAD(0x04D4, 0x0264, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x04D4, 0x0264, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC = IOMUX_PAD(0x04D4, 0x0264, 2, 0x06AC, 1, 0), + MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1 = IOMUX_PAD(0x04D4, 0x0264, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0 = IOMUX_PAD(0x04D4, 0x0264, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__GPIO7_IO14 = IOMUX_PAD(0x04D4, 0x0264, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3 = IOMUX_PAD(0x04D4, 0x0264, 6, 0x04EC, 2, 0), + MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2 = IOMUX_PAD(0x04D4, 0x0264, 7, 0x0000, 0, 0), + + MX7D_PAD_ENET1_COL__ENET1_COL = IOMUX_PAD(0x04D8, 0x0268, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY = IOMUX_PAD(0x04D8, 0x0268, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 = IOMUX_PAD(0x04D8, 0x0268, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__GPT2_CAPTURE2 = IOMUX_PAD(0x04D8, 0x0268, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1 = IOMUX_PAD(0x04D8, 0x0268, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__GPIO7_IO15 = IOMUX_PAD(0x04D8, 0x0268, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__CCM_EXT_CLK4 = IOMUX_PAD(0x04D8, 0x0268, 6, 0x04F0, 2, 0), + MX7D_PAD_ENET1_COL__CSU_INT_DEB = IOMUX_PAD(0x04D8, 0x0268, 7, 0x0000, 0, 0), +}; + +static inline void mx7_setup_pad(void __iomem *iomux, iomux_v3_cfg_t pad) +{ + unsigned int flags = 0; + uint32_t mode = IOMUX_MODE(pad); + + if (mode & IOMUX_CONFIG_LPSR) { + mode &= ~IOMUX_CONFIG_LPSR; + flags = ZERO_OFFSET_VALID | IMX7_PINMUX_LPSR; + } + + iomux_v3_setup_pad(iomux, flags, + IOMUX_CTRL_OFS(pad), + IOMUX_PAD_CTRL_OFS(pad), + IOMUX_SEL_INPUT_OFS(pad), + mode, + IOMUX_PAD_CTRL(pad), + IOMUX_SEL_INPUT(pad)); +} + +#endif diff --git a/arch/arm/mach-imx/include/mach/iomux-v3.h b/arch/arm/mach-imx/include/mach/iomux-v3.h index 271fe94a00..40f6e59992 100644 --- a/arch/arm/mach-imx/include/mach/iomux-v3.h +++ b/arch/arm/mach-imx/include/mach/iomux-v3.h @@ -113,6 +113,7 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_SRE_SLOW (0 << 0) #define IOMUX_CONFIG_SION (0x1 << 4) +#define IOMUX_CONFIG_LPSR BIT(5) #define SHARE_MUX_CONF_REG 0x1 #define ZERO_OFFSET_VALID 0x2 |