summaryrefslogtreecommitdiffstats
path: root/arch/arm
diff options
context:
space:
mode:
authorSascha Hauer <s.hauer@pengutronix.de>2019-05-06 10:14:48 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-05-10 08:18:25 +0200
commitfb4ed4c14091c969f64e441f6d40947d22ccaed1 (patch)
tree5294fa006b247905c3161596aac556e070c82122 /arch/arm
parentf1fa2099a9432a0913d7d087372db1f7287e9226 (diff)
downloadbarebox-fb4ed4c14091c969f64e441f6d40947d22ccaed1.tar.gz
barebox-fb4ed4c14091c969f64e441f6d40947d22ccaed1.tar.xz
ARM: Layerscape: TQMLS1046a: Sync qspi RCW from TQ U-Boot
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg
index 395c75c7d0..2df229c56c 100644
--- a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg
+++ b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg
@@ -8,7 +8,7 @@
# 32: 33 - CGA_PLL2_CFG : 0 [0x0 / 0b00]
# 34: 39 - CGA_PLL2_RAT : 14 [0xe / 0b001110]
# 96: 99 - C1_PLL_SEL : 0 [0x0 / 0b0000]
-# 128:143 - SRDS_PRTCL_S1 : 13107 [0x3333 / 0b0011001100110011]
+# 128:143 - SRDS_PRTCL_S1 : 4403 [0x1133 / 0b0001000100110011]
# 144:159 - SRDS_PRTCL_S2 : 21849 [0x5559 / 0b0101010101011001]
# 160:161 - SRDS_PLL_REF_CLK_SEL_S1 : 3 [0x3 / 0b11]
# 162:163 - SRDS_PLL_REF_CLK_SEL_S2 : 3 [0x3 / 0b11]
@@ -39,7 +39,7 @@
# 357:359 - IRQ_EXT : 0 [0x0 / 0b000]
# 360:362 - SPI_EXT : 0 [0x0 / 0b000]
# 363:365 - SDHC_EXT : 0 [0x0 / 0b000]
-# 366:368 - UART_BASE : 5 [0x5 / 0b101]
+# 366:368 - UART_BASE : 6 [0x6 / 0b110]
# 369:369 - ASLEEP : 0 [0x0 / 0b0]
# 370:370 - RTC : 0 [0x0 / 0b0]
# 371:371 - SDHC_BASE : 0 [0x0 / 0b0]
@@ -79,6 +79,6 @@
aa55aa55 01ee0100
# RCW
0c140010 0e000000 00000000 00000000
-33335559 f0005002 40025000 c1000000
-00000000 00000000 00000000 00028800
+11335559 f0005002 40025000 c1000000
+00000000 00000000 00000000 00030800
20004000 01103202 00000096 00000001