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| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2010-07-22 05:00:13 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-07-23 08:35:25 +0200 |
| commit | d8c86961b333a9c88cf2aa4282a43b8382e9b810 (patch) | |
| tree | cf8b39db96805a2ed876ba14f6824a96ebffc906 /arch/blackfin/boards/ipe337/config.h | |
| parent | d879de38e8430eeb9b37b7b6a2ac3341b0b029f7 (diff) | |
| download | barebox-d8c86961b333a9c88cf2aa4282a43b8382e9b810.tar.gz barebox-d8c86961b333a9c88cf2aa4282a43b8382e9b810.tar.xz | |
move boards to arch/<architecure>/boards
this will allow each arch to handle the boards more simply and depending on
there need
the env var BOARD will refer to the current board dirent
for sandbox as we have only one board the board dirent is arch/sandbox/board
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/blackfin/boards/ipe337/config.h')
| -rw-r--r-- | arch/blackfin/boards/ipe337/config.h | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/blackfin/boards/ipe337/config.h b/arch/blackfin/boards/ipe337/config.h new file mode 100644 index 0000000000..aa25d0792d --- /dev/null +++ b/arch/blackfin/boards/ipe337/config.h @@ -0,0 +1,46 @@ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Clock settings + */ + +/* CONFIG_CLKIN_HZ is any value in Hz */ +#if defined(CONFIG_MACH_IPE337_V1) +#define CONFIG_CLKIN_HZ 25000000 +#elif defined(CONFIG_MACH_IPE337_V2) +#define CONFIG_CLKIN_HZ 40000000 +#else +#error "Unknown IPE337 revision" +#endif + +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 10 /* POR default */ +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 /* POR default */ +/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 /* POR default */ + +/* Frequencies selected: 400MHz CCLK / 80MHz SCLK ^= 12.5ns cycle time*/ + +#define AMGCTLVAL 0x1F + +/* no need for speed, currently, leave at defaults */ +#define AMBCTL0VAL 0xFFC2FFC2 +#define AMBCTL1VAL 0xFFC2FFC2 + +#define CONFIG_MEM_MT48LC16M16A2TG_75 1 +#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */ + +#endif /* __CONFIG_H */ |